From patchwork Thu Mar 2 05:24:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63209 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4062995wrd; Wed, 1 Mar 2023 21:51:38 -0800 (PST) X-Google-Smtp-Source: AK7set9hrmTWYc34PUOQt8A/s1Fu6x0Ln86qHIDFhoo2so/rb4yLxr6itTWmh02BXYw6i1SjF/2d X-Received: by 2002:a17:906:af16:b0:8b1:bafe:6135 with SMTP id lx22-20020a170906af1600b008b1bafe6135mr11587508ejb.60.1677736298031; Wed, 01 Mar 2023 21:51:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736298; cv=none; d=google.com; s=arc-20160816; b=gJUB7S+w+OVn6QUAztm4wN+hBrDo+KfgyprRUMcUxoe8mMsLrlNjVta6u86XOL9NmI WnBioomPmr6zIAUa4CcTqrhESXDqMTqTAFAqFhTYivaAOodqi33BWpQJAB+ErqZUJcXP vqVJL2sMoteHq3ITNA//E0sDLJAlbONoPq9Y1KVZifurMzxX3BABuYGYZYilyFOxWH/W cZPmSoKsJbnBHKFbgqSRu/GUgirlbwpIA7Zi9b01nt8Lr820RL6gMYTPM8PEEV0jaS9f BuNJxY4IULSFzibl7/DhRZcZaUgymOjt9U5kW/NAJEDbJ8BmCgN8EZ/HLWWT/5arG2iy wXkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lz0rIzgfQ3UdI4kxn19lGElU0pAx4EZmyexpGqpeLQk=; b=dyATA3twGC5JiBfFmFbrpzmcuST5gEXhjqEe1zWgJuBNlXhujrcnnxQR8WtS7e5Owm OkI8VmettCJnNRZ46Gm1kUx0aJfBbHoAOiQD/92pAnud/SMturYs0pkvHak6h7sEXdmj TYBJfAoa6LXVCqcyp/zuOmvu3yHbxk/7/ENrnInn0ncCbT5FOX2dOXRDySITKTC2mxuP +1NgWiQdLBnWZiNXkNN2TWhiPnEWxLJ7/2byMvSHjSYg00zT5vuv0YvxhoFND3JNBV7U LYu1X0uCN0PLCvcfW1Z5RWJ1iuiyS9jW/qAlHsV/zxKNMikj6ltEGZWhd3cSgsQDKIsT pQ7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MvS+NcCT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i2-20020a50fc02000000b004bcee2b45f9si3700741edr.175.2023.03.01.21.51.14; Wed, 01 Mar 2023 21:51:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MvS+NcCT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229730AbjCBFuv (ORCPT + 99 others); Thu, 2 Mar 2023 00:50:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229696AbjCBFur (ORCPT ); Thu, 2 Mar 2023 00:50:47 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE66A149A8; Wed, 1 Mar 2023 21:50:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736246; x=1709272246; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CJ5cn83oehVUqkHaIiQkGH139f3gJuf37y85qUnwXYY=; b=MvS+NcCTWz/P/JGdBBZx180i+UI49OYJrJnLKHtoDmLWma28RoMjOAzl y1AoHFUayKa2Ua/dwMv1P4+JxbNJffOatKrNjbUh1+jMa02w5AJ0jcEvf AgPsjHM3ubDgun5p4uL3ier4bAsw8CRUcAKlTxjENZp9Erq34yEUx0kD0 BVZ6aJTn4KTiq7a0WxAxPbaQnmXJJLnDBrWUQ66Mzfqs31ax3jRyGAwaB uhonjlT8TSnJu2hLAsDhtE+7+SljxYScJNq9f/InrPKjaFKtlS1zoedxs eI+Tn6i4lnzGVOQ33I4aw8aXK+FzrpUAjP77d9o1gMENSKC2EKDehoQQk Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420886998" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420886998" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530866" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530866" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:45 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 01/34] x86/traps: let common_interrupt() handle IRQ_MOVE_CLEANUP_VECTOR Date: Wed, 1 Mar 2023 21:24:38 -0800 Message-Id: <20230302052511.1918-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234016448911228?= X-GMAIL-MSGID: =?utf-8?q?1759234016448911228?= From: "H. Peter Anvin (Intel)" IRQ_MOVE_CLEANUP_VECTOR is the only one of the system IRQ vectors that is *below* FIRST_SYSTEM_VECTOR. It is a slow path, so just push it into common_interrupt() just before the spurious interrupt handling. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/irq.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 766ffe3ba313..7e125fff45ab 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -248,6 +248,10 @@ DEFINE_IDTENTRY_IRQ(common_interrupt) desc = __this_cpu_read(vector_irq[vector]); if (likely(!IS_ERR_OR_NULL(desc))) { handle_irq(desc, regs); +#ifdef CONFIG_SMP + } else if (vector == IRQ_MOVE_CLEANUP_VECTOR) { + sysvec_irq_move_cleanup(regs); +#endif } else { ack_APIC_irq(); From patchwork Thu Mar 2 05:24:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63211 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063045wrd; Wed, 1 Mar 2023 21:51:48 -0800 (PST) X-Google-Smtp-Source: AK7set8VKamf26fEPPKz43akTr35+w8kPUItM7cZJjgd0+6rXBmshM7V/L4EJwodoKBPKqJ2sxX3 X-Received: by 2002:a05:6402:1147:b0:4af:51b6:fe49 with SMTP id g7-20020a056402114700b004af51b6fe49mr972086edw.13.1677736307788; Wed, 01 Mar 2023 21:51:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736307; cv=none; d=google.com; s=arc-20160816; b=y/pqBrexe3GiGuoD6KYeSt/Qqellh83Uxh/OzE5GF1R5TEFJxHmUOis2BheC9aT9Ix nxa/jBZwDiFM/zNNgiU/LM5HS0NtvcpIHeODWhgjvSGrIC5hfFJFg/HdA9uNXk19kCf+ YB+gtLyCkMKz1esPpN33xigfGy8RWPwmvNtEkvrM4c9TnP8FhA4Zee6/nCl6CndUl9L5 xwZBgu0ti7afPHMMDLHapB4JLUWUlN8B4ZRAuIoXS4CgxtgsO129I8fcbEPjzHb7dHqm PwuIzbXHU8Pp1aymoH1iwggHc1qOVgnpsHCn9GoMBLWV8PQlrsGpIjYSO4pvKj4IvqwM ubyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f6LSyzIE+j8ZDwmNzpZodWWxsGVCExYPC8AW4gHI8uQ=; b=0fyhx4w+2Xdw9sU60Myy2SxURJdhZxwONHrCltdpcxr+aDuDoj1iQVh+Mtyesuz6f+ WWhj4RsyGI1qeO/eL0Ynby6V+/PQ9uTYZq52DMPvoGSMYf2cWCTcLFnM/e9rg5y1hHv3 FYt5WzIRUldhBTNHECncFmz1UrSidR8A7vohG3txPQvBFRWwyTbzyL9Q3hUF+lVx5WXW +b79ZRmf4pzP8e/7XEb8opwho7J3zzQ8AIAQefkj9vv53JCeFzYTi/SngJPg3EvSQBlH 2Nz8J9iZiFBoJM2xUDw8pobaCu2PEx3JfswtOCa3osaTNOHFLuYvn4quu0Q5Awbp11yT DgEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BOt2wo+9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s6-20020a170906bc4600b008c33d2d544fsi2658240ejv.76.2023.03.01.21.51.25; Wed, 01 Mar 2023 21:51:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BOt2wo+9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229812AbjCBFuz (ORCPT + 99 others); Thu, 2 Mar 2023 00:50:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229712AbjCBFus (ORCPT ); Thu, 2 Mar 2023 00:50:48 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 789DD196A4; Wed, 1 Mar 2023 21:50:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736247; x=1709272247; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KhjFgYlexGV9FGtsACYCvXD7b+GVgwBW3pCpHZa0kY0=; b=BOt2wo+99tr2iwcoo5d44PwAK5iCX7jBepZJQ8Ve1ODD4TkD/lgCF2M5 oBTX2Ml3vPWAiHZ8KPCqfOi2oVw8VT6K86fU12ULlmwfpN45xrusUQXb1 Qy2ETt+Q1vavpkTA5KuOsR4JPz5NwcOzZfdoJhQAzeqwObR78lnvHdSxp hWAHe4HTS3ZZuD2jIRz3qKhCKp27H1v1HcTHKUeumYrDBB3fo4EQZMW7/ qj760iohGuVE5z/SSjJ5lFAGHbGYk8/G/elefbDeiivc6n3u1IY0LdWqe gEAkIVaYZX+WP6jRqKwvWFj/ZBYiFdsFuAW5C3LjHbjWVbg3Sqz3SQA7O A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887009" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887009" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530871" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530871" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:45 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 02/34] x86/traps: add a system interrupt table for system interrupt dispatch Date: Wed, 1 Mar 2023 21:24:39 -0800 Message-Id: <20230302052511.1918-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234026897071301?= X-GMAIL-MSGID: =?utf-8?q?1759234026897071301?= From: "H. Peter Anvin (Intel)" Upon receiving an external interrupt, KVM VMX reinjects it through calling the interrupt handler in its IDT descriptor on the current kernel stack, which essentially uses the IDT as an interrupt dispatch table. However the IDT is one of the lowest level critical data structures between a x86 CPU and the Linux kernel, we should avoid using it *directly* whenever possible, espeically in a software defined manner. On x86, external interrupts are divided into the following groups 1) system interrupts 2) external device interrupts With the IDT, system interrupts are dispatched through the IDT directly, while external device interrupts are all routed to the external interrupt dispatch function common_interrupt(), which dispatches external device interrupts through a per-CPU external interrupt dispatch table vector_irq. To eliminate dispatching external interrupts through the IDT, add a system interrupt handler table for dispatching a system interrupt to its corresponding handler directly. Thus a software based dispatch function will be: void external_interrupt(struct pt_regs *regs, u8 vector) { if (is_system_interrupt(vector)) system_interrupt_handlers[vector_to_sysvec(vector)](regs); else /* external device interrupt */ common_interrupt(regs, vector); } What's more, with the Intel FRED (Flexible Return and Event Delivery) architecture, IDT, the hardware based event dispatch table, is gone, and the Linux kernel needs to dispatch events to their handlers with vector to handler mappings, the dispatch function external_interrupt() is also needed. Signed-off-by: H. Peter Anvin (Intel) Co-developed-by: Xin Li Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/idtentry.h | 64 +++++++++++++++++++++++++++------ arch/x86/include/asm/traps.h | 7 ++++ arch/x86/kernel/traps.c | 40 +++++++++++++++++++++ 3 files changed, 100 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentry.h index b241af4ce9b4..2876ddae02bc 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -167,17 +167,22 @@ __visible noinstr void func(struct pt_regs *regs, unsigned long error_code) /** * DECLARE_IDTENTRY_IRQ - Declare functions for device interrupt IDT entry - * points (common/spurious) + * points (common/spurious) and their corresponding + * software based dispatch handlers in the non-noinstr + * text section * @vector: Vector number (ignored for C) * @func: Function name of the entry point * - * Maps to DECLARE_IDTENTRY_ERRORCODE() + * Maps to DECLARE_IDTENTRY_ERRORCODE(), plus a dispatch function prototype */ #define DECLARE_IDTENTRY_IRQ(vector, func) \ - DECLARE_IDTENTRY_ERRORCODE(vector, func) + DECLARE_IDTENTRY_ERRORCODE(vector, func); \ + void dispatch_##func(struct pt_regs *regs, unsigned long error_code) /** * DEFINE_IDTENTRY_IRQ - Emit code for device interrupt IDT entry points + * and their corresponding software based dispatch + * handlers in the non-noinstr text section * @func: Function name of the entry point * * The vector number is pushed by the low level entry stub and handed @@ -187,6 +192,9 @@ __visible noinstr void func(struct pt_regs *regs, unsigned long error_code) * irq_enter/exit_rcu() are invoked before the function body and the * KVM L1D flush request is set. Stack switching to the interrupt stack * has to be done in the function body if necessary. + * + * dispatch_func() is a software based dispatch handler in the non-noinstr + * text section. */ #define DEFINE_IDTENTRY_IRQ(func) \ static void __##func(struct pt_regs *regs, u32 vector); \ @@ -204,31 +212,48 @@ __visible noinstr void func(struct pt_regs *regs, \ irqentry_exit(regs, state); \ } \ \ +void dispatch_##func(struct pt_regs *regs, unsigned long error_code) \ +{ \ + u32 vector = (u32)(u8)error_code; \ + \ + kvm_set_cpu_l1tf_flush_l1d(); \ + run_irq_on_irqstack_cond(__##func, regs, vector); \ +} \ + \ static noinline void __##func(struct pt_regs *regs, u32 vector) /** * DECLARE_IDTENTRY_SYSVEC - Declare functions for system vector entry points + * and their corresponding software based dispatch + * handlers in the non-noinstr text section * @vector: Vector number (ignored for C) * @func: Function name of the entry point * - * Declares three functions: + * Declares four functions: * - The ASM entry point: asm_##func * - The XEN PV trap entry point: xen_##func (maybe unused) * - The C handler called from the ASM entry point + * - The C handler used in the system interrupt handler table * - * Maps to DECLARE_IDTENTRY(). + * Maps to DECLARE_IDTENTRY(), plus a dispatch table function prototype */ #define DECLARE_IDTENTRY_SYSVEC(vector, func) \ - DECLARE_IDTENTRY(vector, func) + DECLARE_IDTENTRY(vector, func); \ + void dispatch_table_##func(struct pt_regs *regs) /** * DEFINE_IDTENTRY_SYSVEC - Emit code for system vector IDT entry points + * and their corresponding software based dispatch + * handlers in the non-noinstr text section * @func: Function name of the entry point * * irqentry_enter/exit() and irq_enter/exit_rcu() are invoked before the * function body. KVM L1D flush request is set. * - * Runs the function on the interrupt stack if the entry hit kernel mode + * Runs the function on the interrupt stack if the entry hit kernel mode. + * + * dispatch_table_func() is used in the system interrupt handler table for + * system interrupts dispatching. */ #define DEFINE_IDTENTRY_SYSVEC(func) \ static void __##func(struct pt_regs *regs); \ @@ -244,11 +269,19 @@ __visible noinstr void func(struct pt_regs *regs) \ irqentry_exit(regs, state); \ } \ \ +void dispatch_table_##func(struct pt_regs *regs) \ +{ \ + kvm_set_cpu_l1tf_flush_l1d(); \ + run_sysvec_on_irqstack_cond(__##func, regs); \ +} \ + \ static noinline void __##func(struct pt_regs *regs) /** * DEFINE_IDTENTRY_SYSVEC_SIMPLE - Emit code for simple system vector IDT - * entry points + * entry points and their corresponding + * software based dispatch handlers in + * the non-noinstr text section * @func: Function name of the entry point * * Runs the function on the interrupted stack. No switch to IRQ stack and @@ -256,6 +289,9 @@ static noinline void __##func(struct pt_regs *regs) * * Only use for 'empty' vectors like reschedule IPI and KVM posted * interrupt vectors. + * + * dispatch_table_func() is used in the system interrupt handler table for + * system interrupts dispatching. */ #define DEFINE_IDTENTRY_SYSVEC_SIMPLE(func) \ static __always_inline void __##func(struct pt_regs *regs); \ @@ -273,6 +309,14 @@ __visible noinstr void func(struct pt_regs *regs) \ irqentry_exit(regs, state); \ } \ \ +void dispatch_table_##func(struct pt_regs *regs) \ +{ \ + __irq_enter_raw(); \ + kvm_set_cpu_l1tf_flush_l1d(); \ + __##func (regs); \ + __irq_exit_raw(); \ +} \ + \ static __always_inline void __##func(struct pt_regs *regs) /** @@ -634,9 +678,7 @@ DECLARE_IDTENTRY(X86_TRAP_VE, exc_virtualization_exception); /* Device interrupts common/spurious */ DECLARE_IDTENTRY_IRQ(X86_TRAP_OTHER, common_interrupt); -#ifdef CONFIG_X86_LOCAL_APIC DECLARE_IDTENTRY_IRQ(X86_TRAP_OTHER, spurious_interrupt); -#endif /* System vector entry points */ #ifdef CONFIG_X86_LOCAL_APIC @@ -647,7 +689,7 @@ DECLARE_IDTENTRY_SYSVEC(X86_PLATFORM_IPI_VECTOR, sysvec_x86_platform_ipi); #endif #ifdef CONFIG_SMP -DECLARE_IDTENTRY(RESCHEDULE_VECTOR, sysvec_reschedule_ipi); +DECLARE_IDTENTRY_SYSVEC(RESCHEDULE_VECTOR, sysvec_reschedule_ipi); DECLARE_IDTENTRY_SYSVEC(IRQ_MOVE_CLEANUP_VECTOR, sysvec_irq_move_cleanup); DECLARE_IDTENTRY_SYSVEC(REBOOT_VECTOR, sysvec_reboot); DECLARE_IDTENTRY_SYSVEC(CALL_FUNCTION_SINGLE_VECTOR, sysvec_call_function_single); diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 47ecfff2c83d..28c8ba5fd81c 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -47,4 +47,11 @@ void __noreturn handle_stack_overflow(struct pt_regs *regs, struct stack_info *info); #endif +/* + * How system interrupt handlers are called. + */ +#define DECLARE_SYSTEM_INTERRUPT_HANDLER(f) \ + void f (struct pt_regs *regs) +typedef DECLARE_SYSTEM_INTERRUPT_HANDLER((*system_interrupt_handler)); + #endif /* _ASM_X86_TRAPS_H */ diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index d317dc3d06a3..e4bdebdf05dd 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1451,6 +1451,46 @@ DEFINE_IDTENTRY_SW(iret_error) } #endif +#define SYSV(x,y) [(x) - FIRST_SYSTEM_VECTOR] = y + +static system_interrupt_handler system_interrupt_handlers[NR_SYSTEM_VECTORS] = { +#ifdef CONFIG_SMP + SYSV(RESCHEDULE_VECTOR, dispatch_table_sysvec_reschedule_ipi), + SYSV(CALL_FUNCTION_VECTOR, dispatch_table_sysvec_call_function), + SYSV(CALL_FUNCTION_SINGLE_VECTOR, dispatch_table_sysvec_call_function_single), + SYSV(REBOOT_VECTOR, dispatch_table_sysvec_reboot), +#endif + +#ifdef CONFIG_X86_THERMAL_VECTOR + SYSV(THERMAL_APIC_VECTOR, dispatch_table_sysvec_thermal), +#endif + +#ifdef CONFIG_X86_MCE_THRESHOLD + SYSV(THRESHOLD_APIC_VECTOR, dispatch_table_sysvec_threshold), +#endif + +#ifdef CONFIG_X86_MCE_AMD + SYSV(DEFERRED_ERROR_VECTOR, dispatch_table_sysvec_deferred_error), +#endif + +#ifdef CONFIG_X86_LOCAL_APIC + SYSV(LOCAL_TIMER_VECTOR, dispatch_table_sysvec_apic_timer_interrupt), + SYSV(X86_PLATFORM_IPI_VECTOR, dispatch_table_sysvec_x86_platform_ipi), +# ifdef CONFIG_HAVE_KVM + SYSV(POSTED_INTR_VECTOR, dispatch_table_sysvec_kvm_posted_intr_ipi), + SYSV(POSTED_INTR_WAKEUP_VECTOR, dispatch_table_sysvec_kvm_posted_intr_wakeup_ipi), + SYSV(POSTED_INTR_NESTED_VECTOR, dispatch_table_sysvec_kvm_posted_intr_nested_ipi), +# endif +# ifdef CONFIG_IRQ_WORK + SYSV(IRQ_WORK_VECTOR, dispatch_table_sysvec_irq_work), +# endif + SYSV(SPURIOUS_APIC_VECTOR, dispatch_table_sysvec_spurious_apic_interrupt), + SYSV(ERROR_APIC_VECTOR, dispatch_table_sysvec_error_interrupt), +#endif +}; + +#undef SYSV + void __init trap_init(void) { /* Init cpu_entry_area before IST entries are set up */ From patchwork Thu Mar 2 05:24:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63210 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063020wrd; Wed, 1 Mar 2023 21:51:42 -0800 (PST) X-Google-Smtp-Source: AK7set+lVbfHBaCbHA6i7PfSOHIa44u3+nnxdi/eRxQxK6Farqf/CUjzKNOaNJiGo1H+alCQW2AM X-Received: by 2002:a05:6402:10d5:b0:4ab:4c36:463c with SMTP id p21-20020a05640210d500b004ab4c36463cmr9935250edu.16.1677736301871; Wed, 01 Mar 2023 21:51:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736301; cv=none; d=google.com; s=arc-20160816; b=FTVb0X37JeVvkVBrq6Ke/JLhdmKn2Hvizn2MidzMfVBX8FmIYEbyy/V4EVncbqFpsY LerT8Pr9NUHdl23S2cxU+TZprZfIfvpIPOJBZocdUlcs8cpRtTW45ucdIb9CtWrqlEmC l8qzJnXlpNcGZg/3skHcbS7Hx3BokqnwFRRoIaRpvGla7jEbEzzk9kbePD0FsNKiWJ7T Ous7vxVp9Ao8JUWmpAZ2ACD3twBTnwfFoI3wFN0LCpPghIehvS4PaRJIfSSbjb5FKRpU lW+oUVl47j96U/9pGWidVlf5UJ/PKi0AC7r7eTt6pbWPf7uet3qoGgBcIlDJTHoTezI0 pmsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+beR+ZTmYij8mFjI6HP4THUvG6do3ZnfXsCvyZZ5Gsg=; b=X6p7tlgmzwOVfbhW5zAStHZR+qvEpuJZfOljaMOXpurTHkOX1FOJgfAuad8uoMzshz E5fAemk7V1hOIDnHMm8/ymUKkovEyfjx2APAFn4C7ox6dx6zjtyPAQlSvkpfprLKZ2gu 7/sZx816nabJPbnkWvlWqVczugoZ8w4ydNJJ8FyWjWykDWAaxrQJIFWrC7mffE1meTIa Rc6EJFFI5ccNn3x3Pmwc4/rwGaFJXp9zmtPtCyPZH+l2naXjF4mdTMtKPxPtwWHevNyq RVhjR1yOOn9d5XGuH2cohyZLru8d4C8HfqR33VLy0bg9Wi4qDZOOSS9O15mXCgPaRjaa wSvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kMOJ5WCB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bm3-20020a0564020b0300b004af70a5422dsi5432189edb.446.2023.03.01.21.51.18; Wed, 01 Mar 2023 21:51:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kMOJ5WCB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229773AbjCBFux (ORCPT + 99 others); Thu, 2 Mar 2023 00:50:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229708AbjCBFus (ORCPT ); Thu, 2 Mar 2023 00:50:48 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE5D41448A; Wed, 1 Mar 2023 21:50:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736247; x=1709272247; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ayij8j+gLNL7AeS8JLQOEBRiE7R/c3m5AaTu2SyyhUQ=; b=kMOJ5WCB2dwpDS1huuikwoFCuLVHdgz5aWOIUnIZIsgzEAP79lzvMVTh xZoW1qBghyAokY7eEXMGn3WTosJpqxHyhM67XS0d/rXnnpyZBMFB06+2/ np00WDgdVlQQ+SQMNE4ivY69xQa1aSttU8wCwp409kPMmRUZR15KcWDKG pXVNPTIzgSfz6qoWYZXBJqGiYzY430syze7NBTkgaiA9/4n2QiEcTW7Dk 4g2Bn2VGvEJunZqMIVujlaKvcZtVB666+7nYVIWS+LoVXD2JFTvABt84O R7vsMVqlRk7CPKep/XPX25r6cIlry4mGpEcP8Wl/7NbzL+aAA8tM+y/DD g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887029" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887029" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530874" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530874" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:45 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 03/34] x86/traps: add install_system_interrupt_handler() Date: Wed, 1 Mar 2023 21:24:40 -0800 Message-Id: <20230302052511.1918-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234020598661562?= X-GMAIL-MSGID: =?utf-8?q?1759234020598661562?= Some kernel components install system interrupt handlers into the IDT, and we need to do the same for system_interrupt_handlers. A new function install_system_interrupt_handler() is added to install a system interrupt handler into both the IDT and system_interrupt_handlers. Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/traps.h | 2 ++ arch/x86/kernel/cpu/acrn.c | 7 +++++-- arch/x86/kernel/cpu/mshyperv.c | 22 ++++++++++++++-------- arch/x86/kernel/kvm.c | 4 +++- arch/x86/kernel/traps.c | 8 ++++++++ drivers/xen/events/events_base.c | 5 ++++- 6 files changed, 36 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 28c8ba5fd81c..46f5e4e2a346 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -41,6 +41,8 @@ void math_emulate(struct math_emu_info *); bool fault_in_kernel_space(unsigned long address); +void install_system_interrupt_handler(unsigned int n, const void *asm_addr, const void *addr); + #ifdef CONFIG_VMAP_STACK void __noreturn handle_stack_overflow(struct pt_regs *regs, unsigned long fault_address, diff --git a/arch/x86/kernel/cpu/acrn.c b/arch/x86/kernel/cpu/acrn.c index 485441b7f030..9351bf183a9e 100644 --- a/arch/x86/kernel/cpu/acrn.c +++ b/arch/x86/kernel/cpu/acrn.c @@ -18,6 +18,7 @@ #include #include #include +#include static u32 __init acrn_detect(void) { @@ -26,8 +27,10 @@ static u32 __init acrn_detect(void) static void __init acrn_init_platform(void) { - /* Setup the IDT for ACRN hypervisor callback */ - alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_acrn_hv_callback); + /* Install system interrupt handler for ACRN hypervisor callback */ + install_system_interrupt_handler(HYPERVISOR_CALLBACK_VECTOR, + asm_sysvec_acrn_hv_callback, + sysvec_acrn_hv_callback); x86_platform.calibrate_tsc = acrn_get_tsc_khz; x86_platform.calibrate_cpu = acrn_get_tsc_khz; diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index f36dc2f796c5..63282f4bfdcd 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -487,19 +488,24 @@ static void __init ms_hyperv_init_platform(void) */ x86_platform.apic_post_init = hyperv_init; hyperv_setup_mmu_ops(); - /* Setup the IDT for hypervisor callback */ - alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback); - /* Setup the IDT for reenlightenment notifications */ + /* Install system interrupt handler for hypervisor callback */ + install_system_interrupt_handler(HYPERVISOR_CALLBACK_VECTOR, + asm_sysvec_hyperv_callback, + sysvec_hyperv_callback); + + /* Install system interrupt handler for reenlightenment notifications */ if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { - alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR, - asm_sysvec_hyperv_reenlightenment); + install_system_interrupt_handler(HYPERV_REENLIGHTENMENT_VECTOR, + asm_sysvec_hyperv_reenlightenment, + sysvec_hyperv_reenlightenment); } - /* Setup the IDT for stimer0 */ + /* Install system interrupt handler for stimer0 */ if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) { - alloc_intr_gate(HYPERV_STIMER0_VECTOR, - asm_sysvec_hyperv_stimer0); + install_system_interrupt_handler(HYPERV_STIMER0_VECTOR, + asm_sysvec_hyperv_stimer0, + sysvec_hyperv_stimer0); } # ifdef CONFIG_SMP diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 1cceac5984da..5c684df6de7a 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -829,7 +829,9 @@ static void __init kvm_guest_init(void) if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF_INT) && kvmapf) { static_branch_enable(&kvm_async_pf_enabled); - alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_kvm_asyncpf_interrupt); + install_system_interrupt_handler(HYPERVISOR_CALLBACK_VECTOR, + asm_sysvec_kvm_asyncpf_interrupt, + sysvec_kvm_asyncpf_interrupt); } #ifdef CONFIG_SMP diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index e4bdebdf05dd..c0f7666140da 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1491,6 +1491,14 @@ static system_interrupt_handler system_interrupt_handlers[NR_SYSTEM_VECTORS] = { #undef SYSV +void __init install_system_interrupt_handler(unsigned int n, const void *asm_addr, const void *addr) +{ + BUG_ON(n < FIRST_SYSTEM_VECTOR); + + system_interrupt_handlers[n - FIRST_SYSTEM_VECTOR] = (system_interrupt_handler)addr; + alloc_intr_gate(n, asm_addr); +} + void __init trap_init(void) { /* Init cpu_entry_area before IST entries are set up */ diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c index c7715f8bd452..cf1a5ca3bf62 100644 --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include #endif @@ -2249,7 +2250,9 @@ static __init void xen_alloc_callback_vector(void) return; pr_info("Xen HVM callback vector for event delivery is enabled\n"); - alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_xen_hvm_callback); + install_system_interrupt_handler(HYPERVISOR_CALLBACK_VECTOR, + asm_sysvec_xen_hvm_callback, + sysvec_xen_hvm_callback); } #else void xen_setup_callback_vector(void) {} From patchwork Thu Mar 2 05:24:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63214 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063145wrd; Wed, 1 Mar 2023 21:52:13 -0800 (PST) X-Google-Smtp-Source: AK7set8KycB3BNLrLMTulm30h8Cz4VouyJZUyEnmd+3sy1iAnL1OItrr0PyB8lo+hL1CK9e/BQfj X-Received: by 2002:a17:906:5d16:b0:8af:3fef:52c9 with SMTP id g22-20020a1709065d1600b008af3fef52c9mr13991202ejt.22.1677736333654; Wed, 01 Mar 2023 21:52:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736333; cv=none; d=google.com; s=arc-20160816; b=unjyQ5k0+cXAk3ve7O12XpM7K9WSGbqWIZ8pw2+/wwmtY2Zt1GuSDc1mI2l0TJ7DGk hK4M7DyY1JItlKzc/99uGc0e6C0DUMHBm8NnFAkqehg9ws/qNaf8pMg3CwAcJVCp7Bkv zFukUd9NXX/9Ik/Ze6eYGSKJb4B62aEckNnRG9KP3WDz70tEFbUei/z46/UQXzT4gHkS snjUqlcWSxo8yaMOqp27tIQLtVk9cjU84pTXshauZmuBPAtRtetjQKF1tMHfpI/rYjFQ t2dSBye0bEK6ke471yrEeiFLTOAnMdM2nMCBzrocTk8S3R14x89VlEur7VPNRGcBxgdL TqCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rIemuu6QZ5e7zz1ZmPXxi8UM/1xuDAEOyCDdvKuC//8=; b=ylavK1NKsmpQQlSePMvIwAYHdA3p75R/kUU5II++gNN7X6jaMoE9J6pUf+T11eF3Py hGCFpkBSZ+Y1v5hNCRpKQS78A+3p9PfGBjNqA3Rsv20J/B3LtL3+YHFP02SqCIYx1fa8 YkXqAUmKDaKRVpMGKDwbCmm0pISLa1uj/6fDDg2yh2sH1zcuhJrUWCvv/5DbvyF8bnWd PnCxIAdX7E/NSl7bG4oB2NHF4cQ1U/jWa0v6YCpHJPlU7QXeRo2q10ZGVGFTUcW5iTSN 4IYePeXdrNHN9WuAiXHPt4kGMk0j6xVaYfloxUtIJ2kkltDhXb3+8VpUhGsJ6lVNiqUw FGvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=UwF2KvFf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id js19-20020a17090797d300b008e1a91a7b8csi3340573ejc.968.2023.03.01.21.51.49; Wed, 01 Mar 2023 21:52:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=UwF2KvFf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229900AbjCBFvE (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229733AbjCBFut (ORCPT ); Thu, 2 Mar 2023 00:50:49 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF942149A8; Wed, 1 Mar 2023 21:50:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736248; x=1709272248; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0uFNdDkUqLm94ae1U1jdZV+knFHrk6JmxBSxXFP+9lc=; b=UwF2KvFfHcJTiFByhahOJlnBhnaZCZIwahxEuqlpr5xqKzDPAqkFt4OB abTLQvLSEav16cogCTo7brCSsx9Hh1M71OVGc9JKd2Xbvhxj/vd88mt5/ mtT4KD1ZnmvY8lyL7wL2hFXKikU2sqif0BTGVEccDLs1WSmSVSACl6HMP EJuY5U7bEuECtyagI6SsqLEYM8nmWKXWcylbSHFlQaI0A+iK+J7dKEk4n V6ACxavPYJs9Q+H8yKqgMzGC6odnOnzN/xzMW+w/A2IVVDWrwfjbBSIuD 2+XfeIMqOfeK/OY4EN+SZRk+pUMzsrr6wTo50xgFa/SAs3nTJ1ZM4BCA5 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887033" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887033" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530877" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530877" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:45 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 04/34] x86/traps: add external_interrupt() to dispatch external interrupts Date: Wed, 1 Mar 2023 21:24:41 -0800 Message-Id: <20230302052511.1918-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234053948746604?= X-GMAIL-MSGID: =?utf-8?q?1759234053948746604?= From: "H. Peter Anvin (Intel)" Add external_interrupt() to dispatch external interrupts to their handlers. If an external interrupt is a system interrupt, dipatch it through system_interrupt_handler_table, otherwise call into dispatch_common_interrupt(). Signed-off-by: H. Peter Anvin (Intel) Co-developed-by: Xin Li Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/traps.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index c0f7666140da..31ad645be2fb 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1499,6 +1499,47 @@ void __init install_system_interrupt_handler(unsigned int n, const void *asm_add alloc_intr_gate(n, asm_addr); } +#ifndef CONFIG_X86_LOCAL_APIC +/* + * Used when local APIC is not compiled into the kernel, but + * external_interrupt() needs dispatch_spurious_interrupt(). + */ +DEFINE_IDTENTRY_IRQ(spurious_interrupt) +{ + pr_info("Spurious interrupt (vector 0x%x) on CPU#%d, should never happen.\n", + vector, smp_processor_id()); +} +#endif + +/* + * External interrupt dispatch function. + * + * Until/unless dispatch_common_interrupt() can be taught to deal with the + * special system vectors, split the dispatch. + * + * Note: dispatch_common_interrupt() already deals with IRQ_MOVE_CLEANUP_VECTOR. + */ +int external_interrupt(struct pt_regs *regs, unsigned int vector) +{ + unsigned int sysvec = vector - FIRST_SYSTEM_VECTOR; + + if (vector < FIRST_EXTERNAL_VECTOR) { + pr_err("invalid external interrupt vector %d\n", vector); + return -EINVAL; + } + + if (sysvec < NR_SYSTEM_VECTORS) { + if (system_interrupt_handlers[sysvec]) + system_interrupt_handlers[sysvec](regs); + else + dispatch_spurious_interrupt(regs, vector); + } else { + dispatch_common_interrupt(regs, vector); + } + + return 0; +} + void __init trap_init(void) { /* Init cpu_entry_area before IST entries are set up */ From patchwork Thu Mar 2 05:24:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63212 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063101wrd; Wed, 1 Mar 2023 21:52:02 -0800 (PST) X-Google-Smtp-Source: AK7set8mGxhYldg7aQji4H6kGTXt0lcPsPmmhJBJ+qW0QmgVZkJfzu9quXnfhDQ8ZmtToGzfn+uz X-Received: by 2002:aa7:c2c9:0:b0:4c0:e156:7954 with SMTP id m9-20020aa7c2c9000000b004c0e1567954mr108414edp.34.1677736322087; Wed, 01 Mar 2023 21:52:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736322; cv=none; d=google.com; s=arc-20160816; b=jNSzLpvOBJur7rpYZBLjatbwHJ6wcGYjL3wVQghxs5GhDoDO8+q9KQ314p8oPzsyzr Av/WtaKLafo83gFs3UEHq+uEjCo8WPPZAdxQXdpILgjVnxRp3AETAs6DNcKGbJ1o6N95 JKfpT/s8elCss394qifINQHmzG9RrX4PGb2s9x4njRcMT2iwyjbwMdTlUPfI8Q2iUnJA 7fCsecNzUuLMhCS8+atKve2/iNDeyMAiXdGsBdF4tSDyND1NcBDh/9nOORaNSwj9+/x3 +0HVUBzaY+WPLMokNQK93uH+SNgiLOGm8I6LGR1NwF0dasatfNv+dfEU7PZGeYyeFdnj mlHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ur43HcRHxkNKt7OW4fFLQmYxPRkbgPmxJPZDLkTVcCQ=; b=c8GBHqrSIcZHwxdb2l2fZtrqZlC+oNL6vaR/fjcLSwgYWpYhx5IBppUt3c9wAiSLLm Yl+ZA9E5IoYau7Nq+w7tjqv1fU1yn6/Rp1SIViWe/XvUHXrGhD5VS5vsRzuGyP/Ddtsp lO3Ndj64jJ2efLDxkR2xab+BnyP3e6UcUq3iqbmmM9ox9IDY+WD9J5CaYvcrIt34mVaL juCGHNTu1144AjbFVOg8O7u2ZbCWUOslequuFPlNwxmYxadzphKueUHCenHdHKRLhs/r 1PovQn3IWjHIHSDlfcbekRaqztjs7R79h68DFKwf5powVRaQfRTKpoxLLY2qS0BoYAgw ORQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DDGxUA2X; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b2-20020a056402138200b004aba73a1814si841365edv.6.2023.03.01.21.51.39; Wed, 01 Mar 2023 21:52:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DDGxUA2X; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229870AbjCBFu5 (ORCPT + 99 others); Thu, 2 Mar 2023 00:50:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229714AbjCBFut (ORCPT ); Thu, 2 Mar 2023 00:50:49 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA7771A974; Wed, 1 Mar 2023 21:50:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736247; x=1709272247; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=n5Ln656oJnJmTILrzTkjrWNEu25opZektOWvxvWKy2E=; b=DDGxUA2XEVd3Cqm0Nhhf5MqfsXS/gB3fw73sK0yrbbL5YQKkAgWrs8o8 Egc6Ky0vAfj8cTyEr0MCVl1mmmXuRZGjc8h4+kpX3VNh0GJ/g3Hxi2Y4M 7yA1F00ryGF5Ih0vfcoJPR8lrsdKzIEj5llIpbaDSPORSA/W4AF6l3ADD 1So99IuZMk546CsdFx4h7WenDpHkFUurWgNMDcRA3ltn9iygXRiUxbw0W X958xNPEri+ovDMFASxRStJY1ycfPPz57GQkhZLMkCyp5BW9HYvINTRNE +OpdjuUatqr6bmCI7BayAp46nksdcKFNqxOcdvc2NnkhCeij7JY1CCEys Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887052" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887052" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530884" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530884" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:45 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 05/34] x86/traps: export external_interrupt() for VMX IRQ reinjection Date: Wed, 1 Mar 2023 21:24:42 -0800 Message-Id: <20230302052511.1918-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234041977907210?= X-GMAIL-MSGID: =?utf-8?q?1759234041977907210?= To eliminate dispatching IRQ through the IDT, export external_interrupt() for VMX IRQ reinjection. Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/traps.h | 2 ++ arch/x86/kernel/traps.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 46f5e4e2a346..da4c21ed68b4 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -56,4 +56,6 @@ void __noreturn handle_stack_overflow(struct pt_regs *regs, void f (struct pt_regs *regs) typedef DECLARE_SYSTEM_INTERRUPT_HANDLER((*system_interrupt_handler)); +int external_interrupt(struct pt_regs *regs, unsigned int vector); + #endif /* _ASM_X86_TRAPS_H */ diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 31ad645be2fb..cebba1f49e19 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1540,6 +1540,20 @@ int external_interrupt(struct pt_regs *regs, unsigned int vector) return 0; } +#if IS_ENABLED(CONFIG_KVM_INTEL) +/* + * KVM VMX reinjects IRQ on its current stack, it's a sync call + * thus the values in the pt_regs structure are not used in + * executing IRQ handlers, except cs.RPL and flags.IF, which + * are both always 0 in the VMX IRQ reinjection context. + * + * However, the pt_regs structure is sometimes used in stack + * dump, e.g., show_regs(). So let the caller, i.e., KVM VMX + * decide how to initialize the input pt_regs structure. + */ +EXPORT_SYMBOL_GPL(external_interrupt); +#endif + void __init trap_init(void) { /* Init cpu_entry_area before IST entries are set up */ From patchwork Thu Mar 2 05:24:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63213 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063106wrd; Wed, 1 Mar 2023 21:52:02 -0800 (PST) X-Google-Smtp-Source: AK7set+HDN3GoPdzG9YmBYa5+jByke8rhRV3txiR1hZeSV5mwsGcoAgSUjTXEIOgg57oBfmAiMeq X-Received: by 2002:a17:906:e99:b0:8f1:dfa5:8117 with SMTP id p25-20020a1709060e9900b008f1dfa58117mr8346728ejf.51.1677736322626; Wed, 01 Mar 2023 21:52:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736322; cv=none; d=google.com; s=arc-20160816; b=tcyRCGZZpIR6vl5M64aQuo/6frF2LA7rmWxwmG2lu+GVxK/lZpUfOaoKT0kjhOYZM0 k97n4W5d4WQLJ5JyeZks3BGkPSihFWePxHMtHWBuCWVdIa88IUArhPT7vml+NgS3hthU 4ZsTuT4sQQELlRlHE4Wau4TYhwi261YxPzgBzIFOI1xB/TRn/wuBFhT1x6pwQD1+DBrd EgXExvky3G7Duh7CgClWibbXksXzMFxxdY6buzFbVAJHa3M0oXk6Hq3feAJxVMXA7mwj 4QATgP0KO7liJc7HH8BtzmUBIvE+STq38TQFtJYQomXMGlLKFvbxE9o8ZiODvclX+5l9 gQ0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=elR6gv7x2KRkhkEb5mXhzjhgXAhgUl9+ZReHm6RX/ac=; b=TA/uMGxs3I+SZaP2+NHj3ZkRJvNA7Vd5D730mGpQP/e1S1DjOc+Ez2wvAbEfl1OhYk mznVvvcHcGIK7W08R18gDQNffRIzD7QarzW0NASyxtlPL4V/YD/OLKCPXfuEq69JAwvX mDtkCxIFBm8xa/arEhnwcgq9ujsa5ej8yXp24lHYzPfApW2IY/adj3KT9qM/wZMR/oFM hsSRbNFGQ9S1sVZMFBhndl5rXPLsJyyv0pdg1udlerZXczxCOdYnF+CTr8sAYaa5afuj JfbiaKNP6vaLnV0s7KtyIDFJ1JWGSZ2dH3PqZj0DkxDyf3lk1N7oEVWFxjh0+lYORIKv Wiqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=QEuNPJk7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id nb11-20020a1709071c8b00b009087dc51377si210184ejc.903.2023.03.01.21.51.39; Wed, 01 Mar 2023 21:52:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=QEuNPJk7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229888AbjCBFvB (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229734AbjCBFuu (ORCPT ); Thu, 2 Mar 2023 00:50:50 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF9C31E5C6; Wed, 1 Mar 2023 21:50:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736248; x=1709272248; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4FK4WqdWHUwbUV2bYLBoNlxt9vIvY1YGaf10KKshT3E=; b=QEuNPJk7TFPgZguX1BJPB+Co6KQ/yUPCfkcPaqdzRIBDPFXhEe4SfPGI iqhGOg53jHk/+BV0P4fTjkf3jGD/WLto0ieNWUoocdz89jf1Vh3uaBsLF 1366sh+1yOa/bg2eXF8FKO034FGKyiWnyo/LfTZYWLWnrpxJAitSVvECy rHQkQDEN5G4ygbS/tBkubb6ew2nB4cGnhn693XhsgoPnKNLBV0Esyo9YY MgsWX2epgdplGpQivfBJgMI3NHo0HfNjHhC43Vw5PROwejtrsTCv61Kro F254YkKlS9r9qO+meCgnFKQTI2QHIfMds1nJEkdNHpp1II93vn+izXrUP w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887059" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887059" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530887" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530887" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:46 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 06/34] x86/cpufeature: add the cpu feature bit for FRED Date: Wed, 1 Mar 2023 21:24:43 -0800 Message-Id: <20230302052511.1918-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234042199334626?= X-GMAIL-MSGID: =?utf-8?q?1759234042199334626?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for FRED (Flexible Return and Event Delivery). The Intel flexible return and event delivery (FRED) architecture defines simple new transitions that change privilege level (ring transitions). The FRED architecture was designed with the following goals: 1) Improve overall performance and response time by replacing event delivery through the interrupt descriptor table (IDT event delivery) and event return by the IRET instruction with lower latency transitions. 2) Improve software robustness by ensuring that event delivery establishes the full supervisor context and that event return establishes the full user context. The new transitions defined by the FRED architecture are FRED event delivery and, for returning from events, two FRED return instructions. FRED event delivery can effect a transition from ring 3 to ring 0, but it is used also to deliver events incident to ring 0. One FRED instruction (ERETU) effects a return from ring 0 to ring 3, while the other (ERETS) returns while remaining in ring 0. Search for the latest FRED spec in most search engines with this search pattern: site:intel.com FRED (flexible return and event delivery) specification Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 73c9672c123b..1fa444478d33 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -318,6 +318,7 @@ #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */ #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */ #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index b70111a75688..b2218a7a0927 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ From patchwork Thu Mar 2 05:24:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63232 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063808wrd; Wed, 1 Mar 2023 21:54:13 -0800 (PST) X-Google-Smtp-Source: AK7set8kdY/oXGCVY6cP+TuMI0KSDze6M33NSQEJ5z5zGbxLBV0Ai9372qsw+Zz9mLKEdPs+5e0y X-Received: by 2002:a17:906:8302:b0:8a4:7fb9:5658 with SMTP id j2-20020a170906830200b008a47fb95658mr11017407ejx.55.1677736452866; Wed, 01 Mar 2023 21:54:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736452; cv=none; d=google.com; s=arc-20160816; b=IYWkvTs5mGDOzGSqYZl3HZSrldX9XM9Klm0l7KTM1k2F6wMsir+hbdduXW8Ydbw82o fA5v+PdRZmpOCpYID78IlJI1homgSVMYh0j588erCS87eidzk6Rx2Y3iDIMuDAnCKXPH vXkuhMezpE7EpA/DltOlpv+XBnZQkXRJJNcdvzAte1uIcjsfHQyWUL7yHWYZNGCnj+I8 o+nym3yADNNtVY/Luw+CdfJVHaaTrtG/9JwbnvrcCvuGU910SWR9F4aOznkHIwuQALOh YZYcWk+nKXEzJTcT8M6xDuUzz3xpqqmHuL/15oa2hsOCe1cpMwFVZ0evCQ+koFYJDLbg dxNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OnPWU3zKvAFN5zCINdgJhSm8PRbtANkhAuSAcv2ya+Y=; b=J8nbr2h7yyLGRn/6xGc2njguIHBn60vA3Ciq0RMe21B/UqkpPIAGsvxAUzV0+iPcBc HHlQgrvDGV7tTkYNjNgnLn/ObpoJ2qQpoZl03who1TsYyNOkFE8anEsfzJ0YEtbhKslL 7lVp548fGJcLkyxzfG5drWuTm9mhRRyz6KB70k6ZvkvnSZB+BvZaot5nDpcrPondzSsD o2oplZXjn4yqvLHg8LE5Lb9WKsVhMsPIycAg15OegTegBcDdlS0CX2pPc9bIKWj49Zu2 3X1H3n/g/jPXocmj5p0ZTj7kpTuJFi8hLpJ8DF+whZYSgpwtjLom9MOEhNUMo7s56q4Q yUfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=UyZqgT5j; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o15-20020a170906600f00b008d68d018141si13359678ejj.402.2023.03.01.21.53.50; Wed, 01 Mar 2023 21:54:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=UyZqgT5j; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229925AbjCBFvK (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229800AbjCBFuz (ORCPT ); Thu, 2 Mar 2023 00:50:55 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65A274BE9D; Wed, 1 Mar 2023 21:50:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736253; x=1709272253; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9JZohEEZ3OOYA+uz2zlIPReipLAVM4kv9u7LWFHKKew=; b=UyZqgT5jbK1A0GHEiOyK4VfOWeOFsa29A1d1tmiqVt7tuwAOW733vVSv hbGCnssN0iOdrCDhAt2aWR0mltaNs9ZIDNq8wnSVt3j9KHeZYKbrYW2MK 9+klphCrFIdGHarkgg1a6l+9itcPunjlACM05L5QyFvPHkD5u06F+36Oi Uzon/KLGvqAYThFXg5ntekpHU7Hjuzya5fdYWIAfCRhbh/ChXW5huCMlA rW5K8boDj/GuNqCYNQ71Cw24LGmdMGEhCgEqTbNa72wD+rePWJuzFucIy gy8+fIvPX9t+L102gk93g4SuTIi5xXaP83pyFesxmTkwBmwK5orjMq+p2 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887089" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887089" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530890" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530890" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:46 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 07/34] x86/opcode: add ERETU, ERETS instructions to x86-opcode-map Date: Wed, 1 Mar 2023 21:24:44 -0800 Message-Id: <20230302052511.1918-8-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234179064497091?= X-GMAIL-MSGID: =?utf-8?q?1759234179064497091?= From: "H. Peter Anvin (Intel)" Add the instruction opcodes used by FRED: ERETU, ERETS. Opcode number is per public FRED draft spec v3.0. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 2 +- tools/arch/x86/lib/x86-opcode-map.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index 5168ee0360b2..7a269e269dc0 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1052,7 +1052,7 @@ EndTable GrpTable: Grp7 0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B) -1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) +1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) | ERETU (F3),(010),(11B) | ERETS (F2),(010),(11B) 2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B) 3: LIDT Ms 4: SMSW Mw/Rv diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index 5168ee0360b2..7a269e269dc0 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1052,7 +1052,7 @@ EndTable GrpTable: Grp7 0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B) -1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) +1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B) | ERETU (F3),(010),(11B) | ERETS (F2),(010),(11B) 2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B) 3: LIDT Ms 4: SMSW Mw/Rv From patchwork Thu Mar 2 05:24:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63219 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063394wrd; Wed, 1 Mar 2023 21:52:58 -0800 (PST) X-Google-Smtp-Source: AK7set8ZLp7gvHPN3JPbJ7STl9aTcppocgJAV25YZDLnG7YV5ZayeTVopELmKjlIpDIe6z+c8Olz X-Received: by 2002:a17:907:c207:b0:8f6:dc49:337f with SMTP id ti7-20020a170907c20700b008f6dc49337fmr13173225ejc.43.1677736378849; Wed, 01 Mar 2023 21:52:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736378; cv=none; d=google.com; s=arc-20160816; b=Ih7CKja5tQto4CNeEDYr3e6NwrFP+J4fAz5E/fKShVIklRih6GvZ4rT/UkO/ztBMff CzYaI4jT9pMcus6WE2A+rl492NBcpnDO/HBj4zkc25Wd720oV983/YtXD3KJUi9RbP95 6qAnVf4NU1Pkpdct8bIQk0hMKJak0dMO/2yb/+rVzztUkH56yTeWmZHWrOCbCyiRg6a+ pgUukeUSgXdyJw8Jzqf/jmJAtKOaUlg0W0acUWbQfWsf7D0olRX8USU2BWyQZJDyO+0+ hYWWuc2DKVQgx/dNENFyuokYCCuS5e91X/DLAWV+ujaGCsgG6phlQDnme+Q+uO2mpUJf M1Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JchyrjrwEWlGzysbWpGTo/SxUt7dXDnCjmdI0vyFoHM=; b=hj+MZsstqhX+ZlM5SkctwU2c5ba1m5O5roycc7Z8udtiHQ3AymEXbMuzMarrTlZPwJ DLZdVh2W7HLdihVpcVCVAogJwY2yoSMfVHG98GnPFmj5gr1XObuKLM5AMx3GIUaah/8k p1M4okTCvXTXmgLn5jbB6QlFV2mNOti0KHheUW2qG8LaIi7bbGhx90i6A+Cuj0as2OuG 0OvDlfljyHDFvbR0aIVDp5SoRVBVyrY2i4wQXmc2NHRsJTLt9i6YP5IwagWnOJLachrA 5tTcQsz/HDMSwuQdKg8q6RRaGTvW+1wkLnJ2xpBP/uXQwAN6Xve5ZUQkXgQ3v65iMNZz tCyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="EM/UM2+a"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id rn22-20020a170906d93600b008b17f6b745fsi5504440ejb.310.2023.03.01.21.52.34; Wed, 01 Mar 2023 21:52:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="EM/UM2+a"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229931AbjCBFvQ (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229802AbjCBFuz (ORCPT ); Thu, 2 Mar 2023 00:50:55 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD5294BEA8; Wed, 1 Mar 2023 21:50:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736253; x=1709272253; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LlMW1NlXfuZMtqkxnDoQy5w38JDnEhwHgVFWrTwAnVg=; b=EM/UM2+a29EBWhNVAc5Z/K/A3HDeoz0BeNaunYAwyxrD39V9XbopnIYK iY+H1xqARuIx6Yoqj2lH7mXBLJ7rBrlbJF0FXsyJwVDSYHDv47BLrREbl Y8yHHds74I+yywwDkoLIOMKy3/AAze+9hopgXAevIS6f045EQYQ56PT3E H4ESsfNLNvGu9moPpj/tIzy+DVm1Yx69U8eChk2WzRHbcsuvzJs4GoCCa 1SvPjNLV0P0i4wtA8WdcuU1RTScnLRgxoLmRAfsb3j3OjKanvnQwD31KS fnprupcRwHgjCNXA6CbzzHqzPWgWpZ0vCzsxB2iCBIbmVd8f13eb7B5BC Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887105" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887105" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530893" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530893" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:47 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 08/34] x86/objtool: teach objtool about ERETU and ERETS Date: Wed, 1 Mar 2023 21:24:45 -0800 Message-Id: <20230302052511.1918-9-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234100689894380?= X-GMAIL-MSGID: =?utf-8?q?1759234100689894380?= From: "H. Peter Anvin (Intel)" Update the objtool decoder to know about the ERETU and ERETS instructions (type INSN_CONTEXT_SWITCH.) Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- tools/objtool/arch/x86/decode.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decode.c index e7b030f7e2a5..735c909540b5 100644 --- a/tools/objtool/arch/x86/decode.c +++ b/tools/objtool/arch/x86/decode.c @@ -509,12 +509,22 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec case 0x0f: if (op2 == 0x01) { - - if (modrm == 0xca) - *type = INSN_CLAC; - else if (modrm == 0xcb) - *type = INSN_STAC; - + switch (insn_last_prefix_id(&insn)) { + case INAT_PFX_REPE: + case INAT_PFX_REPNE: + if (modrm == 0xca) { + /* eretu/erets */ + *type = INSN_CONTEXT_SWITCH; + } + break; + default: + if (modrm == 0xca) { + *type = INSN_CLAC; + } else if (modrm == 0xcb) { + *type = INSN_STAC; + } + break; + } } else if (op2 >= 0x80 && op2 <= 0x8f) { *type = INSN_JUMP_CONDITIONAL; From patchwork Thu Mar 2 05:24:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63216 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063355wrd; Wed, 1 Mar 2023 21:52:53 -0800 (PST) X-Google-Smtp-Source: AK7set9AlnRtM1i3DVwbHn60eUHXR3nMMA2qPn9gDHrMXJYDFvn9u8TktlpDyfMdVZ2iKmlr/YFd X-Received: by 2002:a17:907:392:b0:878:78f9:d1be with SMTP id ss18-20020a170907039200b0087878f9d1bemr8598924ejb.23.1677736373092; Wed, 01 Mar 2023 21:52:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736373; cv=none; d=google.com; s=arc-20160816; b=lmqQyVsZ4fUxSiCBRiKKVARAn6Yd7buMSlL9dJ0o987WsAtbbEIqr6wf3Ky2kUUb1V gatBjdhrZGPjhr1Qc5UHSRwTpY+D5fD83nM0E7dQOQ4DSICXiOc3JaEYNBicty3V85Lz zptsV+b1BJQD02mmhuJlmXUO5McGQbRF8P88NuPYILjsijrbLZI9xkllYynlLtoK0q9f u1Oy75Tk17cbPrUWUXT8CTFASxgr2IP+WbGMKYVtN5JdXmkTo9baeM+xXp8gUHyLXWLx NlQg4wKnX8iPUzPrhF7PhWw0gckQ1555lC0RfbV/JINEF0Olv72pTwTumRyqQGCKWC6s dqyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xiBkMNop4zUxT+iIfOnmWuMSopGG/t7/1Amns2i3v5k=; b=zR1geMWw4pQesNdbH/+rzd5WEFZnV7xSlM4gzM2Oo6GdfjAor0j9eIDtOSdBrBlg6p neZ5GDYd2CIchM547F8nFQflMxYo1GsbaFbIFnrhTFrDweamYusWf3wXfWjvGbk+Bl5P pzYOePFQ7FYEL/VZ7erEJMANJShqZVX83uRTtPcpI99n4SjhKlJvbdyCZrbGYDN20rMG wHAmJHAi1O2ZJstvsqMmtIzgHqvHcZvN3SwAu60D8o8t7S5jcu07MZk8VvseUyoDZyM5 R+c4BNG6TZPNrp5K6sXgMflxTZzDwGEJVhWopp6yNmlymUzWsGY+CiAs6WONna6XUGtV 7akw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CLzNobft; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q7-20020aa7d447000000b004ab4d025978si17587379edr.245.2023.03.01.21.52.27; Wed, 01 Mar 2023 21:52:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CLzNobft; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229950AbjCBFv0 (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229836AbjCBFu5 (ORCPT ); Thu, 2 Mar 2023 00:50:57 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C3D438EBF; Wed, 1 Mar 2023 21:50:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736255; x=1709272255; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xePdNXHU682aUfMVCFmcmPRxw9pVvyjrZ2d9bkzRB0U=; b=CLzNobftOYhJIANZjkSdArN2/BUj79100PuNwX4FfDu8NNR4kxGLVrG1 7VLjyUn9C58UGE4eEzTk6URP+pkmaN8bQJFMOIsC17eeAjqRfCxOQE4Ey pHvLj0kTKonz7YPD1I/2xdVPm+/jxQVhi6lInv/GfbEX3pMN1rzBYW/lF 8QOYwVxzAPHODuynw9CzAPLxXrViMmGLmINM1FVnF/mQ5UVMRu018tUUb swq2sIPsa+iHlvIPELVmDJpFWNasxGWdPie47p9OvJU2SzNjrIl/1J1cU mTWZ4SVy8A2ASembyY+DXBodfYYPxkpWqk2lNBNJ/BiaqznB4LlWyhVTs A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887123" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887123" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530896" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530896" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:47 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 09/34] x86/cpu: add X86_CR4_FRED macro Date: Wed, 1 Mar 2023 21:24:46 -0800 Message-Id: <20230302052511.1918-10-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234095205093049?= X-GMAIL-MSGID: =?utf-8?q?1759234095205093049?= From: "H. Peter Anvin (Intel)" Add X86_CR4_FRED macro for the FRED bit in %cr4. This bit should be a pinned bit, not to be changed after initialization. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/uapi/asm/processor-flags.h | 2 ++ arch/x86/kernel/cpu/common.c | 11 ++++++++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index c47cc7f2feeb..a90933f1ff41 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -132,6 +132,8 @@ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) #define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology */ #define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) +#define X86_CR4_FRED_BIT 32 /* enable FRED kernel entry */ +#define X86_CR4_FRED _BITULL(X86_CR4_FRED_BIT) /* * x86-64 Task Priority Register, CR8 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 8cd4126d8253..e8cf6f4cfb52 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -412,10 +412,15 @@ static __always_inline void setup_umip(struct cpuinfo_x86 *c) cr4_clear_bits(X86_CR4_UMIP); } -/* These bits should not change their value after CPU init is finished. */ +/* + * These bits should not change their value after CPU init is finished. + * The explicit cast to unsigned long suppresses a warning on i386 for + * x86-64 only feature bits >= 32. + */ static const unsigned long cr4_pinned_mask = - X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | - X86_CR4_FSGSBASE | X86_CR4_CET; + (unsigned long) + (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | + X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED); static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; From patchwork Thu Mar 2 05:24:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63222 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063487wrd; Wed, 1 Mar 2023 21:53:14 -0800 (PST) X-Google-Smtp-Source: AK7set+OYil71mA+x9X4i13Fvvtq3n2UPb6d7abDJIaKR8oGmDwTQ6iYE9EniHJiGrAeMA8q3R+c X-Received: by 2002:aa7:dd4d:0:b0:4b0:d079:1e7e with SMTP id o13-20020aa7dd4d000000b004b0d0791e7emr8871427edw.25.1677736393821; Wed, 01 Mar 2023 21:53:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736393; cv=none; d=google.com; s=arc-20160816; b=a5YRjA5pVngafM7HYjNndATyTY0hpiknkiv5B4ugtRP2qGjti2Fu9RsQh8QAX/CNgn 0YAmkc9Et8qtObgmUlbQKw2GiKEZOd+3vPAuhlZ6gD54eKdGAZByGz7hkQTr8W3Efb53 YdLHpxSnKp0/T4nClRXHeHUHcKziPDsf0K2CXwiEDe/UdFJwAVn8lYlHMHhNKwqp7cj+ ZFUAq27w+ZKjwTWi2IuqvDyIS3aO/YEhjdEZfk0j6wRXuanvq2p9tuc85Dr3D6vUOXRk Tnr5R3UmObFNboR0SUBE/lN7bPlAqxjBx7Z5zN9Kvb0u1qDjvVhRFhTMF8o5tMPkFhRv BvnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=P6HtFL7+PoyEnNsypW2XPKGndzZapARWh2X/00BDeqI=; b=HtpU6Q2gmTsmzwMhLZ1HkDZeedjjAzpgtjKXSkQPCNpK8llIjzquDu/iUkZUBCyMcF HPCbU0dZByWeXNnPjAZwxPLSKrx8LyKT4WjMxErmntcbW/Q3g6vdFdFMD/b936W79cg1 6pWX7OwEYMriTP/P/IdWOvUNZItomASSQpeIbbHxne9lLWW/Qes/m41+dMQYYbWyv17S KkM+1I2kVHUjdC8+8tKGCygpfbUBm+tGDCnVMQ6fVMvsD7FGlaX1DxtVt6641eYG9HzR 7zbXtQJHf7sQlafIqtMmfb74r8zC3e6kkiLaAHoM1kHgCYUD3Yfuysdv9fV9hpR/0a6W kLZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=VD5i4SHF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d10-20020aa7d5ca000000b004acbd4990e5si1143531eds.158.2023.03.01.21.52.49; Wed, 01 Mar 2023 21:53:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=VD5i4SHF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229958AbjCBFvq (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229871AbjCBFvB (ORCPT ); Thu, 2 Mar 2023 00:51:01 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69A9B4ECD3; Wed, 1 Mar 2023 21:50:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736258; x=1709272258; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8lktqN9Ow6nF5dYh+N7FoY+KesvEnknJu52aiBKcpfg=; b=VD5i4SHFmXER1OiNtwS8fTaK5EBZQosPfmgH9x7gEZWU9VTApavPpcID oSXH1jOGbDzkZOoC+pLpzXEAPIq2WcTQjjRFnrVpMdIcpAiBm+b3SvtAj /oE4cW6uRxjE0GgTOStndS8rGORDI89cu2+EoXy6dFHRs5lsAO7VWw++z POsLzrupSf3H/YQ0FVza8/pgbEyA4kGM0AhMbmxnCtpRVrYAwh4jUbC/e JR5iCkHk3nKq+02zhtMDZ+QXRF3mtEDRx/mtg2jox5rR4KAsMkxdTuGpL xp/a95DEkXLmUEOijelb4Ir1Ay9lnMjAyAiS/foxs5B+J2WNbUhw4Ok6A w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887160" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887160" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530899" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530899" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:47 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 10/34] x86/fred: add Kconfig option for FRED (CONFIG_X86_FRED) Date: Wed, 1 Mar 2023 21:24:47 -0800 Message-Id: <20230302052511.1918-11-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234117021821939?= X-GMAIL-MSGID: =?utf-8?q?1759234117021821939?= From: "H. Peter Anvin (Intel)" Add the configuration option CONFIG_X86_FRED to enable FRED. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a825bf031f49..da62178bb246 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -500,6 +500,15 @@ config X86_CPU_RESCTRL Say N if unsure. +config X86_FRED + bool "Flexible Return and Event Delivery" + depends on X86_64 + help + When enabled, try to use Flexible Return and Event Delivery + instead of the legacy SYSCALL/SYSENTER/IDT architecture for + ring transitions and exception/interrupt handling if the + system supports. + if X86_32 config X86_BIGSMP bool "Support for big SMP systems with more than 8 CPUs" From patchwork Thu Mar 2 05:24:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63220 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063411wrd; Wed, 1 Mar 2023 21:53:02 -0800 (PST) X-Google-Smtp-Source: AK7set9zay/X6VJadR1vTcVKM7sFWzQkwXFIKzcwP3cLjNhN4JU4Jsonwd/AE1CsgVQL7ekQmPR+ X-Received: by 2002:a17:906:7ad3:b0:8b1:749f:b2c0 with SMTP id k19-20020a1709067ad300b008b1749fb2c0mr9218920ejo.74.1677736381954; Wed, 01 Mar 2023 21:53:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736381; cv=none; d=google.com; s=arc-20160816; b=WbQv/20Il0nsudM4b6qiRzbNdZtSzAqqN9243Y35B2dw716WAEItplm0k1OkuDB0H8 iadCn+Qa6dB/V9IQBiWGw0nw+sO1SIvBh6JQo6JsDZeeV1HaiziTKWT0Dwtfyl5Y45hI h+kOJlcyC3VsIR8ygQPhre6ANBSftY1ZdEljdwIYBrmzFLydYS09jsB2tyu7nkKMrOCB tU9dBksDY7V3CLGm9adN38eqT0Dvj1gmQHaTgDofWjmqSi6xl/sUa7IHOybrDAIi9Qr3 aiBpDJiN5IAvPB9G0nlcNvSEh8vrny3iXPM+gQAeYP/oErGQnU4KDDtUPJLRgwVvnd67 r/nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OSlqpq1ELTxNU1ltDY4IZP23jYiWVSMftVLwVwljWLg=; b=E5mhiH/BSBP7NYDyb4QYICCjX+n4plktuqQ16Tz0wgGSzBp3lhxyHqqBUlYvx/ip9F SpEWNPuEJdOrRpHVQJvc7hWk7wHbq8LziOJmZeVBbVPCN+0t2xnUP+Ixfg/4zpcXvWSh T6pnjwSAS2oXl2m8IJUFeAcdz/RcXbtoB0GcIce3eTf9L7gcU8+mxv0qM9Q87HO4blmO vNmRm9iknlXLsniJMHHmjWPJf6OCIMOZFnx5G48gqThlKJq20VBg43uWwTqBusECT+bd L1GzQeILYByGO1HbgXsKXw8t2b7rmYHlT+37oyZmL+6G8ZyjYZM3MuLxKRuDCDwOuztT ZqtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=FKuelbhI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id kf20-20020a17090776d400b008d86852d974si15264914ejc.664.2023.03.01.21.52.38; Wed, 01 Mar 2023 21:53:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=FKuelbhI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229996AbjCBFvm (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229868AbjCBFvB (ORCPT ); Thu, 2 Mar 2023 00:51:01 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F1BD4ECC9; Wed, 1 Mar 2023 21:50:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736258; x=1709272258; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wcw4oWWYVKLi17TGIcBaJWkCmV6EYpXPXC/uF0gD9d8=; b=FKuelbhIy9IXvSuvk8Udgrg4wuDL+S1KD2WKbM/XZdleEUGwq+TP359d HRbifouIw/MvKi/QVi/GPzens0w64ZsD7RdbewF1AgoPVi/ToStmGbHhk 0BUm3Lw3d0MSfSw6HN3DX5ZTg3DwwNQ5bNOMEfEwlV0emk1rUUiC7IMNc rmcybNfkfakcYv9nl14y1wSlPGqyjNKYq9NYK7IaeTuhQZcTLY3S/q0Jl f6YnLTOgL8I+GPgmxUteuwRohkxIZw2sQcHoZQUk96B+XIoouDSKws0qC jjLYCapML1oHHB+SaoHuvnTxjIZ01YRM2wD4kklj47jNVV3gccTA1KyJm w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887151" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887151" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530904" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530904" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:47 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 11/34] x86/fred: if CONFIG_X86_FRED is disabled, disable FRED support Date: Wed, 1 Mar 2023 21:24:48 -0800 Message-Id: <20230302052511.1918-12-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234104409742485?= X-GMAIL-MSGID: =?utf-8?q?1759234104409742485?= From: "H. Peter Anvin (Intel)" Add CONFIG_X86_FRED to to make cpu_feature_enabled() work correctly with FRED. Originally-by: Megha Dey Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/disabled-features.h | 8 +++++++- tools/arch/x86/include/asm/disabled-features.h | 8 +++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index 5dfa4fb76f4b..56838de9cb23 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -99,6 +99,12 @@ # define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31)) #endif +#ifdef CONFIG_X86_FRED +# define DISABLE_FRED 0 +#else +# define DISABLE_FRED (1 << (X86_FEATURE_FRED & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -115,7 +121,7 @@ #define DISABLED_MASK10 0 #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \ DISABLE_CALL_DEPTH_TRACKING) -#define DISABLED_MASK12 0 +#define DISABLED_MASK12 (DISABLE_FRED) #define DISABLED_MASK13 0 #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h index c44b56f7ffba..2d3ec539dcc7 100644 --- a/tools/arch/x86/include/asm/disabled-features.h +++ b/tools/arch/x86/include/asm/disabled-features.h @@ -99,6 +99,12 @@ # define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31)) #endif +#ifdef CONFIG_X86_FRED +# define DISABLE_FRED 0 +#else +# define DISABLE_FRED (1 << (X86_FEATURE_FRED & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -115,7 +121,7 @@ #define DISABLED_MASK10 0 #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \ DISABLE_CALL_DEPTH_TRACKING) -#define DISABLED_MASK12 0 +#define DISABLED_MASK12 (DISABLE_FRED) #define DISABLED_MASK13 0 #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 From patchwork Thu Mar 2 05:24:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63227 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063582wrd; Wed, 1 Mar 2023 21:53:32 -0800 (PST) X-Google-Smtp-Source: AK7set+fpC5bJFYW1Zs7wo11GOGFGOFI01MEDDFeHqgPoP+fdbyQ+5vgBUqMCgzcst6GpLEqjEqm X-Received: by 2002:a50:ff07:0:b0:4af:601c:ea21 with SMTP id a7-20020a50ff07000000b004af601cea21mr8321721edu.38.1677736411930; Wed, 01 Mar 2023 21:53:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736411; cv=none; d=google.com; s=arc-20160816; b=F24Ss9EzCUPMH2zHqjR9JINzTgF0WTt/y2rZ29rYk3JDXJcJXpZ20CICgRrepmPouR H387iTLvFOk/x/9FdA0OlPMR9rVTtIBxJTrqznWUuXwr5aDTP2PyWcja5lBbG7bUENXa LngA6j+TzycaZv9a8O/h1mQ4UWSJkVv9E3xRt/rwQGbbYewLLmApkMUwZ0ykrNR5NVF+ wJc/VEGJT3zdQtMemkNs+mfbeOYe0yYyO8NWiNYh51fno25MJHzzzcXa8g0JT1qyRPiS 9v3pEA0Y+TdZzlTb+KDt8xNaIMPPo+mM/fys9DacEZ3zhrvh51pDF4ssSzaPlbTN+JoA Xtuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VHkMyyU3HTkyeBGCsS/PdXW3i+nYIJWDtBukRe4hz1Y=; b=W8H1chzcsh2Vt2NJhYmjXTNHAp4hD+pZysbpjJrYJd7AD/DPenAtlg8MlxgiC7dPI2 84H8c/h8xUYsNQPYokMSZSXTgiChNx0HkiJtrzRmpZJXxcR5gSmox7S1M2BS80uzA1he XpMKbn2mDX4cEHxYz3b3OSSIgMhazNyqLlOjRI4DL3nV3NL2039nIBIpjbDwcsmM/yYL tQA1aZ3BnaC1F1mnVjMpf+nmBfgOwumRyhaX7F1z/auwUDB+FdTGw+jdONM/KLko5Gp8 S2kHs2inWVsSrT3h3S3UC5tNDH3ytwYTW94wSVmEAixQM+WJQric0pykUjSPMnGuPFFn T6jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LRb87I6i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qk17-20020a1709077f9100b008cd6f50c059si9160672ejc.669.2023.03.01.21.53.09; Wed, 01 Mar 2023 21:53:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LRb87I6i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230102AbjCBFwX (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjCBFvq (ORCPT ); Thu, 2 Mar 2023 00:51:46 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 844464ECED; Wed, 1 Mar 2023 21:51:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736265; x=1709272265; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Dhlfn7qvLhWN1c0RzKGaosBPQEjw24rUF7QUjxaHu4I=; b=LRb87I6iGWe0s4IDAGpRGOJtnLAw5iUVxtcQay2Dh+nKkcDp0vEOPZVy 0FXnqpsIiOdd6StrY4YuD8On/wLhiG5Okfdq1RmeCbbxHbpQImBjxdXkW h0ZYKZgR3+nVagI9kUCyDPyY5B9HCrcaNavKgPL7WsGY3nxDttyIiaU/k A3C1EzEmrWoIk6CS7NUC2DGcJ3s3DPRoEsLXUbGQ0bi5TbH8Y9RVy3YDF iJNwV/2T32S9IiAZONZ+h8CA8TDj6a6Iypuo9PP7p8C84P/KUslqXANvN ke2KTxJlZXBOwtzjZJeiw3AV8MH1uqvL+/6yydpvJrCSZpP5cTsjja9gP A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887228" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887228" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530907" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530907" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:47 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 12/34] x86/cpu: add MSR numbers for FRED configuration Date: Wed, 1 Mar 2023 21:24:49 -0800 Message-Id: <20230302052511.1918-13-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234135705978121?= X-GMAIL-MSGID: =?utf-8?q?1759234135705978121?= From: "H. Peter Anvin (Intel)" Add MSR numbers for the FRED configuration registers. Originally-by: Megha Dey Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/msr-index.h | 13 ++++++++++++- tools/arch/x86/include/asm/msr-index.h | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ad35355ee43e..87db728f8bbc 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -36,8 +36,19 @@ #define EFER_FFXSR (1<<_EFER_FFXSR) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) -/* Intel MSRs. Some also available on other CPUs */ +/* FRED MSRs */ +#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */ +#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */ +#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */ +#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */ +#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */ +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */ +#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */ +#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */ +#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */ +#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */ +/* Intel MSRs. Some also available on other CPUs */ #define MSR_TEST_CTRL 0x00000033 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 37ff47552bcb..0ade66db3627 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -34,8 +34,19 @@ #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) -/* Intel MSRs. Some also available on other CPUs */ +/* FRED MSRs */ +#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */ +#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */ +#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */ +#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */ +#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */ +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */ +#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */ +#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */ +#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */ +#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */ +/* Intel MSRs. Some also available on other CPUs */ #define MSR_TEST_CTRL 0x00000033 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) From patchwork Thu Mar 2 05:24:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63218 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063392wrd; Wed, 1 Mar 2023 21:52:58 -0800 (PST) X-Google-Smtp-Source: AK7set+K1L/cObCtPvSV41lxFsBA2+8JEqyJQvfcGiXscmtunkyt+3AYmJHkDd6nL9jb670VzW4r X-Received: by 2002:a17:906:e99:b0:8f1:dfa5:8117 with SMTP id p25-20020a1709060e9900b008f1dfa58117mr8348246ejf.51.1677736378418; Wed, 01 Mar 2023 21:52:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736378; cv=none; d=google.com; s=arc-20160816; b=DuKL6S2XhxvV/+k1tBLDJ6QbchbleA0Qb/lBOIqUbQbUvHYo1r/T9OeM2QsKUYC6mF we/sIvxr6tsMFZq7VIyGUVVWM+dBKgVGHeqo7SqO8zwnxfQxxsLwp3W1y3MEGNtBp6Bf 4jdpqCztCLO9I6SvzR1JM7va6bo+CNxRGhLJhTLH5hNbwxQNpGcy8GTPCt6nfwZ/t+yF 1VXKQzftyL31sA7LfXvfQ4CxRwMOUHVWD+HQwT7freLZtbTedH+V27pKOTRwG04pl8XH ut9l6J0wW0BxHtyu8dmTiDXieeE0Hy6/AOTeb0eu3pgIlRURS/AZNSQZT0pMH65GzVXR NqFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+VaUPr04RvGnPD9G9LEI7rZpFLR5XlVkh+7KmqRc0j4=; b=KIIiGk3n19/JT/RQ/nHI8IW/GyYGhld9R12Hefob1IQ7C/Gz5KHHad4GNE5hvoZQA3 kPxtz+Dd8zICpZPQT5f/zFN2StXxoV0X15f3SgApuLJIXg6sGK48oL3lAkSuS7SyDqzd GEfH/4kJaajNob1Kl9dLwkYzCMH5cgW5nJeZeIm0yG3eg7JIowgn75vcVUDXBrR5lRml qTdGzsMsDFwjl7xcd+ifZVtbHuzyeEIKkZBjUnevnKFHisQwrakdSKEH6oDrrIxYK62V itdXrBRncYxsUR4vMhX9ost38/Vet6JBQXMfNnw6XwV5ZhqXUFRN6haT/vIjEgoEAVLb 7qtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kQqfNGTI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l16-20020a170906a41000b008ddf3c18304si1835213ejz.946.2023.03.01.21.52.32; Wed, 01 Mar 2023 21:52:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kQqfNGTI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229831AbjCBFvj (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229823AbjCBFvA (ORCPT ); Thu, 2 Mar 2023 00:51:00 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FF014ECC2; Wed, 1 Mar 2023 21:50:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736258; x=1709272258; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tP9iIQUbrhMc+5l0AHCXnkXnhn3TgNNmkDoitFhCFbw=; b=kQqfNGTIOwujFAgDZd9vgSioCXQY6Irir5a+8NUl+mmcYcYVmvo20Nhy 0mEgpyi0YUOxTa1ryjxIrgDDYdkzlAMXbchwJT3Ng50AiCXJW3ZVM+QIN LsztLpzUSidDHqOaTi4CiH/WU17HyTtlEpEz13Uw+nbUUcRn5AYd62L2Z Iy/ftGJnW8uXz9mzDPvhoV3IWcIx2YWEC517FWz2qoVg6GkPqjQV05jY+ s+SJYLEb40Anw+rHoeem96n4macl3WS+3Ny43MCR4bkzhixFCS1jhqXdx Up1JRTATgsHni7OJzBltiZiCV+BFys9uEMxV3hiX4u6ePXkVWau7z47qc w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887176" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887176" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530910" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530910" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:48 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 13/34] x86/fred: header file for event types Date: Wed, 1 Mar 2023 21:24:50 -0800 Message-Id: <20230302052511.1918-14-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234101218140116?= X-GMAIL-MSGID: =?utf-8?q?1759234101218140116?= FRED inherits the Intel VT-x enhancement of classified events with a two-level event dispatch logic. The first-level dispatch is on the event type, not the event vector as used in the IDT architecture. This also means that vectors in different event types are orthogonal, e.g., vectors 0x10-0x1f become available as hardware interrupts. Add a header file for event types, and also use it in . Suggested-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/event-type.h | 17 +++++++++++++++++ arch/x86/include/asm/vmx.h | 17 +++++++++-------- 2 files changed, 26 insertions(+), 8 deletions(-) create mode 100644 arch/x86/include/asm/event-type.h diff --git a/arch/x86/include/asm/event-type.h b/arch/x86/include/asm/event-type.h new file mode 100644 index 000000000000..fedaa0e492c5 --- /dev/null +++ b/arch/x86/include/asm/event-type.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_EVENT_TYPE_H +#define _ASM_X86_EVENT_TYPE_H + +/* + * Event type codes: these are the same that are used by VTx. + */ +#define EVENT_TYPE_HWINT 0 /* Maskable external interrupt */ +#define EVENT_TYPE_RESERVED 1 +#define EVENT_TYPE_NMI 2 /* Non-maskable interrupt */ +#define EVENT_TYPE_HWFAULT 3 /* Hardware exceptions (e.g., page fault) */ +#define EVENT_TYPE_SWINT 4 /* Software interrupt (INT n) */ +#define EVENT_TYPE_PRIVSW 5 /* INT1 (ICEBP) */ +#define EVENT_TYPE_SWFAULT 6 /* Software exception (INT3 or INTO) */ +#define EVENT_TYPE_OTHER 7 /* FRED: SYSCALL/SYSENTER */ + +#endif diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 498dc600bd5c..8d9b8b0d8e56 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f) @@ -372,14 +373,14 @@ enum vmcs_field { #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK -#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ -#define INTR_TYPE_RESERVED (1 << 8) /* reserved */ -#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ -#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ -#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ -#define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */ -#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ -#define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */ +#define INTR_TYPE_EXT_INTR (EVENT_TYPE_HWINT << 8) /* external interrupt */ +#define INTR_TYPE_RESERVED (EVENT_TYPE_RESERVED << 8) /* reserved */ +#define INTR_TYPE_NMI_INTR (EVENT_TYPE_NMI << 8) /* NMI */ +#define INTR_TYPE_HARD_EXCEPTION (EVENT_TYPE_HWFAULT << 8) /* processor exception */ +#define INTR_TYPE_SOFT_INTR (EVENT_TYPE_SWINT << 8) /* software interrupt */ +#define INTR_TYPE_PRIV_SW_EXCEPTION (EVENT_TYPE_PRIVSW << 8) /* ICE breakpoint - undocumented */ +#define INTR_TYPE_SOFT_EXCEPTION (EVENT_TYPE_SWFAULT << 8) /* software exception */ +#define INTR_TYPE_OTHER_EVENT (EVENT_TYPE_OTHER << 8) /* other event */ /* GUEST_INTERRUPTIBILITY_INFO flags. */ #define GUEST_INTR_STATE_STI 0x00000001 From patchwork Thu Mar 2 05:24:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63226 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063552wrd; Wed, 1 Mar 2023 21:53:26 -0800 (PST) X-Google-Smtp-Source: AK7set8uw9tso9JOqi4pddIk0styA1UvIx95GiAXH3SsxqgUxYZT6bhaNY/LQrjhqaVlmNPEpqQx X-Received: by 2002:a17:906:c516:b0:8de:e66a:ee68 with SMTP id bf22-20020a170906c51600b008dee66aee68mr6545392ejb.35.1677736406119; Wed, 01 Mar 2023 21:53:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736406; cv=none; d=google.com; s=arc-20160816; b=KD/OmAgUU1lKSCoXt+2Af82No2PYtmrH+gLvuNFFqeycFkLOSsMuOYGOsF/8f18u+9 NI2J3l1VuGiSFJTX01D3TuuleyaB7hysRQzTi/r6mQPuNys3xm1edtp7im7KKVTQ8r9i HGH+J3J7PlO8seg1QLBaGm98kbVDojbFLnwsBszmRsKXcvDxmnrU9K7hNKQbUXKsWgoP ryv2I6QYSFbGLDa+RiXHiPKYa7mOF/6oJX39+OijikPIrLiIDmaojo+edV9ZQQIP3Fqq oiZKkXt3ee4NzkKBOPf2WtPeDDiTTZSdTrD1xKUdOxG+vgCiHMMzrus60JEbB2ZNHMSt rG2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QHneXLYBHY7+PKhzjeNNAwkmNqTBqSO8csgVEzl5Wy8=; b=pkGBHuXCytk5DWHa0mY0gszao9bdddGBRksy+hUwWWLbQh44ydyt2vFIeU9PZC8zcc H2h2ZrfoRRk6VBc67dAQFLxv/CxMX0vE0juQbePGjq300O56Ehq/gTVlvcS00M1neepO roHkUHyHEfbzvZvH39vNrdC3oO/piQEiOZ+rRBQBVWi4HynyDEWRVNQmq09q/FDsc3hl aFoUiV/AA9jm6eNcWFvk+i6EGqXFd4U0URJYrEwe28W93/N/sZklQHAQY11ABf3hk204 aI0Z0biXBPn1tiU8ADIhQlK2aTqk9FKCV9F/S4qhO7Lytf3+Nv+yuLFXs4ri8TTHzn7J RUww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=cIlkQVWd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id rp8-20020a170906d96800b008bd8270048dsi17183253ejb.371.2023.03.01.21.53.03; Wed, 01 Mar 2023 21:53:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=cIlkQVWd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230076AbjCBFwF (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229971AbjCBFve (ORCPT ); Thu, 2 Mar 2023 00:51:34 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AB7D521D7; Wed, 1 Mar 2023 21:51:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736261; x=1709272261; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LJAIMdwNFTUrVjDLTbKC/eMN5WktrEucLVbwGrEfGpc=; b=cIlkQVWdtm12nZHIzbdnCkuv+FxLTsigcMK9m/FibReBdMaQEt5Qg37K wqsQradwVOf2OhGH4zFw/bKWfVrzd7HloWozzzqOb0dRmfC9qE3VPMgAi WtEaQZV4yZYBHYOWr+bS0ML1c/zNgsjRC7Jm1e6HDWDwLZmIF55WXqGn3 OC9YgwvD0q9LuyHNo5P30NEnfp1l6aEU79b/y6sXCDausr4SbfKHXNtPU JybKcj29w67aKj53Cm9ZjdnlTCbK7lcocq4w0vMg1aAFhOMu6S4SXYeQO A7CEIfkbpIz8p9BR255Z63gkjiIPKWylgp+y3n2z390BfyT/z35OESU/P A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887206" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887206" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530914" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530914" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:48 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 14/34] x86/fred: header file with FRED definitions Date: Wed, 1 Mar 2023 21:24:51 -0800 Message-Id: <20230302052511.1918-15-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234129734146138?= X-GMAIL-MSGID: =?utf-8?q?1759234129734146138?= From: "H. Peter Anvin (Intel)" Add a header file for FRED prototypes and definitions. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 101 ++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 arch/x86/include/asm/fred.h diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h new file mode 100644 index 000000000000..2f337162da73 --- /dev/null +++ b/arch/x86/include/asm/fred.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/x86/include/asm/fred.h + * + * Macros for Flexible Return and Event Delivery (FRED) + */ + +#ifndef ASM_X86_FRED_H +#define ASM_X86_FRED_H + +#ifdef CONFIG_X86_FRED + +#include +#include + +/* + * FRED return instructions + * + * Replace with "ERETS"/"ERETU" once binutils support FRED return instructions. + * The binutils version supporting FRED instructions is still TBD, and will + * update once we have it. + */ +#define ERETS _ASM_BYTES(0xf2,0x0f,0x01,0xca) +#define ERETU _ASM_BYTES(0xf3,0x0f,0x01,0xca) + +/* + * Event stack level macro for the FRED_STKLVLS MSR. + * Usage example: FRED_STKLVL(X86_TRAP_DF, 3) + * Multiple values can be ORd together. + */ +#define FRED_STKLVL(v,l) (_AT(unsigned long, l) << (2*(v))) + +/* FRED_CONFIG MSR */ +#define FRED_CONFIG_CSL_MASK 0x3 +#define FRED_CONFIG_SHADOW_STACK_SPACE _BITUL(3) +#define FRED_CONFIG_REDZONE(b) __ALIGN_KERNEL_MASK((b), _UL(0x3f)) +#define FRED_CONFIG_INT_STKLVL(l) (_AT(unsigned long, l) << 9) +#define FRED_CONFIG_ENTRYPOINT(p) _AT(unsigned long, (p)) + +/* FRED event type and vector bit width and counts */ +#define FRED_EVENT_TYPE_BITS 3 /* only 3 bits used in FRED 3.0 */ +#define FRED_EVENT_TYPE_COUNT _BITUL(FRED_EVENT_TYPE_BITS) +#define FRED_EVENT_VECTOR_BITS 8 +#define FRED_EVENT_VECTOR_COUNT _BITUL(FRED_EVENT_VECTOR_BITS) + +/* FRED EVENT_TYPE_OTHER vector numbers */ +#define FRED_SYSCALL 1 +#define FRED_SYSENTER 2 + +/* Flags above the CS selector (regs->csx) */ +#define FRED_CSL_ENABLE_NMI _BITUL(28) +#define FRED_CSL_ALLOW_SINGLE_STEP _BITUL(25) +#define FRED_CSL_INTERRUPT_SHADOW _BITUL(24) + +#ifndef __ASSEMBLY__ + +#include +#include + +/* FRED stack frame information */ +struct fred_info { + unsigned long edata; /* Event data: CR2, DR6, ... */ + unsigned long resv; +}; + +/* Full format of the FRED stack frame */ +struct fred_frame { + struct pt_regs regs; + struct fred_info info; +}; + +/* Getting the FRED frame information from a pt_regs pointer */ +static __always_inline struct fred_info *fred_info(struct pt_regs *regs) +{ + return &container_of(regs, struct fred_frame, regs)->info; +} + +static __always_inline unsigned long fred_event_data(struct pt_regs *regs) +{ + return fred_info(regs)->edata; +} + +/* + * How FRED event handlers are called. + * + * FRED event delivery establishes the full supervisor context + * by pushing everything related to the event being delivered + * to the FRED stack frame, e.g., the faulting linear address + * of a #PF is pushed as event data of the FRED #PF stack frame. + * Thus a struct pt_regs has everything needed and it's the only + * input parameter required for a FRED event handler. + */ +#define DECLARE_FRED_HANDLER(f) void f (struct pt_regs *regs) +#define DEFINE_FRED_HANDLER(f) noinstr DECLARE_FRED_HANDLER(f) +typedef DECLARE_FRED_HANDLER((*fred_handler)); + +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_X86_FRED */ + +#endif /* ASM_X86_FRED_H */ From patchwork Thu Mar 2 05:24:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63221 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063444wrd; Wed, 1 Mar 2023 21:53:07 -0800 (PST) X-Google-Smtp-Source: AK7set9Y3UcZHLza8fiLAKpVbxGZTleS9QJ7aid+MzGLUm2jX8DJh2vi/XhRJmF+xOQGwWGMcw84 X-Received: by 2002:aa7:d712:0:b0:4bd:d822:71 with SMTP id t18-20020aa7d712000000b004bdd8220071mr2743821edq.9.1677736387300; Wed, 01 Mar 2023 21:53:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736387; cv=none; d=google.com; s=arc-20160816; b=NT2hgBsqn1jGQctYb2I752aZiUD+HlvwXLy61zCBS9/RcTzXGROY6YHpk5ejcXn2v5 ssCu4a77f9HRPbcKBn8o98BPT37MSc8FMUmME8HGiNHH7GQ0OJWjb4Teqecq6RdPjqYW RYGbX2LPUA2V96eeXrrqkxC0ZD2MibN8teB/1qh7MhZHjJGYs2dRYzgB044kD4nP1uNS sGhy5MsatctwhZjx1M7KXvMBCaK+b+v1EPgD9Ld2a7TNSdZD6DQQGzUIrP85V7w2Mumb w+1pMdSgv3AmYi1CWEgb1DpV1kljpA3mtFFFFFwL3KlIgWebIMNUbXYQzZRcFPRgdL1k 49ZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FmLWc74cBQAtyaKd+oPKv8/i1ka1LREJLyMbbja5omw=; b=QwQUt0O1IvThYZMBRzIvf2I6Zqm1aRxx7+0jpAilX4Vpc4zY2cEmM8diOZ7ud5FevZ x66Eb1VNvw267SM+JQ78b44Gwa0iU/XBRG7EB3pmPkHtCBg/j7P1jEgrC+JrB7gLZhlt pPqJIfD/19GRT6e4UOp67qPCdjXhWaqF2Rth/jgaPsdGBwVBmtM8J8nIdWgUCGIw+IuL V0V18TPOTE0FmlcjGFIoap09uM6N4FWmWSl2jM2VRUZgBzMjiyIBNvUHBYESKwFWoCDV Aw0Y/eyovUuVKn6EXYBSzt3fA17EtMu34v75Kel3h/RURN2Lldme21gwnjDDanK6+Iry 65sQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bbo9k+K4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s14-20020a170906168e00b008b1814ec83fsi7548743ejd.176.2023.03.01.21.52.44; Wed, 01 Mar 2023 21:53:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bbo9k+K4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229937AbjCBFvV (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229799AbjCBFu4 (ORCPT ); Thu, 2 Mar 2023 00:50:56 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 476194C6E1; Wed, 1 Mar 2023 21:50:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736254; x=1709272254; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bMX4XCzIvBalTCdycaBebYL7w+KbpVnH8+oaUrz4fJQ=; b=bbo9k+K4SsranXdcP4Nwn0PsiTVv4AWuFiQwiUdeXS9vtWpK7OEYi9a3 JbRJ8cx2l/hK6ENT9ccbQe+s2dtyIKqxl3jzua9iWpPNBNfaEUjsSbj0+ +LP+f7aWJDFiZDxBPYBZYGJ37D+ngYlge2kIRx0icmWgPd0HDkeEuqSJw WrSw+Ruj6WyY8OwD9tFgGLzeMxMNeosM0gmCzOhfR9yy2MCPUTGWTrIFd 1vvCYepC8JtUqa70oBo44jDRX5LKZmYo1nY/z/GIat6g1hvg55tN3oE8r FdPq8zld1p/tIBcBdRNXKUvEKYJYX1Nk5x4sVgURyruKsjSVRHohExczg A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887114" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887114" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530918" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530918" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:48 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 15/34] x86/fred: make unions for the cs and ss fields in struct pt_regs Date: Wed, 1 Mar 2023 21:24:52 -0800 Message-Id: <20230302052511.1918-16-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234110147128302?= X-GMAIL-MSGID: =?utf-8?q?1759234110147128302?= From: "H. Peter Anvin (Intel)" Make the cs and ss fields in struct pt_regs unions between the actual selector and the unsigned long stack slot. FRED uses this space to store additional flags. The printk changes are simply due to the cs and ss fields changed to unsigned short from unsigned long. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v3: * Rename csl/ssl of the pt_regs structure to csx/ssx (x for extended) (Andrew Cooper). --- arch/x86/entry/vsyscall/vsyscall_64.c | 2 +- arch/x86/include/asm/ptrace.h | 36 ++++++++++++++++++++++++--- arch/x86/kernel/process_64.c | 2 +- 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c b/arch/x86/entry/vsyscall/vsyscall_64.c index d234ca797e4a..2429ad0df068 100644 --- a/arch/x86/entry/vsyscall/vsyscall_64.c +++ b/arch/x86/entry/vsyscall/vsyscall_64.c @@ -76,7 +76,7 @@ static void warn_bad_vsyscall(const char *level, struct pt_regs *regs, if (!show_unhandled_signals) return; - printk_ratelimited("%s%s[%d] %s ip:%lx cs:%lx sp:%lx ax:%lx si:%lx di:%lx\n", + printk_ratelimited("%s%s[%d] %s ip:%lx cs:%x sp:%lx ax:%lx si:%lx di:%lx\n", level, current->comm, task_pid_nr(current), message, regs->ip, regs->cs, regs->sp, regs->ax, regs->si, regs->di); diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index f4db78b09c8f..a61d860dc33c 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -82,13 +82,41 @@ struct pt_regs { * On hw interrupt, it's IRQ number: */ unsigned long orig_ax; -/* Return frame for iretq */ + + /* Return frame for iretq/eretu/erets */ unsigned long ip; - unsigned long cs; + union { + unsigned long csx; /* cs extended: CS + any fields above it */ + struct __attribute__((__packed__)) { + unsigned short cs; /* CS selector proper */ + unsigned int current_stack_level: 2; + unsigned int __csx_resv1 : 6; + unsigned int interrupt_shadowed : 1; + unsigned int software_initiated : 1; + unsigned int __csx_resv2 : 2; + unsigned int nmi : 1; + unsigned int __csx_resv3 : 3; + unsigned int __csx_resv4 : 32; + }; + }; unsigned long flags; unsigned long sp; - unsigned long ss; -/* top of stack page */ + union { + unsigned long ssx; /* ss extended: SS + any fields above it */ + struct __attribute__((__packed__)) { + unsigned short ss; /* SS selector proper */ + unsigned int __ssx_resv1 : 16; + unsigned int vector : 8; + unsigned int __ssx_resv2 : 8; + unsigned int type : 4; + unsigned int __ssx_resv3 : 4; + unsigned int enclv : 1; + unsigned int long_mode : 1; + unsigned int nested : 1; + unsigned int __ssx_resv4 : 1; + unsigned int instr_len : 4; + }; + }; }; #endif /* !__i386__ */ diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 4e34b3b68ebd..57de166dc61c 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -116,7 +116,7 @@ void __show_regs(struct pt_regs *regs, enum show_regs_mode mode, printk("%sFS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", log_lvl, fs, fsindex, gs, gsindex, shadowgs); - printk("%sCS: %04lx DS: %04x ES: %04x CR0: %016lx\n", + printk("%sCS: %04x DS: %04x ES: %04x CR0: %016lx\n", log_lvl, regs->cs, ds, es, cr0); printk("%sCR2: %016lx CR3: %016lx CR4: %016lx\n", log_lvl, cr2, cr3, cr4); From patchwork Thu Mar 2 05:24:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63224 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063533wrd; Wed, 1 Mar 2023 21:53:22 -0800 (PST) X-Google-Smtp-Source: AK7set9MqG2iT1mZQB2qO/kqra8rVRoz2IPSWGkxOdjhgZ4QmeLYAHCplG/AhPoX3ANZK1m0NGUA X-Received: by 2002:a17:907:25c2:b0:8e1:12b6:a8fc with SMTP id ae2-20020a17090725c200b008e112b6a8fcmr11278865ejc.4.1677736402184; Wed, 01 Mar 2023 21:53:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736402; cv=none; d=google.com; s=arc-20160816; b=U6gtxyDhjGmNAxUj0QUyiwUGrfUgz1pUG2jGfR8XPCRKbCBs/AqlDLXbU2p1M6D+GI whSvY4f2++8z+YuiBKcRYJ0ziEnJ5d9gHE+UdQs9XTYmCjHOfy9Jc0fL0lna+O5Jfk/H EqqO13c1rMsmU1FYJ032ybhILQO6Xu6klod5xjkyO6g0YdwFT6W99NHJ6krwUH2AQfKD LSj+NoALNWktDq2cXVvcdLZunuMyEL4ahZkauNOB0f1tfZ1R+PQF+n6nfvydLgIDULR4 g2gBQ8Z/j+3QbQoycKtPc0Tfi3EpMAl39TSekS0+IFoLzex0E7OM9QvRgyxPdq/5AN/N Vz1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=N4FXxoAND7jQBjEqpShHPjc4hHLflyZ6xveUxpk88v4=; b=IQgv7IXkVBlSTEzBtwlBR6PEX8IabIg7jq2KxZ31IyzHp2cbjO4Nn+3ZNIkHb8UIQK 4SzXsRQo50yTclp70YPDMrb71gWLyuBfeLVBHY0GpJ0EoZ9mFAX4m+xkLx46cUYNRNJK b3tRVx662JkXioSGDPHkaF8hGLKzb491wJ1tm6QUY9lPjHbqJXqHw+AK2J5Dqin6Sv+i ppeeoYYEg7M2TW7UIaUEK+ZZ7IgcHk98/EWA5k3owQKRAzoiJgQoVKO5lZMpPbJCTFIf 1KQnESROOpcsIEMLg2Rs64sbL6FIug7v9Tz2uRphoGbyxEcL817Bsw3u5XnsWl4wPLIk sVLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gjEX5fzf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v12-20020a170906338c00b008e0bd541c5fsi14036521eja.926.2023.03.01.21.52.57; Wed, 01 Mar 2023 21:53:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gjEX5fzf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230052AbjCBFvy (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229965AbjCBFva (ORCPT ); Thu, 2 Mar 2023 00:51:30 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54D0C4E5E8; Wed, 1 Mar 2023 21:51:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736260; x=1709272260; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=voFQVjFSRNzDP3of726cqSfwzN6e3VmowuyZWcsyuKM=; b=gjEX5fzftlhKADWO1Mdk4T6ESyjkokRqYTUmr33Gpwu4gZvzuRWbXkkG lii4AJWxJlatWFWQqfGNmKKbRFyvTcFrH96jB92TD68cKdvP0oAwfe6rR Y84C4Dym6rwsKtW1AYFRdf0HI3qH0jlzGoaYpFC1hev0OE+PkDJUDgGQX u8P+90BgKutUuUVEeVzrpgZ6TS41qonA5v1j5tW8g+IyBXvaGernsS3IU Erw9jHksdGXk5VEsUAJZZJbekttBPnEZaFoLfA8DvvX9nPFkB8FzIo2RR yD/eZXUslpmp7Y4h3k8SdFGxC5TW67OVqPzfKuZREkSn7+4Nh3LH7zqoF Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887199" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887199" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530921" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530921" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:48 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 16/34] x86/fred: reserve space for the FRED stack frame Date: Wed, 1 Mar 2023 21:24:53 -0800 Message-Id: <20230302052511.1918-17-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234125659500993?= X-GMAIL-MSGID: =?utf-8?q?1759234125659500993?= From: "H. Peter Anvin (Intel)" When using FRED, reserve space at the top of the stack frame, just like i386 does. A future version of FRED might have dynamic frame sizes, though, in which case it might be necessary to make TOP_OF_KERNEL_STACK_PADDING a variable instead of a constant. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/thread_info.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index f1cccba52eb9..998483078d5f 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -31,7 +31,9 @@ * In vm86 mode, the hardware frame is much longer still, so add 16 * bytes to make room for the real-mode segments. * - * x86_64 has a fixed-length stack frame. + * x86-64 has a fixed-length stack frame, but it depends on whether + * or not FRED is enabled. Future versions of FRED might make this + * dynamic, but for now it is always 2 words longer. */ #ifdef CONFIG_X86_32 # ifdef CONFIG_VM86 @@ -39,8 +41,12 @@ # else # define TOP_OF_KERNEL_STACK_PADDING 8 # endif -#else -# define TOP_OF_KERNEL_STACK_PADDING 0 +#else /* x86-64 */ +# ifdef CONFIG_X86_FRED +# define TOP_OF_KERNEL_STACK_PADDING (2*8) +# else +# define TOP_OF_KERNEL_STACK_PADDING 0 +# endif #endif /* From patchwork Thu Mar 2 05:24:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63233 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063918wrd; Wed, 1 Mar 2023 21:54:34 -0800 (PST) X-Google-Smtp-Source: AK7set+ozgCl53otEz7/6QOGnOvkDSWrAe7gxM3zyJx1Mi5CDO8PepzyhFpI3siIa3EdBHUsPyLh X-Received: by 2002:aa7:cb12:0:b0:4ac:b2c8:aeaf with SMTP id s18-20020aa7cb12000000b004acb2c8aeafmr9547850edt.26.1677736474367; Wed, 01 Mar 2023 21:54:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736474; cv=none; d=google.com; s=arc-20160816; b=hJTwazRsZdD3fiMocYRibljbeS/quAC176IJCbr0Db9Q9rU2L2pWBraqY0o5/itUSS 9cJY3n1lMqpLU+8qk2gCqy6n3wUybsuyzyXw87cXzGrEJGxU8DVogHibonrw7Cff+YSQ NcmdujlJmpk//MPStUH3nQ/OuwvLFqd6cj+jNTj3o278NRu0JaYjjAVGVEj85kAApHCH HHpfZCT385OH8mdX7WD4j/pELfECxGK5mtT/EsIvldJwKwjGW0TBmZ0pgAstTv2/D37w EdQGjHF/Wweb3lv/c3IADnBhKz7R9+Qxm+IeKg8rt5BCEJj1tCdWJu4Pp3m/FIgCroSS 4x8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BWZ/Fs/YqPHhG+vbleqMrIxlzACZYftKS0YHpwFAQyI=; b=Fypm+lVAsUI60ZL4zDPRNR/rCZoDolCc+DIWfcYFCXV6EhVlWZkdA7VqRLDaAMUqqg QKM5tR3RyY/pevwx0rff1in3gf1MF4ka0sxVOWDZF0c7/QPxi14ityiMf86NYJ8PBzLv sseP4z1iUpz7BBO1ChF6uEjYtA2HRClKpEL4/KAeahiFkxQEVU0zscHTQwCiGGjdpl/A TqcguolY0364cI3wE9P0pG0jYjMPcVd42fuyZSltC/spGZu201x7UlMkKU8LCUPKHrJD eqzu+WfxMa910IE+bNyKDR7DgBPJo9bDyt/hbO9TIkV9v9qGfH9P6kt6Xnfld6gCEUkW efAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=WcuqUjLt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d25-20020a50fb19000000b004beaccf8fd3si2398513edq.409.2023.03.01.21.54.12; Wed, 01 Mar 2023 21:54:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=WcuqUjLt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229968AbjCBFva (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229861AbjCBFu5 (ORCPT ); Thu, 2 Mar 2023 00:50:57 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0EF84DE12; Wed, 1 Mar 2023 21:50:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736255; x=1709272255; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zbDdVunyGdhXyhjUE3Gbpn/xbHM27xiNyk5ThtGHdLg=; b=WcuqUjLtgjAOK+DLaIe6uzx5hbjPPIsCCX2YrCUB8e0u/7K0voKg+kxF ODNzVC4/TZbOozJmIc+TMJNSTO/vDAs6j2BUMnsoSdtOD6hENS4uOTasd o/I/TUekjaF7sMBTjFAEcfn9OoxdeRSjBdDB509KktFlY7LZ9pdkHCjuz 8K7kg6tPR/akGB1suwqgfcRaffFcEEX/09hBhEYQwWc8CaFmCRu/LQ6lT JJXASbRrgyrugIAkxZsjR9+lxdDyxe/0f2azVBNYlx36Trkz7ehu1J3CL l4K0bu+L90wcK5RQrjY9rkajrxf/s/67MueRhZlt0PM5CrJhnwkvGPk0H A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887132" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887132" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530924" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530924" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:48 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 17/34] x86/fred: add a page fault entry stub for FRED Date: Wed, 1 Mar 2023 21:24:54 -0800 Message-Id: <20230302052511.1918-18-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234201263719558?= X-GMAIL-MSGID: =?utf-8?q?1759234201263719558?= From: "H. Peter Anvin (Intel)" Add a page fault entry stub for FRED. On a FRED system, the faulting address (CR2) is passed on the stack, to avoid the problem of transient state. Thus we get the page fault address from the stack instead of CR2. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 2 ++ arch/x86/mm/fault.c | 20 ++++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 2f337162da73..57affbf80ced 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -94,6 +94,8 @@ static __always_inline unsigned long fred_event_data(struct pt_regs *regs) #define DEFINE_FRED_HANDLER(f) noinstr DECLARE_FRED_HANDLER(f) typedef DECLARE_FRED_HANDLER((*fred_handler)); +DECLARE_FRED_HANDLER(fred_exc_page_fault); + #endif /* __ASSEMBLY__ */ #endif /* CONFIG_X86_FRED */ diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index a498ae1fbe66..0f946121de14 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -33,6 +33,7 @@ #include /* kvm_handle_async_pf */ #include /* fixup_vdso_exception() */ #include +#include /* fred_event_data() */ #define CREATE_TRACE_POINTS #include @@ -1507,9 +1508,10 @@ handle_page_fault(struct pt_regs *regs, unsigned long error_code, } } -DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault) +static __always_inline void page_fault_common(struct pt_regs *regs, + unsigned int error_code, + unsigned long address) { - unsigned long address = read_cr2(); irqentry_state_t state; prefetchw(¤t->mm->mmap_lock); @@ -1556,3 +1558,17 @@ DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault) irqentry_exit(regs, state); } + +DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault) +{ + page_fault_common(regs, error_code, read_cr2()); +} + +#ifdef CONFIG_X86_FRED + +DEFINE_FRED_HANDLER(fred_exc_page_fault) +{ + page_fault_common(regs, regs->orig_ax, fred_event_data(regs)); +} + +#endif /* CONFIG_X86_FRED */ From patchwork Thu Mar 2 05:24:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63225 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063548wrd; Wed, 1 Mar 2023 21:53:25 -0800 (PST) X-Google-Smtp-Source: AK7set/+HKYW7CoUi6LjjSy7w38DA2C8exyPHfkhBy2o5hQmlZkHU3U3O83fbH73stf+im6kYP/p X-Received: by 2002:a17:906:e14:b0:861:4671:a834 with SMTP id l20-20020a1709060e1400b008614671a834mr8677677eji.71.1677736405810; Wed, 01 Mar 2023 21:53:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736405; cv=none; d=google.com; s=arc-20160816; b=F4O27TrL9k0ooHJhY3GrbJYolpjx1TFKA4EgSjHsD+zb3TJvBfzwL3frhGvaT+wmbD CoLF/a9vRuwWhcKKw5kBpMYcIzALV3tfguJ1rIJXVBb5JDnlHRB+bhSsPCEuetRnRweF jzpiTYU+TPnoAgDY0wYQgWQTIE8VCsdh2xEmJHIlWJcAIjrzakg3snDedS5HzMnE2QpN QJZ+WPHaMjyxboF0xHLyn+p/cUJ/vGSpVQYuFrAi7yW0kOAY2W5+UHvq3F8R77AnW4j5 /ezb1bT+TMGi9Ly8d8/OutblrXWYaZJCDfph/0uCt7wOTGiGqNIbHMNnvFTONycximkJ DElg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5faTauMQSF6A1INgRvw37EaNuyfpbr4ubN9CGI+xwAg=; b=x9gCjdOpkSCQyr317dZRB8BcpJgfJGqpOlKHGAjsATu2oc0iw+cjyRbHSxF0VYsW6G p9IvihubvzF6bC3mZtg+7R0iWaFBhGMGg3ED+A9C/qQ4m1fdOkoOSllGb5VQLIyv1ki7 TowPmxmjbDn0M8bbZaj2PoZeMNqBkbXXSjddozG9IsWTDqxj5V65XLCVjvFJpcBTHMh9 k3e7u6TBwJx0RnKi875VrnbjsH2OMd7hklX9Gi/GacZr3d06sU97bmGJPu43yB9IES5o c3UA0MW5+JX0q8hl5MWzuwKjfVqYy02ugMa2/XoMuwEjj2pNXXSk3K3Yf1/tjFhp/TOZ sZqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Lbz4xAm1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sa26-20020a1709076d1a00b008b79a5e7440si100076ejc.117.2023.03.01.21.53.02; Wed, 01 Mar 2023 21:53:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Lbz4xAm1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230071AbjCBFwB (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229892AbjCBFvd (ORCPT ); Thu, 2 Mar 2023 00:51:33 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C64D4DE0A; Wed, 1 Mar 2023 21:51:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736261; x=1709272261; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4MOmv1ssbPQB1T3aYHisX8wUlNtj7mFGaUC5mOSwjmE=; b=Lbz4xAm1+SYo5/758WHbUY0/x9tD4P1IN7CJqvlmEUn8xK0YViLZgyD8 CIEdg8K/culhaPFd39PoyroTw3Wt9DuWGsOblmFUoQHQNqCnmvq+mVTne TGdLwhnlptz+dg4EtOj52Kg/DLE5qLdAXTFfBVy0Sbq/O6YHkdxZdNztD k2Lxj39Z5gvhzkZ4HkOL6Iisp5OlAQZqRVtOcdcZ9TD9PeItlfrJyva3y ZTp/E0L1SI4pN9hneblfNzGy3oRyiFkH0wj08oa57TKYrOCPYPjLXA4FL sdsrPijgT4DfSA0OcGeH5zTUyoOtrcFM9XZXkncn8sffrpOrUO4cTPDVs w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887204" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887204" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530927" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530927" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:49 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 18/34] x86/fred: add a debug fault entry stub for FRED Date: Wed, 1 Mar 2023 21:24:55 -0800 Message-Id: <20230302052511.1918-19-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234129185552885?= X-GMAIL-MSGID: =?utf-8?q?1759234129185552885?= From: "H. Peter Anvin (Intel)" Add a debug fault entry stub for FRED. On a FRED system, the debug trap status information (DR6) is passed on the stack, to avoid the problem of transient state. Furthermore, FRED transitions avoid a lot of ugly corner cases the handling of which can, and should be, skipped. The FRED debug trap status information saved on the stack differs from DR6 in both stickiness and polarity; it is exactly what debug_read_clear_dr6() returns, and exc_debug_user()/exc_debug_kernel() expect. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v1: * call irqentry_nmi_{enter,exit}() in both IDT and FRED debug fault kernel handler (Peter Zijlstra). --- arch/x86/include/asm/fred.h | 1 + arch/x86/kernel/traps.c | 56 +++++++++++++++++++++++++++---------- 2 files changed, 42 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 57affbf80ced..633dd9e6a68e 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -94,6 +94,7 @@ static __always_inline unsigned long fred_event_data(struct pt_regs *regs) #define DEFINE_FRED_HANDLER(f) noinstr DECLARE_FRED_HANDLER(f) typedef DECLARE_FRED_HANDLER((*fred_handler)); +DECLARE_FRED_HANDLER(fred_exc_debug); DECLARE_FRED_HANDLER(fred_exc_page_fault); #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index cebba1f49e19..4b0f63344526 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include #include @@ -1020,21 +1021,9 @@ static bool notify_debug(struct pt_regs *regs, unsigned long *dr6) return false; } -static __always_inline void exc_debug_kernel(struct pt_regs *regs, - unsigned long dr6) +static __always_inline void debug_kernel_common(struct pt_regs *regs, + unsigned long dr6) { - /* - * Disable breakpoints during exception handling; recursive exceptions - * are exceedingly 'fun'. - * - * Since this function is NOKPROBE, and that also applies to - * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a - * HW_BREAKPOINT_W on our stack) - * - * Entry text is excluded for HW_BP_X and cpu_entry_area, which - * includes the entry stack is excluded for everything. - */ - unsigned long dr7 = local_db_save(); irqentry_state_t irq_state = irqentry_nmi_enter(regs); instrumentation_begin(); @@ -1062,7 +1051,8 @@ static __always_inline void exc_debug_kernel(struct pt_regs *regs, * Catch SYSENTER with TF set and clear DR_STEP. If this hit a * watchpoint at the same time then that will still be handled. */ - if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs)) + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + (dr6 & DR_STEP) && is_sysenter_singlestep(regs)) dr6 &= ~DR_STEP; /* @@ -1090,7 +1080,25 @@ static __always_inline void exc_debug_kernel(struct pt_regs *regs, out: instrumentation_end(); irqentry_nmi_exit(regs, irq_state); +} +static __always_inline void exc_debug_kernel(struct pt_regs *regs, + unsigned long dr6) +{ + /* + * Disable breakpoints during exception handling; recursive exceptions + * are exceedingly 'fun'. + * + * Since this function is NOKPROBE, and that also applies to + * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a + * HW_BREAKPOINT_W on our stack) + * + * Entry text is excluded for HW_BP_X and cpu_entry_area, which + * includes the entry stack is excluded for everything. + */ + unsigned long dr7 = local_db_save(); + + debug_kernel_common(regs, dr6); local_db_restore(dr7); } @@ -1179,6 +1187,24 @@ DEFINE_IDTENTRY_DEBUG_USER(exc_debug) { exc_debug_user(regs, debug_read_clear_dr6()); } + +# ifdef CONFIG_X86_FRED +DEFINE_FRED_HANDLER(fred_exc_debug) +{ + /* + * The FRED debug information saved onto stack differs from + * DR6 in both stickiness and polarity; it is exactly what + * debug_read_clear_dr6() returns. + */ + unsigned long dr6 = fred_event_data(regs); + + if (user_mode(regs)) + exc_debug_user(regs, dr6); + else + debug_kernel_common(regs, dr6); +} +# endif /* CONFIG_X86_FRED */ + #else /* 32 bit does not have separate entry points. */ DEFINE_IDTENTRY_RAW(exc_debug) From patchwork Thu Mar 2 05:24:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63217 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063385wrd; Wed, 1 Mar 2023 21:52:57 -0800 (PST) X-Google-Smtp-Source: AK7set9yDkw5uowTeW/STsP75+4lGdkZvp43shhlWZLkLgKCsxIIZLZo+gBONdPTgYkJlL3MdBBv X-Received: by 2002:a17:906:c1d0:b0:88e:682e:3a9e with SMTP id bw16-20020a170906c1d000b0088e682e3a9emr9999425ejb.61.1677736377442; Wed, 01 Mar 2023 21:52:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736377; cv=none; d=google.com; s=arc-20160816; b=VGT3j5jL0un3AbvRQSMm/qxJbGhpnI0FawbbMD808nc2D6Qkd28fVbHdNWSchukrfw ctbIds9TV20lt+8f6Xf8BhExBGAQtUf8Jxl+MSVloFdaL4V69KcQ0DGouN3xDKsmLq7v m3PCUx9gPmZDXW55WKkfTV5m27hLbiHKX3ldQPU8fr0NbXfu1mUPTnLPxCZFf0JACXht mHLlz3WcPlKQYpSP3GMYO6F2Fflhz+xXuqbrmy6zqtnNbHXbtRQTQeHMXu3OGWwQ9WLJ BPXtxhnSZCBA4kc92B/VeWMR+y94x7VoMEwYk3stDpyIitSKGmuMoW9uMrxyyGemdSMw fC5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=h+68pRnmJGZH53rrxJ5ePUtJhcj/U+0E+Y2T3Oe3Zns=; b=rZLPgIO/su1qN6Ljln/RI+QZ0hM0pJHUog8E2xFx+hRYgMNBpijEuQ6kMQwxqJoD7G oJ8SfRdCaEFcDkYYa+F04+tB2XoDsUHq8Xj0c/R4WqgEt8HP6XvgnLtofpLg9wycaBvp /hUjngGSbSmfNjd0yVhdz8FWfflJwDfi5f3+07eHl0NM6vbFztAQLRLKjEQJTA7dZ5QF +29908Qca041RzPY1sNGjSbhMhwcPhTKVs1YqgIU3LtN9E9C2t1F9q5ErcfIetjjFgUv wKTrEq989fsFlEeZ8p1gYC2LRSA7qZL4Ul0ja71po/NJ27Efx0H9Tb93VnDp5LN2WWWy oCgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YZM7dUQS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v16-20020a170906859000b008b17879ce7asi1171533ejx.914.2023.03.01.21.52.29; Wed, 01 Mar 2023 21:52:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YZM7dUQS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229977AbjCBFve (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229881AbjCBFu7 (ORCPT ); Thu, 2 Mar 2023 00:50:59 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19A794E5C0; Wed, 1 Mar 2023 21:50:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736257; x=1709272257; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=siTNXpO7BJ/4zV0VfXO5tCEXqrBwC+DhXoQqxTjs92s=; b=YZM7dUQSruF79mZdIQyCNWfnwadP0uDxdF0WBHjIW5oeXtZgg2CtRBk0 cx6h94t7OcRsh4JjokGiovC+M7UP0NxswS+j7Jch9gzb6JR9Uh6BGXzKb KXffb+c6QHo6ki9UG6wX9FChpO3FwetLuSCTuLhDfzDyD1IFBDbWvz5eq UUkbGAShraOvtLHTlnQg+nkjHiHYmclbU7ZmCvWAl6HIqu1oBhN9+/r0+ K552+2zhnoqESYQFnq2h3XFDol9ioHo9+Iq6CCuA9S5IsK8Bb2fFLT8Xk xfF14JnV6jh1yc4ZDrKSghbQE4j1CyAoi2+/YmFsT2sl/jb0yTL5JSd8S g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887141" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887141" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530931" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530931" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:49 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 19/34] x86/fred: add a NMI entry stub for FRED Date: Wed, 1 Mar 2023 21:24:56 -0800 Message-Id: <20230302052511.1918-20-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234099980260167?= X-GMAIL-MSGID: =?utf-8?q?1759234099980260167?= From: "H. Peter Anvin (Intel)" On a FRED system, NMIs nest both with themselves and faults, transient information is saved into the stack frame, and NMI unblocking only happens when the stack frame indicates that so should happen. Thus, the NMI entry stub for FRED is really quite small... Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 1 + arch/x86/kernel/nmi.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 633dd9e6a68e..f928a03082af 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -94,6 +94,7 @@ static __always_inline unsigned long fred_event_data(struct pt_regs *regs) #define DEFINE_FRED_HANDLER(f) noinstr DECLARE_FRED_HANDLER(f) typedef DECLARE_FRED_HANDLER((*fred_handler)); +DECLARE_FRED_HANDLER(fred_exc_nmi); DECLARE_FRED_HANDLER(fred_exc_debug); DECLARE_FRED_HANDLER(fred_exc_page_fault); diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 776f4b1e395b..1deedfd6de69 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -34,6 +34,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include @@ -643,6 +644,33 @@ void nmi_backtrace_stall_check(const struct cpumask *btp) #endif +#ifdef CONFIG_X86_FRED +DEFINE_FRED_HANDLER(fred_exc_nmi) +{ + /* + * With FRED, CR2 and DR6 are pushed atomically on faults, + * so we don't have to worry about saving and restoring them. + * Breakpoint faults nest, so assume it is OK to leave DR7 + * enabled. + */ + irqentry_state_t irq_state = irqentry_nmi_enter(regs); + + /* + * VM exits induced by NMIs keep NMI blocked, and we do + * "int $2" to reinject the NMI w/ NMI kept being blocked. + * However "int $2" doesn't set the nmi bit in the FRED + * stack frame, so we explicitly set it to make sure a + * later ERETS will unblock NMI immediately. + */ + regs->nmi = 1; + + inc_irq_stat(__nmi_count); + default_do_nmi(regs); + + irqentry_nmi_exit(regs, irq_state); +} +#endif + void stop_nmi(void) { ignore_nmis++; From patchwork Thu Mar 2 05:24:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63215 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063199wrd; Wed, 1 Mar 2023 21:52:25 -0800 (PST) X-Google-Smtp-Source: AK7set8vQr02k0Axw7lG3RgGNZ58r4s0H/435pamx0DnYeCdeu9T/L3pdwXSVE/luWSlF2tyqfca X-Received: by 2002:a17:907:80cd:b0:8ae:fa9f:d58e with SMTP id io13-20020a17090780cd00b008aefa9fd58emr15523887ejc.53.1677736345758; Wed, 01 Mar 2023 21:52:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736345; cv=none; d=google.com; s=arc-20160816; b=whGhp+NEdCwsYQFs9iuEIvj7mvKdi1y1L2yBAcrLeOiBKeDANfplDXG4aTahKXBOJi /Ayue00jGmogmMnoT0TsfOwsKPvy/I6t+vSTr0rjdu3D9Lha53ciZTiPzHqXoNcGSJ04 keiV7kvdcz0v8CQ5RSJ17jNcl+msUO8h+wnUBThISHEdq3uxHx0BhKvVb4PQ/NxdOjak yNuJzarKZooVoWQebq75RbW8fIbGtWMbuaMcx2+uNTeSsVMji2iQDmCYgffrU0Ogf6sk sKhP9Nd7ggFw9zZWjvrt/9u/XmkSrwHwOrCHDqk4U140gDs46IQl/0wX8SURoVKBkqKP U0mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=62cabqeBtlyHMtRghTLfhd1jpTyyJqzc9Z9q/A5AdvQ=; b=PJ6Xt3dKM+ctvjLuOs5bs1mcolBoe5WroUL0J4IZfftZIaYbZvVjcG92KktJJERKPa F1PXq0AhloTi7A4xLLQDkjU2RdSzTaxo4LkrFucMdh2CCTXqBRgjI6fzA64actWscx8W 3FmFj/lKJTcHNZSIdClnCXai8q1S/JP9OOFfgDhWdRjmn5+ivRddpfop+PRGvrKs2kJF k+v7Niq5WJzWe9JtO7g2ZLKOpvaQEOOHPkWxIXMG+8o6OKFwKvyQwXeTVx0+8EhFGWGU G8ws9renVyuBNuK8PagwjBzz9JEM9pOS4hBeuSsdnAHxfFPGKW7DIdvAbXVqEWpEUdLA ZmXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=lf3UTBua; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id re23-20020a170906d8d700b008de4a641ff4si6407849ejb.412.2023.03.01.21.52.01; Wed, 01 Mar 2023 21:52:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=lf3UTBua; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229916AbjCBFvH (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229764AbjCBFux (ORCPT ); Thu, 2 Mar 2023 00:50:53 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B13A4AFE7; Wed, 1 Mar 2023 21:50:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736252; x=1709272252; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Y8+C0nkNS1GRT0vpQmI78TLcU0TSh7ChvDXpWBoU34k=; b=lf3UTBuaNQ4UC3hRSL9g25i0HubuI79ZeLF5Jxg3IHb6NLGLiX7u36Mz zv3RyJUI9lYHCy00Hh8BAjwDfd3x+GihEU/TvCOpiU9LsQoC441K1Lav+ ncjdIqmG/Tu7pK1L/ybnMVi/eFSh0+PJRAIjoxwCzlh31QN91g7vDUp6s vcrCTDLhl0Ojp2WRBlvUEoaTPqnkvWhBabtiBlwD8ZWIx2K0ravnPlhgp ioaQwg9gxRX+Q5WsgMc1x/GIWU2Bs50DaYDX9bxtYtC2WiKWtq6+TGERK 1pnp6T15LqAqbQ7VmNRPTGXYaYWGXDz4MTBzrh0BBDk7P3vrkJkW8mE9n Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887080" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887080" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530944" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530944" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:49 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 20/34] x86/fred: add a machine check entry stub for FRED Date: Wed, 1 Mar 2023 21:24:57 -0800 Message-Id: <20230302052511.1918-21-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234066359577219?= X-GMAIL-MSGID: =?utf-8?q?1759234066359577219?= Add a machine check entry stub for FRED. Unlike IDT, no need to save/restore dr7 in FRED machine check handler. Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 1 + arch/x86/kernel/cpu/mce/core.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index f928a03082af..54746e8c0a17 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -97,6 +97,7 @@ typedef DECLARE_FRED_HANDLER((*fred_handler)); DECLARE_FRED_HANDLER(fred_exc_nmi); DECLARE_FRED_HANDLER(fred_exc_debug); DECLARE_FRED_HANDLER(fred_exc_page_fault); +DECLARE_FRED_HANDLER(fred_exc_machine_check); #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 7832a69d170e..26fa7fa44f30 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -52,6 +52,7 @@ #include #include #include +#include #include "internal.h" @@ -2111,6 +2112,16 @@ DEFINE_IDTENTRY_MCE_USER(exc_machine_check) exc_machine_check_user(regs); local_db_restore(dr7); } + +#ifdef CONFIG_X86_FRED +DEFINE_FRED_HANDLER(fred_exc_machine_check) +{ + if (user_mode(regs)) + exc_machine_check_user(regs); + else + exc_machine_check_kernel(regs); +} +#endif #else /* 32bit unified entry point */ DEFINE_IDTENTRY_RAW(exc_machine_check) From patchwork Thu Mar 2 05:24:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63223 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063506wrd; Wed, 1 Mar 2023 21:53:18 -0800 (PST) X-Google-Smtp-Source: AK7set9EAy4uvb3JplYhh4PiBgtTjb4T/7+WHLPOBS9ueflMpOjJRukAN1Y06Oejc0hF4X6fspkn X-Received: by 2002:aa7:cd89:0:b0:4af:69e2:529f with SMTP id x9-20020aa7cd89000000b004af69e2529fmr10687250edv.27.1677736397835; Wed, 01 Mar 2023 21:53:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736397; cv=none; d=google.com; s=arc-20160816; b=GafWMYLrueg6I15ZIkswnSgnLNFo33c3INODrU8Q0sZgQp3csG8sMkL0qaZV5TN34l T/02DD2woYceAyDuR7GGhrgrm0ZMnQ0WJdCzC/q+GfL28YcNz9tEnvHwOq4cBdQfTBH+ PFZb2gEa19PzsSsL5ep8v6F5RnEScqdKNB1yirhuw0sSi18onTe5PYOYCI6qiexUws9j suXM8W7h1/MqbF83VUEMY9CnuknewBO9jnhXJaHTJ5LbgELo1fJ3wQIs7hzwybISAi2t HlY7laaeoBvr5QuoUFbZHpwfFkg4HfNNfPDSGtL1rqduEqrXfmsNBb7mO9NSYIxQYtIB qaPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KMqggURA2a0xPPHvMAq7UcLQB8jEYYPYmRFWzEuSg7o=; b=u3vpfUM8G8bLapZFFnULPMUMq4JBrsWBXdhmyb7Dv5npyS04Am2QIogUmkDII4NzmH 7+5O5nzX13EJPjM3zhNCmBT2TeMVNb7Lcmoxrc8HleTaB+lP9VKkKP0EemtB3/AEYzzm +8FYXsbWFQBZRGhW+CWeuf+Kc3nPAxSQljpWeCiMpIxK2y1xVz5uDlHwSnw8C8zVhMYs tV6ODm89DzuK4YCvv42cFz8GwyFpSgldSpBx7pyJXhZwrvkvVYmYqoKMF8+bGZ9F2Z5Z rzbaB1nhJEllqqgLCN8O6RCar3VhbglwRggwWhnYVDVSIBuNWcpLVy9bqptOJKMDmWbG wuqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Yn5nC5sb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k11-20020a05640212cb00b004ad71106d26si16457765edx.60.2023.03.01.21.52.54; Wed, 01 Mar 2023 21:53:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Yn5nC5sb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230026AbjCBFvu (ORCPT + 99 others); Thu, 2 Mar 2023 00:51:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229939AbjCBFvW (ORCPT ); Thu, 2 Mar 2023 00:51:22 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C3674FABB; Wed, 1 Mar 2023 21:50:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736259; x=1709272259; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DfbDTbcuTc/NaPEM2f1ypPU+AzEx1PFO0osNZ74tfhA=; b=Yn5nC5sb88ZnICYJkHwcsrvzJSI68BmYXvVExLlPs6T1MdBUoPo11HeV mw1YzCzQe7pc3X67mJxJw0foQT8w/+KfAy/JDelogkiDlr57RY6qb3E4y IbPPGCh2dI0EXWpyU/FWHLfDSSNI8hvVjUKg/ZbaCSYvr7GPEXMEVuHOj CjsJ8QJul/EGgq0xH8fLwL9IEbVhIu+10mtO4YBpgT++jNjVPlxahmsvc JRxvuNkbKSAoK4GY0/cwT8tqLMHd3ZzyKIqzNztbR+Jdw7ZnmM6rgvEIJ i0Qct1+Px+Z6Ji+dJpqR8sY8+95a0jmYFv7tdAoJJzVGlN9yGqW9pG0EX Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887179" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887179" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530946" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530946" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:49 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 21/34] x86/fred: FRED entry/exit and dispatch code Date: Wed, 1 Mar 2023 21:24:58 -0800 Message-Id: <20230302052511.1918-22-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234120594658758?= X-GMAIL-MSGID: =?utf-8?q?1759234120594658758?= From: "H. Peter Anvin (Intel)" The code to actually handle kernel and event entry/exit using FRED. It is split up into two files thus: - entry_64_fred.S contains the actual entrypoints and exit code, and saves and restores registers. - entry_fred.c contains the two-level event dispatch code for FRED. The first-level dispatch is on the event type, and the second-level is on the event vector. Originally-by: Megha Dey Signed-off-by: H. Peter Anvin (Intel) Co-developed-by: Xin Li Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v1: * Initialize a FRED exception handler to fred_bad_event() instead of NULL if no FRED handler defined for an exception vector (Peter Zijlstra). * Push calling irqentry_{enter,exit}() and instrumentation_{begin,end}() down into individual FRED exception handlers, instead of in the dispatch framework (Peter Zijlstra). --- arch/x86/entry/Makefile | 5 +- arch/x86/entry/entry_64_fred.S | 55 ++++++++ arch/x86/entry/entry_fred.c | 232 ++++++++++++++++++++++++++++++++ arch/x86/include/asm/idtentry.h | 8 ++ 4 files changed, 299 insertions(+), 1 deletion(-) create mode 100644 arch/x86/entry/entry_64_fred.S create mode 100644 arch/x86/entry/entry_fred.c diff --git a/arch/x86/entry/Makefile b/arch/x86/entry/Makefile index ca2fe186994b..c93e7f5c2a06 100644 --- a/arch/x86/entry/Makefile +++ b/arch/x86/entry/Makefile @@ -18,6 +18,9 @@ obj-y += vdso/ obj-y += vsyscall/ obj-$(CONFIG_PREEMPTION) += thunk_$(BITS).o +CFLAGS_entry_fred.o += -fno-stack-protector +CFLAGS_REMOVE_entry_fred.o += -pg $(CC_FLAGS_FTRACE) +obj-$(CONFIG_X86_FRED) += entry_64_fred.o entry_fred.o + obj-$(CONFIG_IA32_EMULATION) += entry_64_compat.o syscall_32.o obj-$(CONFIG_X86_X32_ABI) += syscall_x32.o - diff --git a/arch/x86/entry/entry_64_fred.S b/arch/x86/entry/entry_64_fred.S new file mode 100644 index 000000000000..1fb765fd3871 --- /dev/null +++ b/arch/x86/entry/entry_64_fred.S @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/x86/entry/entry_64_fred.S + * + * The actual FRED entry points. + */ +#include +#include +#include +#include + +#include "calling.h" + + .code64 + .section ".noinstr.text", "ax" + +.macro FRED_ENTER + UNWIND_HINT_EMPTY + PUSH_AND_CLEAR_REGS + movq %rsp, %rdi /* %rdi -> pt_regs */ +.endm + +.macro FRED_EXIT + UNWIND_HINT_REGS + POP_REGS + addq $8,%rsp /* Drop error code */ +.endm + +/* + * The new RIP value that FRED event delivery establishes is + * IA32_FRED_CONFIG & ~FFFH for events that occur in ring 3. + * Thus the FRED ring 3 entry point must be 4K page aligned. + */ + .align 4096 + +SYM_CODE_START_NOALIGN(fred_entrypoint_user) + FRED_ENTER + call fred_entry_from_user +SYM_INNER_LABEL(fred_exit_user, SYM_L_GLOBAL) + FRED_EXIT + ERETU +SYM_CODE_END(fred_entrypoint_user) + +/* + * The new RIP value that FRED event delivery establishes is + * (IA32_FRED_CONFIG & ~FFFH) + 256 for events that occur in + * ring 0, i.e., fred_entrypoint_user + 256. + */ + .org fred_entrypoint_user+256 +SYM_CODE_START_NOALIGN(fred_entrypoint_kernel) + FRED_ENTER + call fred_entry_from_kernel + FRED_EXIT + ERETS +SYM_CODE_END(fred_entrypoint_kernel) diff --git a/arch/x86/entry/entry_fred.c b/arch/x86/entry/entry_fred.c new file mode 100644 index 000000000000..8d3e144670d6 --- /dev/null +++ b/arch/x86/entry/entry_fred.c @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/x86/entry/entry_fred.c + * + * This contains the dispatch functions called from the entry point + * assembly. + */ + +#include +#include /* oops_begin/end, ... */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Badness... + */ +static DEFINE_FRED_HANDLER(fred_bad_event) +{ + irqentry_state_t irq_state = irqentry_nmi_enter(regs); + + instrumentation_begin(); + + /* Panic on events from a high stack level */ + if (regs->current_stack_level > 0) { + pr_emerg("PANIC: invalid or fatal FRED event; event type %u " + "vector %u error 0x%lx aux 0x%lx at %04x:%016lx\n", + regs->type, regs->vector, regs->orig_ax, + fred_event_data(regs), regs->cs, regs->ip); + die("invalid or fatal FRED event", regs, regs->orig_ax); + panic("invalid or fatal FRED event"); + } else { + unsigned long flags = oops_begin(); + int sig = SIGKILL; + + pr_alert("BUG: invalid or fatal FRED event; event type %u " + "vector %u error 0x%lx aux 0x%lx at %04x:%016lx\n", + regs->type, regs->vector, regs->orig_ax, + fred_event_data(regs), regs->cs, regs->ip); + + if (__die("Invalid or fatal FRED event", regs, regs->orig_ax)) + sig = 0; + + oops_end(flags, regs, sig); + } + + instrumentation_end(); + irqentry_nmi_exit(regs, irq_state); +} + +noinstr void fred_exc_double_fault(struct pt_regs *regs) +{ + exc_double_fault(regs, regs->orig_ax); +} + +/* + * Exception entry + */ +static DEFINE_FRED_HANDLER(fred_exception) +{ + /* + * Exceptions that cannot happen on FRED h/w are set to fred_bad_event(). + */ + static const fred_handler exception_handlers[NUM_EXCEPTION_VECTORS] = { + [X86_TRAP_DE] = exc_divide_error, + [X86_TRAP_DB] = fred_exc_debug, + [X86_TRAP_NMI] = fred_bad_event, /* A separate event type, not handled here */ + [X86_TRAP_BP] = exc_int3, + [X86_TRAP_OF] = exc_overflow, + [X86_TRAP_BR] = exc_bounds, + [X86_TRAP_UD] = exc_invalid_op, + [X86_TRAP_NM] = exc_device_not_available, + [X86_TRAP_DF] = fred_exc_double_fault, + [X86_TRAP_OLD_MF] = fred_bad_event, /* 387 only! */ + [X86_TRAP_TS] = fred_exc_invalid_tss, + [X86_TRAP_NP] = fred_exc_segment_not_present, + [X86_TRAP_SS] = fred_exc_stack_segment, + [X86_TRAP_GP] = fred_exc_general_protection, + [X86_TRAP_PF] = fred_exc_page_fault, + [X86_TRAP_SPURIOUS] = fred_bad_event, /* Interrupts are their own event type */ + [X86_TRAP_MF] = exc_coprocessor_error, + [X86_TRAP_AC] = fred_exc_alignment_check, + [X86_TRAP_MC] = fred_exc_machine_check, + [X86_TRAP_XF] = exc_simd_coprocessor_error, + [X86_TRAP_VE...NUM_EXCEPTION_VECTORS-1] = fred_bad_event + }; + u8 vector = array_index_nospec((u8)regs->vector, NUM_EXCEPTION_VECTORS); + + exception_handlers[vector](regs); +} + +static __always_inline void fred_emulate_trap(struct pt_regs *regs) +{ + regs->type = EVENT_TYPE_SWFAULT; + regs->orig_ax = 0; + fred_exception(regs); +} + +static __always_inline void fred_emulate_fault(struct pt_regs *regs) +{ + regs->ip -= regs->instr_len; + fred_emulate_trap(regs); +} + +/* + * Emulate SYSENTER if applicable. This is not the preferred system + * call in 32-bit mode under FRED, rather int $0x80 is preferred and + * exported in the vdso. SYSCALL proper has a hard-coded early out in + * fred_entry_from_user(). + */ +static DEFINE_FRED_HANDLER(fred_syscall_slow) +{ + if (IS_ENABLED(CONFIG_IA32_EMULATION) && + likely(regs->vector == FRED_SYSENTER)) { + /* Convert frame to a syscall frame */ + regs->orig_ax = regs->ax; + regs->ax = -ENOSYS; + do_fast_syscall_32(regs); + } else { + regs->vector = X86_TRAP_UD; + fred_emulate_fault(regs); + } +} + +/* + * Some software exceptions can also be triggered as int instructions, + * for historical reasons. Implement those here. The performance-critical + * int $0x80 (32-bit system call) has a hard-coded early out. + */ +static DEFINE_FRED_HANDLER(fred_sw_interrupt_user) +{ + if (IS_ENABLED(CONFIG_IA32_EMULATION) && + likely(regs->vector == IA32_SYSCALL_VECTOR)) { + /* Convert frame to a syscall frame */ + regs->orig_ax = regs->ax; + regs->ax = -ENOSYS; + return do_int80_syscall_32(regs); + } + + switch (regs->vector) { + case X86_TRAP_BP: + case X86_TRAP_OF: + fred_emulate_trap(regs); + break; + default: + regs->vector = X86_TRAP_GP; + fred_emulate_fault(regs); + break; + } +} + +static DEFINE_FRED_HANDLER(fred_hw_interrupt) +{ + irqentry_state_t state = irqentry_enter(regs); + + instrumentation_begin(); + external_interrupt(regs, regs->vector); + instrumentation_end(); + irqentry_exit(regs, state); +} + +__visible noinstr void fred_entry_from_user(struct pt_regs *regs) +{ + static const fred_handler user_handlers[FRED_EVENT_TYPE_COUNT] = + { + [EVENT_TYPE_HWINT] = fred_hw_interrupt, + [EVENT_TYPE_RESERVED] = fred_bad_event, + [EVENT_TYPE_NMI] = fred_exc_nmi, + [EVENT_TYPE_SWINT] = fred_sw_interrupt_user, + [EVENT_TYPE_HWFAULT] = fred_exception, + [EVENT_TYPE_SWFAULT] = fred_exception, + [EVENT_TYPE_PRIVSW] = fred_exception, + [EVENT_TYPE_OTHER] = fred_syscall_slow + }; + + /* + * FRED employs a two-level event dispatch mechanism, with + * the first-level on the type of an event and the second-level + * on its vector. Thus a dispatch typically induces 2 calls. + * We optimize it by using early outs for the most frequent + * events, and syscalls are the first. We may also need early + * outs for page faults. + */ + if (likely(regs->type == EVENT_TYPE_OTHER && + regs->vector == FRED_SYSCALL)) { + /* Convert frame to a syscall frame */ + regs->orig_ax = regs->ax; + regs->ax = -ENOSYS; + do_syscall_64(regs, regs->orig_ax); + } else { + /* Not a system call */ + u8 type = array_index_nospec((u8)regs->type, FRED_EVENT_TYPE_COUNT); + + user_handlers[type](regs); + } +} + +static DEFINE_FRED_HANDLER(fred_sw_interrupt_kernel) +{ + switch (regs->vector) { + case X86_TRAP_NMI: + fred_exc_nmi(regs); + break; + default: + fred_bad_event(regs); + break; + } +} + +__visible noinstr void fred_entry_from_kernel(struct pt_regs *regs) +{ + static const fred_handler kernel_handlers[FRED_EVENT_TYPE_COUNT] = + { + [EVENT_TYPE_HWINT] = fred_hw_interrupt, + [EVENT_TYPE_RESERVED] = fred_bad_event, + [EVENT_TYPE_NMI] = fred_exc_nmi, + [EVENT_TYPE_SWINT] = fred_sw_interrupt_kernel, + [EVENT_TYPE_HWFAULT] = fred_exception, + [EVENT_TYPE_SWFAULT] = fred_exception, + [EVENT_TYPE_PRIVSW] = fred_exception, + [EVENT_TYPE_OTHER] = fred_bad_event + }; + u8 type = array_index_nospec((u8)regs->type, FRED_EVENT_TYPE_COUNT); + + /* The pt_regs frame on entry here is an exception frame */ + kernel_handlers[type](regs); +} diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentry.h index 2876ddae02bc..bd43866f9c3e 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -82,6 +82,7 @@ static __always_inline void __##func(struct pt_regs *regs) #define DECLARE_IDTENTRY_ERRORCODE(vector, func) \ asmlinkage void asm_##func(void); \ asmlinkage void xen_asm_##func(void); \ + __visible void fred_##func(struct pt_regs *regs); \ __visible void func(struct pt_regs *regs, unsigned long error_code) /** @@ -106,6 +107,11 @@ __visible noinstr void func(struct pt_regs *regs, \ irqentry_exit(regs, state); \ } \ \ +__visible noinstr void fred_##func(struct pt_regs *regs) \ +{ \ + func (regs, regs->orig_ax); \ +} \ + \ static __always_inline void __##func(struct pt_regs *regs, \ unsigned long error_code) @@ -622,6 +628,8 @@ DECLARE_IDTENTRY_RAW(X86_TRAP_MC, exc_machine_check); #ifdef CONFIG_XEN_PV DECLARE_IDTENTRY_RAW(X86_TRAP_MC, xenpv_exc_machine_check); #endif +#else +#define fred_exc_machine_check fred_bad_event #endif /* NMI */ From patchwork Thu Mar 2 05:24:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63230 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063661wrd; Wed, 1 Mar 2023 21:53:48 -0800 (PST) X-Google-Smtp-Source: AK7set8fUagFBjMcFlC0FLVANjtueWatEysZevEAIUOdFAptA1+raYp9OYjPD79csgteie84tBkO X-Received: by 2002:a17:906:d191:b0:8b1:3225:66f0 with SMTP id c17-20020a170906d19100b008b1322566f0mr9071091ejz.68.1677736427800; Wed, 01 Mar 2023 21:53:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736427; cv=none; d=google.com; s=arc-20160816; b=tEpdlHVJbF2Ngba5Gj3cwaTVsYT8Z7GezRzZgCqOoqBFVVFufCfgPgekswJzC21azS DnW1M8nY4hZj4Yaut9vOnJw+WiUP+OpO7t+woyfuAVjzrGAGCqYanOhll6KDtGNzqurV I5s/qO3y5TqlWzduyVLz9b360mjIsJgEwU6P4lD0omfPng40hudYX5QYz89MJ1jpHGt3 /FiEYQnEWYZB4fbcmFaqQAo1QJ4Kpja1tdE/ceaUy5PJflJRv+Gpml57RD9RXiA35aW0 KaVCt0ZBO6M0auGEBNGnRbsMfEm2NdA8+UoTmAPAAUq10Z4tgViPoqnTv8XT8HufLBYd ixjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=n2G8OriNYvMHXbMJyivNUqkFjrJPHQRB1xxvHa2TK+Q=; b=XsJdtErjfXari7jCD6z/SLdsouHQd3h5dT3k8yM3SGiYrQqn3hlptBo+eDMiE8QLnt /yWXcq0phSxf0iMdIuv3pIZXvwPQHiSXnuei+gpwiiZDFneh3/3u0iHF3ik4CkhqZGzV 3tygEwetyET6bTvw6L72hkGCWYPJYvuw7n+pFr+LNDY0UPeNlmVtVHhNtPdmAJJWRbOe liUbV8eGWaH2o5q/KKsoYoRaUnED4Kiu8akx6yylTs7rvLvkHA9fm2ShZ37YLLMg2UFt iz1MtDae/6EpEa/cqf0f8WhiwryPJRFeaMECa/bcGYkejqwx79PNeo5Dkfzla60sqY/L MFEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=cDBI1821; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id br19-20020a170906d15300b008b17d4012c0si2414473ejb.145.2023.03.01.21.53.24; Wed, 01 Mar 2023 21:53:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=cDBI1821; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230081AbjCBFwe (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230050AbjCBFvy (ORCPT ); Thu, 2 Mar 2023 00:51:54 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98B794DBF0; Wed, 1 Mar 2023 21:51:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736270; x=1709272270; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JbvAq9INt68NatqqmP2U9nOnHNc976vHMsLHgFC3s2k=; b=cDBI1821DHgfKVc45MhxXo6gBjKziRQ/PTeaCpv+YhmcEaRRS2rtT4Va z0FwOOGsJq6kjAA9mvubjZtGa2BFvYe3kDHynskkHBK3n6D4NKCO8pE1P NQCqWp7+mqbHLuBmVghEGa8PrZes4pB+sshT1A3iD0RIZ2yboGrQIWbVx onvFTfiDi2627n53M16+SQpLLA9yUgtVFLR5DHXqLmaYlM1p/Jo2/yvoj LERJrgTGNTeD52nw7bAO4yYsPuAigVQ7locQkZdPNBvtPLYnErJgKXBjB fTC90SQaoQaXirR9Mkpxpi+OU7K9QDXBbkV7WFE7wL8B0CA382QFgV1oZ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887241" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887241" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530949" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530949" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:49 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 22/34] x86/fred: FRED initialization code Date: Wed, 1 Mar 2023 21:24:59 -0800 Message-Id: <20230302052511.1918-23-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234152391733043?= X-GMAIL-MSGID: =?utf-8?q?1759234152391733043?= From: "H. Peter Anvin (Intel)" The code to initialize FRED when it's available and _not_ disabled. cpu_init_fred_exceptions() is the core function to initialize FRED, which 1. Sets up FRED entrypoints for events happening in ring 0 and 3. 2. Sets up a default stack for event handling. 3. Sets up dedicated event stacks for DB/NMI/MC/DF, equivalent to the IDT IST stacks. 4. Forces 32-bit system calls to use "int $0x80" only. 5. Enables FRED and invalidtes IDT. When the FRED is used, cpu_init_exception_handling() initializes FRED through calling cpu_init_fred_exceptions(), otherwise it sets up TSS IST and loads IDT. As FRED uses the ring 3 FRED entrypoint for SYSCALL and SYSENTER, it skips setting up SYSCALL/SYSENTER related MSRs, e.g., MSR_LSTAR. Signed-off-by: H. Peter Anvin (Intel) Co-developed-by: Xin Li Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 14 +++++++ arch/x86/include/asm/traps.h | 2 + arch/x86/kernel/Makefile | 1 + arch/x86/kernel/cpu/common.c | 74 +++++++++++++++++++++++------------- arch/x86/kernel/fred.c | 73 +++++++++++++++++++++++++++++++++++ arch/x86/kernel/irqinit.c | 7 +++- arch/x86/kernel/traps.c | 16 +++++++- 7 files changed, 157 insertions(+), 30 deletions(-) create mode 100644 arch/x86/kernel/fred.c diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 54746e8c0a17..cd974edc8e8a 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -99,8 +99,22 @@ DECLARE_FRED_HANDLER(fred_exc_debug); DECLARE_FRED_HANDLER(fred_exc_page_fault); DECLARE_FRED_HANDLER(fred_exc_machine_check); +/* + * The actual assembly entry and exit points + */ +extern __visible void fred_entrypoint_user(void); + +/* + * Initialization + */ +void cpu_init_fred_exceptions(void); +void fred_setup_apic(void); + #endif /* __ASSEMBLY__ */ +#else +#define cpu_init_fred_exceptions() BUG() +#define fred_setup_apic() BUG() #endif /* CONFIG_X86_FRED */ #endif /* ASM_X86_FRED_H */ diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index da4c21ed68b4..69fafef1136e 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -56,6 +56,8 @@ void __noreturn handle_stack_overflow(struct pt_regs *regs, void f (struct pt_regs *regs) typedef DECLARE_SYSTEM_INTERRUPT_HANDLER((*system_interrupt_handler)); +system_interrupt_handler get_system_interrupt_handler(unsigned int i); + int external_interrupt(struct pt_regs *regs, unsigned int vector); #endif /* _ASM_X86_TRAPS_H */ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index dd61752f4c96..08d9c0a0bfbe 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -47,6 +47,7 @@ obj-y += platform-quirks.o obj-y += process_$(BITS).o signal.o signal_$(BITS).o obj-y += traps.o idt.o irq.o irq_$(BITS).o dumpstack_$(BITS).o obj-y += time.o ioport.o dumpstack.o nmi.o +obj-$(CONFIG_X86_FRED) += fred.o obj-$(CONFIG_MODIFY_LDT_SYSCALL) += ldt.o obj-y += setup.o x86_init.o i8259.o irqinit.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index e8cf6f4cfb52..eea41cb8722e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -58,6 +58,7 @@ #include #include #include +#include #include #include #include @@ -2054,28 +2055,6 @@ static void wrmsrl_cstar(unsigned long val) /* May not be marked __init: used by software suspend */ void syscall_init(void) { - wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); - wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); - -#ifdef CONFIG_IA32_EMULATION - wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); - /* - * This only works on Intel CPUs. - * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. - * This does not cause SYSENTER to jump to the wrong location, because - * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). - */ - wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, - (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); - wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); -#else - wrmsrl_cstar((unsigned long)ignore_sysret); - wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); - wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); -#endif - /* * Flags to clear on syscall; clear as much as possible * to minimize user space-kernel interference. @@ -2086,6 +2065,41 @@ void syscall_init(void) X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| X86_EFLAGS_AC|X86_EFLAGS_ID); + + /* + * The default user and kernel segments + */ + wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); + + if (cpu_feature_enabled(X86_FEATURE_FRED)) { + /* Both sysexit and sysret cause #UD when FRED is enabled */ + wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); + } else { + wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); + +#ifdef CONFIG_IA32_EMULATION + wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); + /* + * This only works on Intel CPUs. + * On AMD CPUs these MSRs are 32-bit, CPU truncates + * MSR_IA32_SYSENTER_EIP. + * This does not cause SYSENTER to jump to the wrong + * location, because AMD doesn't allow SYSENTER in + * long mode (either 32- or 64-bit). + */ + wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, + (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); +#else + wrmsrl_cstar((unsigned long)ignore_sysret); + wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); +#endif + } } #else /* CONFIG_X86_64 */ @@ -2218,18 +2232,24 @@ void cpu_init_exception_handling(void) /* paranoid_entry() gets the CPU number from the GDT */ setup_getcpu(cpu); - /* IST vectors need TSS to be set up. */ - tss_setup_ist(tss); + /* Set up the TSS */ tss_setup_io_bitmap(tss); set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); - load_TR_desc(); /* GHCB needs to be setup to handle #VC. */ setup_ghcb(); - /* Finally load the IDT */ - load_current_idt(); + if (cpu_feature_enabled(X86_FEATURE_FRED)) { + /* Set up FRED exception handling */ + cpu_init_fred_exceptions(); + } else { + /* IST vectors need TSS to be set up. */ + tss_setup_ist(tss); + + /* Finally load the IDT */ + load_current_idt(); + } } /* diff --git a/arch/x86/kernel/fred.c b/arch/x86/kernel/fred.c new file mode 100644 index 000000000000..827b58fd98d4 --- /dev/null +++ b/arch/x86/kernel/fred.c @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include +#include +#include /* For cr4_set_bits() */ +#include + +/* + * Initialize FRED on this CPU. This cannot be __init as it is called + * during CPU hotplug. + */ +void cpu_init_fred_exceptions(void) +{ + wrmsrl(MSR_IA32_FRED_CONFIG, + FRED_CONFIG_ENTRYPOINT(fred_entrypoint_user) | + FRED_CONFIG_REDZONE(8) | /* Reserve for CALL emulation */ + FRED_CONFIG_INT_STKLVL(0)); + + wrmsrl(MSR_IA32_FRED_STKLVLS, + FRED_STKLVL(X86_TRAP_DB, 1) | + FRED_STKLVL(X86_TRAP_NMI, 2) | + FRED_STKLVL(X86_TRAP_MC, 2) | + FRED_STKLVL(X86_TRAP_DF, 3)); + + /* The FRED equivalents to IST stacks... */ + wrmsrl(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(DB)); + wrmsrl(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(NMI)); + wrmsrl(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(DF)); + + /* Not used with FRED */ + wrmsrl(MSR_LSTAR, 0ULL); + wrmsrl(MSR_CSTAR, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); + + /* Enable FRED */ + cr4_set_bits(X86_CR4_FRED); + idt_invalidate(); /* Any further IDT use is a bug */ + + /* Use int $0x80 for 32-bit system calls in FRED mode */ + setup_clear_cpu_cap(X86_FEATURE_SYSENTER32); + setup_clear_cpu_cap(X86_FEATURE_SYSCALL32); +} + +/* + * Initialize system vectors from a FRED perspective, so + * lapic_assign_system_vectors() can do its job. + */ +void __init fred_setup_apic(void) +{ + int i; + + for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) + set_bit(i, system_vectors); + + /* + * Don't set the non assigned system vectors in the + * system_vectors bitmap. Otherwise they show up in + * /proc/interrupts. + */ +#ifdef CONFIG_SMP + set_bit(IRQ_MOVE_CLEANUP_VECTOR, system_vectors); +#endif + + for (i = 0; i < NR_SYSTEM_VECTORS; i++) { + if (get_system_interrupt_handler(i) != NULL) { + set_bit(i + FIRST_SYSTEM_VECTOR, system_vectors); + } + } + + /* The rest are fair game... */ +} diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c index c683666876f1..2a510f72dd11 100644 --- a/arch/x86/kernel/irqinit.c +++ b/arch/x86/kernel/irqinit.c @@ -28,6 +28,7 @@ #include #include #include +#include #include /* @@ -96,7 +97,11 @@ void __init native_init_IRQ(void) /* Execute any quirks before the call gates are initialised: */ x86_init.irqs.pre_vector_init(); - idt_setup_apic_and_irq_gates(); + if (cpu_feature_enabled(X86_FEATURE_FRED)) + fred_setup_apic(); + else + idt_setup_apic_and_irq_gates(); + lapic_assign_system_vectors(); if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) { diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 4b0f63344526..c7253b4901f0 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1517,12 +1517,21 @@ static system_interrupt_handler system_interrupt_handlers[NR_SYSTEM_VECTORS] = { #undef SYSV +system_interrupt_handler get_system_interrupt_handler(unsigned int i) +{ + if (i >= NR_SYSTEM_VECTORS) + return NULL; + + return system_interrupt_handlers[i]; +} + void __init install_system_interrupt_handler(unsigned int n, const void *asm_addr, const void *addr) { BUG_ON(n < FIRST_SYSTEM_VECTOR); system_interrupt_handlers[n - FIRST_SYSTEM_VECTOR] = (system_interrupt_handler)addr; - alloc_intr_gate(n, asm_addr); + if (!cpu_feature_enabled(X86_FEATURE_FRED)) + alloc_intr_gate(n, asm_addr); } #ifndef CONFIG_X86_LOCAL_APIC @@ -1590,7 +1599,10 @@ void __init trap_init(void) /* Initialize TSS before setting up traps so ISTs work */ cpu_init_exception_handling(); + /* Setup traps as cpu_init() might #GP */ - idt_setup_traps(); + if (!cpu_feature_enabled(X86_FEATURE_FRED)) + idt_setup_traps(); + cpu_init(); } From patchwork Thu Mar 2 05:25:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63228 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063617wrd; Wed, 1 Mar 2023 21:53:39 -0800 (PST) X-Google-Smtp-Source: AK7set+W7Lzd5coPUWiQ3lyifHgTkfbRgwnME4ICYrqvbzLsga7R1w7LSXnKuiiu2oIKr9Sp3OD7 X-Received: by 2002:a17:907:8b17:b0:900:a150:cea5 with SMTP id sz23-20020a1709078b1700b00900a150cea5mr11734589ejc.54.1677736419077; Wed, 01 Mar 2023 21:53:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736419; cv=none; d=google.com; s=arc-20160816; b=d6BP2J26D/7t2P0WMx7OdiGIK4Jr7nxzH/t/9aHyO+2MH7KmwXzMCIKLYVzgOfUVcS xTC5B0DAJKk24FjlZ1QybLjHy3YuFc4BX5MxSjRfYU7iMyUH5A7aanaaLFuGCHj+8MHE tkV/Q7P+q5S3iU8Sb+jcCbZTynQuneiNKYIZ0QCO14Y/ig4a0RX4qT3AdHkjuncRGd3T 6VCzbyG7Rro1GM7toylTIy4kIk6oP9o/l4m8sA7QIn1xuC5ZRb/5hMvkacsS9Wp86eOO Xf9OmuVEKVXJPROBaDYjFih7ld6EXJwA6HPV9+EBVvJYP5Cb75hx0VfLsFaaRrJfACPO DUQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=o/s4OgoBvlYE/i/ueeuD809hBfxz0iI2J7KU1Tu8hr0=; b=aXCErqfpdFNbQsunmAHZ4Wlcakiu6yecLzESUZ2mUAG7JnEMrBYI55BvIcViJ7ABIv xJQM4dhV9hiJXlCABqIo8jQUdWd34fkG4cninrXuQ2+a8iKQ8BZTxmoPg8pDUqncrphN xTCQiHjrianxjfkplUf6zLpV0nyhaBwxuRjN3aug7Ew1NssUe0l7vHbYIPimdgkhKaNZ nnJfV3wrcF9qtO2klw28eTNipeyfYSV8BJIOfFuJ2nnR+wUDJss85dUd6xKZ1mu+4k9a PHSG+eMh39C/1FH5UHq1BO20vtbdZlttO0zY05l0uo20sniMJd0jFh3RPEZ3epFePH2P 47Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Zmw+nEZM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a21-20020aa7d915000000b004ab1c20c759si5350620edr.543.2023.03.01.21.53.16; Wed, 01 Mar 2023 21:53:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Zmw+nEZM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230048AbjCBFw2 (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229496AbjCBFvw (ORCPT ); Thu, 2 Mar 2023 00:51:52 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E1274DE12; Wed, 1 Mar 2023 21:51:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736269; x=1709272269; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SfNRJW38HST/J2vYBy+d2Rz7YNwfS+VaJzsap6qMLmE=; b=Zmw+nEZMsh5OaGqBExIrVm8w3i4BOWz5VTMkQzlKk5rrPyEA7quVJvUD dtXVM4An7T+cNlpaVd2P3VavVdrLjrlkWoTQow5wXhagMHsehv3z2WjDr Y4RXvMWQDjPBCaiIyLDl+49sN9vh4eqNo7QYit27CqRIX09G3d2z3bjZs +CCR5Y4H0054iktjAWcRXOHg9Ukuy+x8/KlhHnk3OQaf6UmI4WNjpxVkq pc3+7w3/dKYovaVUaTLMoPCyZDx7LR+xsyMAxhK8wIC1eS4d0KPx0AIhF MzlqcqBhgEVwvEBSIsrPCIDzPQjlR8kpyw4jM+q9FkOFoqt7SE9d4t6v2 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887232" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887232" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530951" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530951" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:49 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 23/34] x86/fred: update MSR_IA32_FRED_RSP0 during task switch Date: Wed, 1 Mar 2023 21:25:00 -0800 Message-Id: <20230302052511.1918-24-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234143127919678?= X-GMAIL-MSGID: =?utf-8?q?1759234143127919678?= From: "H. Peter Anvin (Intel)" MSR_IA32_FRED_RSP0 is used during ring 3 event delivery, and needs to be updated to point to the top of next task stack during task switch. Update MSR_IA32_FRED_RSP0 with WRMSR instruction for now, and will use WRMSRNS/WRMSRLIST for performance once it gets upstreamed. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/switch_to.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index 5c91305d09d2..00fd85abc1d2 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -68,9 +68,16 @@ static inline void update_task_stack(struct task_struct *task) #ifdef CONFIG_X86_32 this_cpu_write(cpu_tss_rw.x86_tss.sp1, task->thread.sp0); #else - /* Xen PV enters the kernel on the thread stack. */ - if (cpu_feature_enabled(X86_FEATURE_XENPV)) + if (cpu_feature_enabled(X86_FEATURE_FRED)) { + /* + * Will use WRMSRNS/WRMSRLIST for performance once it's upstreamed. + */ + wrmsrl(MSR_IA32_FRED_RSP0, + task_top_of_stack(task) + TOP_OF_KERNEL_STACK_PADDING); + } else if (cpu_feature_enabled(X86_FEATURE_XENPV)) { + /* Xen PV enters the kernel on the thread stack. */ load_sp0(task_top_of_stack(task)); + } #endif } From patchwork Thu Mar 2 05:25:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63231 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063714wrd; Wed, 1 Mar 2023 21:53:56 -0800 (PST) X-Google-Smtp-Source: AK7set/xo5sykpZdaXAu/6mty2D3xmQqJfybtbYhxNbwok/SiWhSDfi8nQr2fPGYCpP4nJJEeMBa X-Received: by 2002:a05:6402:189:b0:4a0:e31a:434 with SMTP id r9-20020a056402018900b004a0e31a0434mr8274987edv.27.1677736436355; Wed, 01 Mar 2023 21:53:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736436; cv=none; d=google.com; s=arc-20160816; b=k3sJFfblDlR9yH9be6NQrxcah3z/xlFu0E+x5WgULh90lF+h8ryhzewqhmbFwmDnoi KRWkYZ0V0cuCZyXJXUCqdleL0xdukcxkt11TXVg1QTvYWzisz7pSe/DrNReJB+1o+YFj iDnBbhWA6gDb4yaXmzH9jE6sK8Gbx9tvyc5zroGC3hJNiSQIoEQIAuy2Q5WzfmfgunxV iwIATi1gHv8o8chA93WZErBi5ZW+C6l3PQb4fTdmIasSFKjPQiFaoJ64ZUdjyPlCgQvB hSwcOhEO+4go3ssoaFvftFDeW+AGnccxmCTmL/DQN41TF27NdCM/dRSkODECBxH90pU8 ejpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4BTz/OYFP659MTV9jAlMUDj6IzhLOKvkYwE26MSR2Sg=; b=dGhfpL5dF5UVm5NDvnIc/bQbMV0uOYWUG3eH9/P8FrdOS756/NmPn9Dzy6PKzScga4 kNXszLFHOwrzB4CNEwFiY8VUaj08QaXxd6knHOFXLDlhiwsV4vKUh8h9umffVM4IbiCs 92rgKB1qeGEWCOEhUuKLp+eIKM3QzfagP0AYaoFs8ws3TsMeha2yZSEUUpZlixv9aqEb vi542UCr4XvEcjx2gP+tajmx1H6qWcWe7+zFA5X1lpg0fZuePWI2mbbVOs06J72QZ/DL cp1e02kvz5wa+Zc+NkKLBBslJaSCxppi+TacaEkolmZxpVJp5BfncZupBvwhBqqJaSGP Amiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=SMfaJpmT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id lf22-20020a170906ae5600b008be2daad941si16405255ejb.648.2023.03.01.21.53.33; Wed, 01 Mar 2023 21:53:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=SMfaJpmT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229998AbjCBFwt (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229988AbjCBFwR (ORCPT ); Thu, 2 Mar 2023 00:52:17 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9E77515C8; Wed, 1 Mar 2023 21:51:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736279; x=1709272279; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dQrYcTRM4xVVKpWEBRpp2gh8m1WDXg1zEAfOSTgEfys=; b=SMfaJpmTdnGP2YeSs8uNdFfQWmfprf/klOvS4uq3tMfUm2zpeNzYIHoX 308BCxIwwjfNvsIiJSprxdw8E6fHly0BRAv/Ut7jQEa+hUeOmfDY3+ATe ChpO85h/c9fv1A2yoQfwuErePmy/+r+rmCggauA7yHgxDbnhkcC9xB9NG +pbG+km+hdCr3G3i30YKgVew0FVrDJeEThwl82zzrf8U3NrK9gm/zsw+z qYPA4paMdAOaS1NBSJAd3uOUu0CXylvn0wOSp8boaRDRiDfSBWQ/Wsszo JAI7Qnh0+yRaGlq5yUKw9OM48dW7dOD6HwKpe3i0zt77hmqF4wP+IdyuF A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887256" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887256" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530954" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530954" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:50 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 24/34] x86/fred: let ret_from_fork() jmp to fred_exit_user when FRED is enabled Date: Wed, 1 Mar 2023 21:25:01 -0800 Message-Id: <20230302052511.1918-25-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234161503263034?= X-GMAIL-MSGID: =?utf-8?q?1759234161503263034?= From: "H. Peter Anvin (Intel)" Let ret_from_fork() jmp to fred_exit_user when FRED is enabled, otherwise the existing IDT code is chosen. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 7ecd2aeeeffc..7ffd20578b8c 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -299,7 +299,12 @@ SYM_CODE_START_NOALIGN(ret_from_fork) UNWIND_HINT_REGS movq %rsp, %rdi call syscall_exit_to_user_mode /* returns with IRQs disabled */ +#ifdef CONFIG_X86_FRED + ALTERNATIVE "jmp swapgs_restore_regs_and_return_to_usermode", \ + "jmp fred_exit_user", X86_FEATURE_FRED +#else jmp swapgs_restore_regs_and_return_to_usermode +#endif 1: /* kernel thread */ From patchwork Thu Mar 2 05:25:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63241 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4068811wrd; Wed, 1 Mar 2023 22:08:30 -0800 (PST) X-Google-Smtp-Source: AK7set84zIGw2gxYXJCXMlvJdpjCNnWMsIVSTcVAmd7DhDAR1MC5p2ioCNGWxjkQLDAJ9b2UoDCa X-Received: by 2002:a05:6a21:6da1:b0:cc:c69b:f7e5 with SMTP id wl33-20020a056a216da100b000ccc69bf7e5mr11090529pzb.9.1677737309767; Wed, 01 Mar 2023 22:08:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677737309; cv=none; d=google.com; s=arc-20160816; b=N1hTy2kRqHYY6txyqItpUZq4+jHs0FyEyjktezenAXRNGIkwjTDwofBcelmVe/50gt 4TZ4MVWgl4hjrix4psJwA8gbRC5Rn7FX712tMTZwUgPKkU9rgzTB+YtRgbRxlZXUUSfe v4CAK/WFKhfpWMCFLOqPzUHAw6OuM+ltKc04f2aZSQuIVjflBwrmAkn8ZGD3z8Er+yEG YiaXkpDms33jKme6ejmGNiKhPS6uFccT9FdFKUNKo/98nLVHPbofPhIbPoELgKN3be+B KpS3ybhd6Wco7aGXrXi/BQaazhtrNpN9pzlMA7Zv3uBLuCcxIAGXxQv/8pszQ8ejYRZ+ AVcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CAwwHxdmySeTwUiXJxBjwIE6ec+fx+NkUFLB6oSL6+I=; b=MQ+zHKocd7/1VIBxEIAX33SWbqkI4uIyfZ6SjgOTh8TvyOOPuxibwEfP0oC3oUL6w9 2C9GFv9g2kotLZfkyfesq/IMMoWn79rUqyoaEx1waKpyDHo/LIySd+eiTEFRU/6QaAt/ H1PE1rI/NTXxu0tkzafjFyf5ZfArDWUhIOa5xBiqWIB+LhYAdWTe3a/pEpYay1PvAfSZ HkrgONYykgN1hWWyzJFIX2jY545h2//Tnbqf3sMJNPh71VuyVrypi0FepjF7Hy1Y1eKB brRRL7sJe3tTEno2ZR+N++3NjtfeV01iJgjZPbkpWQ/ry4fDUItXui22B5yLA8PgxOM7 5R1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="ka5ay/5T"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w189-20020a6382c6000000b004fb42dcc3b0si14635745pgd.710.2023.03.01.22.08.16; Wed, 01 Mar 2023 22:08:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="ka5ay/5T"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230124AbjCBFw7 (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230098AbjCBFwW (ORCPT ); Thu, 2 Mar 2023 00:52:22 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8F64532AE; Wed, 1 Mar 2023 21:51:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736285; x=1709272285; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JCKu4lASdy4fofKGHW4gy5ePwfNi7YQxHJ13+kwlv3k=; b=ka5ay/5TeN2UCtOgI6Y2fZeGibJS4uC1tORRFgivbbhHh3rTbb9+VdQH LkceHnsNJhODN6WvYOVhAkzgUPZVnQZfF119eMr55J7dJokQS7jotg4nN 8uebwA21T/7Q7T1bxfKjmbY3Bmk/Pbd6xblY5zzYikdqVtzCwLM1YO3nJ jz7qazwr3AxK8b83OIjNQUB13HW+HuvKZX1JPZ1gsJovv5LhNP7H+tP/Z auMVvLqm5ZYC2HZslxQM9K6qUw0s+UXnnbb8+GP+13bCOluSoDmgiSL07 88neN2qZzArMxT0KmTN28w+9fPABmaL8ZFN5uBcChuWcoa4yANAuGVad6 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887283" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887283" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530956" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530956" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:50 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 25/34] x86/fred: disallow the swapgs instruction when FRED is enabled Date: Wed, 1 Mar 2023 21:25:02 -0800 Message-Id: <20230302052511.1918-26-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759235077445535678?= X-GMAIL-MSGID: =?utf-8?q?1759235077445535678?= From: "H. Peter Anvin (Intel)" The FRED architecture establishes the full supervisor/user through: 1) FRED event delivery swaps the value of the GS base address and that of the IA32_KERNEL_GS_BASE MSR. 2) ERETU swaps the value of the GS base address and that of the IA32_KERNEL_GS_BASE MSR. Thus, the swapgs instruction is disallowed when FRED is enabled, otherwise it cauess #UD. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/process_64.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 57de166dc61c..ff6594dbea4a 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -165,7 +165,8 @@ static noinstr unsigned long __rdgsbase_inactive(void) lockdep_assert_irqs_disabled(); - if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + !cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); gsbase = rdgsbase(); native_swapgs(); @@ -190,7 +191,8 @@ static noinstr void __wrgsbase_inactive(unsigned long gsbase) { lockdep_assert_irqs_disabled(); - if (!cpu_feature_enabled(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + !cpu_feature_enabled(X86_FEATURE_XENPV)) { native_swapgs(); wrgsbase(gsbase); native_swapgs(); From patchwork Thu Mar 2 05:25:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63234 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063948wrd; Wed, 1 Mar 2023 21:54:43 -0800 (PST) X-Google-Smtp-Source: AK7set80gfHUcEK+mRlHe9RYynz/iPM41uZjZxKt2zCr1TQfJTJsegvEdw5kb1+XwfFdUXajq3YZ X-Received: by 2002:a17:907:7e82:b0:8ab:4c4:d0f6 with SMTP id qb2-20020a1709077e8200b008ab04c4d0f6mr12478906ejc.56.1677736483186; Wed, 01 Mar 2023 21:54:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736483; cv=none; d=google.com; s=arc-20160816; b=m7KIrymuBjw1uwPD2cGJglYTnVEjkG2dtVFtNMkCTsvptghS0nFxwZsz0tDYrrumX4 xqz6ICIGLwd4QwZcUAE3HMvyWutKubCP33Svarb6FkXyxMAXh2AJ/7id+0gcYfRrEoib tt2NMsxBsIsv5Q9RDzXWrZlYBo8cpWrhZvAKibKfd95CttobGXGQ+ykK8TPvRkXP2n1H awgl/2UGc2i8eV+laNJ0qUB9dtgHJDIS8ikp3zY3c8/uUZ69hLu8LAFgrLWrY3gv1P0o +il8pd9vDTQ1WGSLx2FsbLCwgA7D3KxPngtFNH/3MpvvaKrHVMOVO5xD4ICRXDxQZh2Y iHEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vxjy11Tsv/mgkUj27ibhp2UA7uqHHL7WLXhaKKIvcCY=; b=b37DfR3WVKiPJcRwEYsQbE1kCGZRR5ETunOazv2CkcHuiAK3aF3rnaUY34bBnKstK4 KLM6o1ltKOmyYZjtv6nlAc7XiwyuQZ8aruFO14FSiPpo1gw27VBbqHZwZu8YTg0/YjMn v/cqcGQPiMrd/YveLWf4x95YDMVqDxP+/U5txVPoHk9qDBsFlrWFAxxSKhugZY8vCfXJ e0x3w861e6NLyir5Fm157O+wj5LJ0u+mKWEJLnyzcD+2T/07EaPHyk0/TY2erfRB3Uuv 3IhMatEIJNdlk7S5ydUKU04icjETzG5JapvFwRUp8Wx1dnfSYTHbGrDOj5vRfbsB5CJc F38Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=HOuaorGB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gg17-20020a170906e29100b008ceead154e9si1122787ejb.942.2023.03.01.21.54.18; Wed, 01 Mar 2023 21:54:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=HOuaorGB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230166AbjCBFwx (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230003AbjCBFwT (ORCPT ); Thu, 2 Mar 2023 00:52:19 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25EA351F9E; Wed, 1 Mar 2023 21:51:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736283; x=1709272283; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YTgEgmA3f1uzY8PacyZ6XmpZcGIgDW5/dB0vDrivilc=; b=HOuaorGBemCaZyBXmXxjQ3em0xKDFzaWI+0p/xIwjLYNrEyXINVbyvd/ V2k0p2wWGDZ909PSei7r4WXqq5jbtyCz3MDF+BxALl4p36ltvJ9/+iu0V 222gcU1HdYCOGedxtzc9L4AHP/c6Z+vEbRMXMg9dY2llo1hTI3cFLgTiM lnC8Ijk/rlC1fqD+z6j/zNgrO92pabtw6ZoHzdn+wpKm5oUhTB2Z0YGVT dyO20vr4uZQnB0sHpNUnezsUs1kbsFH+nuR+aPzCYlPj7ba4X+U416u/W 0aAdRHGolS0+xHULy4k9NyEuUjQUJGILmIyBhJLBYOF3007R7YDKZ/awP g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887268" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887268" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530958" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530958" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:50 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 26/34] x86/fred: no ESPFIX needed when FRED is enabled Date: Wed, 1 Mar 2023 21:25:03 -0800 Message-Id: <20230302052511.1918-27-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234210533899596?= X-GMAIL-MSGID: =?utf-8?q?1759234210533899596?= From: "H. Peter Anvin (Intel)" Because FRED always restores the full value of %rsp, ESPFIX is no longer needed when it's enabled. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/espfix_64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/kernel/espfix_64.c b/arch/x86/kernel/espfix_64.c index 16f9814c9be0..48d133a54f45 100644 --- a/arch/x86/kernel/espfix_64.c +++ b/arch/x86/kernel/espfix_64.c @@ -106,6 +106,10 @@ void __init init_espfix_bsp(void) pgd_t *pgd; p4d_t *p4d; + /* FRED systems don't need ESPFIX */ + if (cpu_feature_enabled(X86_FEATURE_FRED)) + return; + /* Install the espfix pud into the kernel page directory */ pgd = &init_top_pgt[pgd_index(ESPFIX_BASE_ADDR)]; p4d = p4d_alloc(&init_mm, pgd, ESPFIX_BASE_ADDR); @@ -129,6 +133,10 @@ void init_espfix_ap(int cpu) void *stack_page; pteval_t ptemask; + /* FRED systems don't need ESPFIX */ + if (cpu_feature_enabled(X86_FEATURE_FRED)) + return; + /* We only have to do this once... */ if (likely(per_cpu(espfix_stack, cpu))) return; /* Already initialized */ From patchwork Thu Mar 2 05:25:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63236 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4064402wrd; Wed, 1 Mar 2023 21:56:41 -0800 (PST) X-Google-Smtp-Source: AK7set+YIEzlWUeYOz7CRx07Yr4S0ohBMFlR3elMCIOTwtIslICz26KV0GVyQPOVfo31OIEpJ7Q5 X-Received: by 2002:a17:90b:1d0e:b0:237:9858:ebbf with SMTP id on14-20020a17090b1d0e00b002379858ebbfmr10431061pjb.30.1677736601367; Wed, 01 Mar 2023 21:56:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736601; cv=none; d=google.com; s=arc-20160816; b=Yc4oHDcLftWr1egXkCcLsb5e5QzPrA6aGzqVfWNif94lNNaqf5X1yad6ZRStNX5kTE lP6/xTM0vaEA+TmdpTSHU5HDE9sCA7HSDle6UZHqNJIYSRNkMS1SRVZdhLBNhMjoR1nY 7DHBrCjayxwvLFEi5IFJJcSZL5tiJtpq5dcnAg2GSjv61kaDq8S0iFyrbOsZ4sORqO3A /OqCsiPYPIgMXDQHZlNihdHBwe11OKKpO+82A2K5QAfZl2nSwY9rCgG6own9juHq/eHy B9AU/IZJphS6EoodHqL8ajeOe4ur5vLpzAInCHIUviXlzYXV+lmjZ8ukkiFGCRj+zliH gXkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=evUt1h51br55zOpbl7ekH6vYbwwJKnK8ENE5d3fdDfI=; b=bn4FX8wfEkWBxQSwskTiFkhe4UbaPudurNsPjbXER5zCAq3g/BViTV3kmVJGXm6vvf jf15+aPrX6RiMBRCRN7VISzEsG3t9cYs7ga8E0pgv+3r75XaactokyvCk+OVEEZOMuHL 6BM3dKYP6Z49pQilw38/2NXv2fgaNTYCuLc73ienE36cuxwYvDTdj7whzH9Xl+CsPOzN BlNk8NHKDDjV6O87tgZnPzixsD4cvLCELnZiUBxbV6qBElDP43WWv+troutSDc1NCiz0 RFpHS0mS1Fm+OZUaDsjSC/ZuoZUmdp7kCG+bephfAx4TmLjMAzmyCWPsjUSCl9UH6shc 7y+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="Pd/0ZDSL"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x3-20020a17090a9dc300b00233f147ef63si1522150pjv.40.2023.03.01.21.56.27; Wed, 01 Mar 2023 21:56:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="Pd/0ZDSL"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230114AbjCBFw4 (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230104AbjCBFwX (ORCPT ); Thu, 2 Mar 2023 00:52:23 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 497CD55047; Wed, 1 Mar 2023 21:51:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736287; x=1709272287; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pLas5p/5GAmOvBK0uD9R5N8t9jJL8ZoKvTscvrwkS8w=; b=Pd/0ZDSL1fPqBYZRIPo1FATEKZYxgGtgIK/oipGpz/CSMDqufEqh580J VP3XMqHjC8/9nZodWifOuRgoBd+v8wExgOQ3m45MgCM4+c26ueHTQEgjw KIb4BBx/hxmsI2RA5Mjj2Ru4Z2iq26v9ysr73QC4XOyBYlZwwoEwnNZg+ Ajd//Ooug4UxKQSrGyj96Nu2SdBc/r5+8vjMBVaD+RXSgyhUZKH8eQEBy 51Kpf9fusviOOdUdXkb8IySK2ePyoe/J/+OoQi5CaPEE1+BtbWfjXH+jb yt3JZgo0Dle+3UY2kBS7kQAYibxxjTNhf/orKFRAuqrJFUTGb/pzaL+2M A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887292" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887292" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530960" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530960" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:50 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 27/34] x86/fred: allow single-step trap and NMI when starting a new thread Date: Wed, 1 Mar 2023 21:25:04 -0800 Message-Id: <20230302052511.1918-28-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234334578984868?= X-GMAIL-MSGID: =?utf-8?q?1759234334578984868?= From: "H. Peter Anvin (Intel)" Allow single-step trap and NMI when starting a new thread, thus once the new thread returns to ring3, single-step trap and NMI are both enabled immediately. High-order 48 bits above the lowest 16 bit CS are discarded by the legacy IRET instruction, thus can be set unconditionally, even when FRED is not enabled. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/fred.h | 11 +++++++++++ arch/x86/kernel/process_64.c | 13 +++++++------ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index cd974edc8e8a..12449448e9bf 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -52,6 +52,14 @@ #define FRED_CSL_ALLOW_SINGLE_STEP _BITUL(25) #define FRED_CSL_INTERRUPT_SHADOW _BITUL(24) +/* + * High-order 48 bits above the lowest 16 bit CS are discarded by the + * legacy IRET instruction, thus can be set unconditionally, even when + * FRED is not enabled. + */ +#define CSL_PROCESS_START \ + (FRED_CSL_ENABLE_NMI | FRED_CSL_ALLOW_SINGLE_STEP) + #ifndef __ASSEMBLY__ #include @@ -115,6 +123,9 @@ void fred_setup_apic(void); #else #define cpu_init_fred_exceptions() BUG() #define fred_setup_apic() BUG() + +#define CSL_PROCESS_START 0 + #endif /* CONFIG_X86_FRED */ #endif /* ASM_X86_FRED_H */ diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index ff6594dbea4a..b23850352e7d 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -55,6 +55,7 @@ #include #include #include +#include #ifdef CONFIG_IA32_EMULATION /* Not included via unistd.h */ #include @@ -506,7 +507,7 @@ void x86_gsbase_write_task(struct task_struct *task, unsigned long gsbase) static void start_thread_common(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp, - unsigned int _cs, unsigned int _ss, unsigned int _ds) + u16 _cs, u16 _ss, u16 _ds) { WARN_ON_ONCE(regs != current_pt_regs()); @@ -521,11 +522,11 @@ start_thread_common(struct pt_regs *regs, unsigned long new_ip, loadsegment(ds, _ds); load_gs_index(0); - regs->ip = new_ip; - regs->sp = new_sp; - regs->cs = _cs; - regs->ss = _ss; - regs->flags = X86_EFLAGS_IF; + regs->ip = new_ip; + regs->sp = new_sp; + regs->csx = _cs | CSL_PROCESS_START; + regs->ssx = _ss; + regs->flags = X86_EFLAGS_IF | X86_EFLAGS_FIXED; } void From patchwork Thu Mar 2 05:25:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63229 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4063653wrd; Wed, 1 Mar 2023 21:53:46 -0800 (PST) X-Google-Smtp-Source: AK7set+/15kjnQlgiZyM6WOWJ82I2MH4qqw7O7wdJZ9h4hA4T7CH32WPDHFKpdJpA4i8HLmgC0mm X-Received: by 2002:aa7:d754:0:b0:4af:740d:fde with SMTP id a20-20020aa7d754000000b004af740d0fdemr809133eds.20.1677736426177; Wed, 01 Mar 2023 21:53:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677736426; cv=none; d=google.com; s=arc-20160816; b=wYcQ3LaulET230w2koGbyY5K8DhDNJ/sBfytLb0pa3/VPANCj0LH1XuZxKfoQPB/VX FlAKquMFaEdfuNLT+KWPSv6TfPCBMUFIvqJKg/WeNzD1PA0AF4RWYFDUvsjIDGz49sNe hAyV/QFO1Pf7pLmKVWkqkupCs/GpJMRknDvNul8qSZrHdNR5glOzbY7XZdO9AkpwO9vl pgKrwbQ3UT98yTHKspNpSKeazNvUq3wiiAJo3KY4ktT4hiUWZtu2oWb0prOfBGE9omlo gFnG3qrF3v3CfGzvhiPovxV8ncXFF5XoELVtCtQqJfkoJoQ8y3JajYymS1AYsMFZqAh7 f5+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+yaNDyjHciRyCSV2CarXljfkk6fSKjRAy2iTkNBrIO4=; b=aSuCBFoVmxihFwTCsQBYwO2trQPpybRPPu3Dv4d/9HIf0IGdAHuSjZI2Vj5Z6r9gS8 SfEnfYJj2CQ7kOjxGSDp53rE7zTYirz+q0hwhW64B9Bt8lBCJc4knhzAXDrGATNVKDjl vTLBXV0Xou7Mu3VF/BVLMsSveaTCqrP54diVBeXyZ2e1vIsd3q2VespHcfbvfR+wxoZi 32sOkAdHNDU9FgUjn0P47vPuYqXqb+TH58anOyjBd1K/kNzUVsmyqWafogN4DrUvSPo7 B43CjFuL8NmO7MW89Qj/BXBjdm35x9prBX72WrcEd+fxbXYXCsUnBlLIjZ3reCuHRNQf XW5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ljkPnil6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e9-20020a056402148900b004ad0232da1dsi4322519edv.31.2023.03.01.21.53.22; Wed, 01 Mar 2023 21:53:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ljkPnil6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230130AbjCBFwa (ORCPT + 99 others); Thu, 2 Mar 2023 00:52:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230031AbjCBFvw (ORCPT ); Thu, 2 Mar 2023 00:51:52 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F08A44ECC2; Wed, 1 Mar 2023 21:51:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736270; x=1709272270; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iXYrw/l8XuMvDJL0/urb7Y4MFn+tao/ntyyueUqHbW8=; b=ljkPnil6ch+/bbAJAhhLnVDhbeSvxM/faUIohObkRqCzVakrj4jSGgMq Pg2qj+iTX/gvHRnMThEFg3GX/VLNAZftpQKjYVSP6kxdOVOsNa+93aCoZ FVbN8s7RX/CHBwpLP/SO25Nh/oLjuo8cvfG2otVzNDW74SXIP9vm3enRc mDx2IwaRhoPMmRJFlM1lLquZICjtfAE5r1aX1X1vksOmm+LmBOk4g+frm FNiKt2KAltYPRNVeKwzWa8JoQ63KkKH+VR5Uka7q6qifR3rKtJn0z9/yi qQ3S9oMrEwj6L9ZU1YyBLlVxjhIoUFexRj7PxnbfoJa6mS+BufXYx8gLx Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887258" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887258" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530965" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530965" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:51 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 28/34] x86/fred: fixup fault on ERETU by jumping to fred_entrypoint_user Date: Wed, 1 Mar 2023 21:25:05 -0800 Message-Id: <20230302052511.1918-29-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234150826053886?= X-GMAIL-MSGID: =?utf-8?q?1759234150826053886?= If the stack frame contains an invalid user context (e.g. due to invalid SS, a non-canonical RIP, etc.) the ERETU instruction will trap (#SS or #GP). From a Linux point of view, this really should be considered a user space failure, so use the standard fault fixup mechanism to intercept the fault, fix up the exception frame, and redirect execution to fred_entrypoint_user. The end result is that it appears just as if the hardware had taken the exception immediately after completing the transition to user space. Suggested-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/entry/entry_64_fred.S | 8 +++++-- arch/x86/include/asm/extable_fixup_types.h | 4 +++- arch/x86/mm/extable.c | 28 ++++++++++++++++++++++ 3 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/x86/entry/entry_64_fred.S b/arch/x86/entry/entry_64_fred.S index 1fb765fd3871..027ef8f1e600 100644 --- a/arch/x86/entry/entry_64_fred.S +++ b/arch/x86/entry/entry_64_fred.S @@ -5,8 +5,10 @@ * The actual FRED entry points. */ #include -#include +#include #include +#include +#include #include #include "calling.h" @@ -38,7 +40,9 @@ SYM_CODE_START_NOALIGN(fred_entrypoint_user) call fred_entry_from_user SYM_INNER_LABEL(fred_exit_user, SYM_L_GLOBAL) FRED_EXIT - ERETU +1: ERETU + + _ASM_EXTABLE_TYPE(1b, fred_entrypoint_user, EX_TYPE_ERETU) SYM_CODE_END(fred_entrypoint_user) /* diff --git a/arch/x86/include/asm/extable_fixup_types.h b/arch/x86/include/asm/extable_fixup_types.h index 991e31cfde94..1585c798a02f 100644 --- a/arch/x86/include/asm/extable_fixup_types.h +++ b/arch/x86/include/asm/extable_fixup_types.h @@ -64,6 +64,8 @@ #define EX_TYPE_UCOPY_LEN4 (EX_TYPE_UCOPY_LEN | EX_DATA_IMM(4)) #define EX_TYPE_UCOPY_LEN8 (EX_TYPE_UCOPY_LEN | EX_DATA_IMM(8)) -#define EX_TYPE_ZEROPAD 20 /* longword load with zeropad on fault */ +#define EX_TYPE_ZEROPAD 20 /* longword load with zeropad on fault */ + +#define EX_TYPE_ERETU 21 #endif diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index 60814e110a54..88a2c419ce8b 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -195,6 +196,29 @@ static bool ex_handler_ucopy_len(const struct exception_table_entry *fixup, return ex_handler_uaccess(fixup, regs, trapnr); } +#ifdef CONFIG_X86_FRED +static bool ex_handler_eretu(const struct exception_table_entry *fixup, + struct pt_regs *regs, unsigned long error_code) +{ + struct pt_regs *uregs = (struct pt_regs *)(regs->sp - offsetof(struct pt_regs, ip)); + unsigned short ss = uregs->ss; + unsigned short cs = uregs->cs; + + fred_info(uregs)->edata = fred_event_data(regs); + uregs->ssx = regs->ssx; + uregs->ss = ss; + uregs->csx = regs->csx; + uregs->current_stack_level = 0; + uregs->cs = cs; + + /* Copy error code to uregs and adjust stack pointer accordingly */ + uregs->orig_ax = error_code; + regs->sp -= 8; + + return ex_handler_default(fixup, regs); +} +#endif + int ex_get_fixup_type(unsigned long ip) { const struct exception_table_entry *e = search_exception_tables(ip); @@ -272,6 +296,10 @@ int fixup_exception(struct pt_regs *regs, int trapnr, unsigned long error_code, return ex_handler_ucopy_len(e, regs, trapnr, reg, imm); case EX_TYPE_ZEROPAD: return ex_handler_zeropad(e, regs, fault_addr); +#ifdef CONFIG_X86_FRED + case EX_TYPE_ERETU: + return ex_handler_eretu(e, regs, error_code); +#endif } BUG(); } From patchwork Thu Mar 2 05:25:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63243 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4070364wrd; Wed, 1 Mar 2023 22:12:57 -0800 (PST) X-Google-Smtp-Source: AK7set+4wiHIudYgjBEAQIh05zQvE4U1BTupWvvZ00Pb+7O7+dueymMymo1M6nWnuLVfRP4bdjZc X-Received: by 2002:a05:6a20:3d91:b0:cd:3f04:6452 with SMTP id s17-20020a056a203d9100b000cd3f046452mr11541016pzi.49.1677737576994; Wed, 01 Mar 2023 22:12:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677737576; cv=none; d=google.com; s=arc-20160816; b=HVFOVrK+OXv5l/gVPMwr62oc/M/CoURZ7gVTe5HgRA875IEMOU26EO7x5GTY7t+IEn 19vXUXgY8inKs4ZEDVASY9mRcaxOOWXTvxqGykVjLV4Z7U4PGLMPwsECBikpBEL400Bx 33QR6NqeRS3FN9x1aYgPDRsV4RG2AQ600reh25SRMtTDarV27npdbMS3137ioq/AfTOs XaSfZDvgJhpEPUkGjFTq2W/CzhE5zqpANauxjrcHMEvjrJ9kOK0+vNnDufnBKVkmgrCP G/N765pBP65rUyQ2Na5hSNMaT8ohO9sv23cP50sul1P8xTtMQfvoBdPVh+usu8L3kr7E fMYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6ryoaO52SQacc1V2FLptfa9uuyFKNPljQyyaT3VTYMw=; b=Hs5MvgAGMV354K13+qXGyQwGDUtw8Q3VERme+EJeNGUFc59wk5OkixT2CO+GS7t5O8 bQ+XE19r5dcdMXEaMZIr+aUeXLzQfj6eHOBxhkn7F+0Mkarb/kBnKtxJTUqYAssQD4QP 165HMyMTlms7GQiuRb6N6ienmrN2X3gqVZ1R0oSozeTCXUwiP8icKhV2FAQ76r7JWGmu FhnPPQuOXNLBI3urIpStt0Z1ULL9xA4bUYpaQZ32k7yxC6eSw5IK4uibs7L1zhW2p291 OaaO2MGKcAdHPTI7ZwK+xibox+ysMozhp1ubJIbP7F5T/WKdvxUgbW6DIRiJ1fGcGarh Mv7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XrxBh89F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 84-20020a630557000000b004dfe1a4ff03si13663811pgf.106.2023.03.01.22.12.43; Wed, 01 Mar 2023 22:12:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XrxBh89F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230176AbjCBFxB (ORCPT + 99 others); Thu, 2 Mar 2023 00:53:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230057AbjCBFwa (ORCPT ); Thu, 2 Mar 2023 00:52:30 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EFC555074; Wed, 1 Mar 2023 21:51:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736292; x=1709272292; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5IBl0XY5xGj0Ul5jZJTZVlHtGnpVju3gJ8HZ07Stwk0=; b=XrxBh89F5efoaqUKFckWHq+4kQ1aFc9XuAfUEvt6r9jAq/0HEHPXwOzt tsAfVpsx1F/raEybyyBIOurjdMojuTbnubI9sFnMNkwMCSxK0aNOQuHV8 yoVsiAzGP1KGq2YBvBqf/GTBG6fT9PXxIUZ+ChhqsArl32ZtdCr3FQm2z bEDA2v4GvdVpUqhXy2Wgm4VbN+DByPhq23xTbNW3YIuAqRWXOkGw5v69x A/MS1xAvBM3jpDmevBQ0L769HZ0ZV6RjrPsymoP8zGnDlT6scS87PwZvC XGgrSjmBoGha0eergh2v+lssqtswVEDPNh5zCLsn4gJi2+g9+CakswHnj A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887297" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887297" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530970" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530970" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:51 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 29/34] x86/ia32: do not modify the DPL bits for a null selector Date: Wed, 1 Mar 2023 21:25:06 -0800 Message-Id: <20230302052511.1918-30-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759235357881153624?= X-GMAIL-MSGID: =?utf-8?q?1759235357881153624?= When a null selector is to be loaded into a segment register, reload_segments() sets its DPL bits to 3. Later when the IRET instruction loads it, it zeros the segment register. The two operations offset each other to actually effect a nop. Unlike IRET, ERETU does not make any of DS, ES, FS, or GS null if it is found to have DPL < 3. It is expected that a FRED-enabled operating system will return to ring 3 (in compatibility mode) only when those segments all have DPL = 3. Thus when FRED is enabled, we end up with having 3 in a segment register even when it is initially set to 0. Fix it by not modifying the DPL bits for a null selector. Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kernel/signal_32.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/signal_32.c b/arch/x86/kernel/signal_32.c index 9027fc088f97..7796cf84fca2 100644 --- a/arch/x86/kernel/signal_32.c +++ b/arch/x86/kernel/signal_32.c @@ -36,22 +36,27 @@ #ifdef CONFIG_IA32_EMULATION #include +static inline u16 usrseg(u16 sel) +{ + return sel <= 3 ? sel : sel | 3; +} + static inline void reload_segments(struct sigcontext_32 *sc) { unsigned int cur; savesegment(gs, cur); - if ((sc->gs | 0x03) != cur) - load_gs_index(sc->gs | 0x03); + if (usrseg(sc->gs) != cur) + load_gs_index(usrseg(sc->gs)); savesegment(fs, cur); - if ((sc->fs | 0x03) != cur) - loadsegment(fs, sc->fs | 0x03); + if (usrseg(sc->fs) != cur) + loadsegment(fs, usrseg(sc->fs)); savesegment(ds, cur); - if ((sc->ds | 0x03) != cur) - loadsegment(ds, sc->ds | 0x03); + if (usrseg(sc->ds) != cur) + loadsegment(ds, usrseg(sc->ds)); savesegment(es, cur); - if ((sc->es | 0x03) != cur) - loadsegment(es, sc->es | 0x03); + if (usrseg(sc->es) != cur) + loadsegment(es, usrseg(sc->es)); } #define sigset32_t compat_sigset_t From patchwork Thu Mar 2 05:25:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63240 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4067797wrd; Wed, 1 Mar 2023 22:06:03 -0800 (PST) X-Google-Smtp-Source: AK7set9YboBvPze12QvHMgYRnkOJP0DGF/7a6prWxLFvdaQFgyfoWjQH4pBcoT9Yfc3xjAr8iQZX X-Received: by 2002:a05:6a20:938c:b0:cc:85ff:1810 with SMTP id x12-20020a056a20938c00b000cc85ff1810mr10647089pzh.60.1677737163614; Wed, 01 Mar 2023 22:06:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677737163; cv=none; d=google.com; s=arc-20160816; b=O+V3iWzo4QwsA1mHaM7ghhTHB5caebx8MEj8kKymxtyAGr4LRUJy6AZXWjzJvWA7gr X2lEIhRGQOEqtRs5YsgFYzy0NIwN9r15tlDu9msoC6cZ7sHnGPddvhpLoDqNj2ZtjHPE lOGyxVA/p3gWMwIc4KedGddx1F7zU2Vg0k5IuXEQe0hkF0pPJZRZJnP7am7vLV7O8NU4 4vL4TDVA+O834IR368Sv7w3qYani80ffgGBUKswm5lUHQLQ85w+hSOiU7J+eU/4oKcY8 p0oo3JCeOwcwg+/eS04VWpj7E8Fn02a557gTisnnAqo5N2kG+FeTTl24Dk8385vIlVJo hpqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2vzRnTD/nydo1nEapLXA2WTadvHuQY1PFpg25Irc/wM=; b=aKS5XGjtUVnjeFI16aMjtYpvHtAt8BQ3BAWekId8NK9d33eYnf3wupt00XurD6pL+Y N+4otOqwcCU83qc3qGTTtTbPvX445wSR8P8uRrY10SXnYDfUdhBOranw+/oSEd7ZetUd NYXV3R7QFt2X3UbmjTK7XrRVeBbV2KRlZdlm7zjEWSx0G6aqvARvN8X6e9k3wYTXL6R9 cgukJXxkIVC0NTwusPYF3w4I0UiSE220Tq4k/BfZxXZD6Y5+cAtZUwMTnEASvII6oNvG S1yRIa+vFmlsLUFycIUbBmZGWaU9Yj+WADIWDXse+snI9VyLC8F+JY9+j5Jp4eIAYEzu 9OlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=D7G5HRbw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w123-20020a623081000000b00576fca27d92si12798550pfw.206.2023.03.01.22.05.50; Wed, 01 Mar 2023 22:06:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=D7G5HRbw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230188AbjCBFxI (ORCPT + 99 others); Thu, 2 Mar 2023 00:53:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230061AbjCBFwe (ORCPT ); Thu, 2 Mar 2023 00:52:34 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 659E841B69; Wed, 1 Mar 2023 21:51:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736294; x=1709272294; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ld6f/xX7p2ZEo7XaTPWc1rWGQxKM5Erhz0oCVevDNM4=; b=D7G5HRbwD9HN1L4uaD50VFod2XYq8kiffqUSM/ov2jUUxm0KKDsmhOeE 7Bsv/or3lzAXUswRyNAnW/CV9pjMr8wA0klJx5Wuylac5ssqBMZiH5jOl mMD5ooChGgJKu6Uy8EgOFk9JPP5XMfacDRJf1Fy9PTu0a9W0znZUpfipK InrLu0HKUyHnImClVDLNhiQjinQOLqDEVMbIu9Ynf/BGgzRvJlsI6I/kZ lNXvWEhwRJJAaKIn2TgLr/ZgJ8Dh0tvro6ymZWgQTdnljYIn/4w2gvTQt fy3LcpvpM/1n4eYRHdmFjAhlPY9YcC+ewuDZWZ/glwbpfnD6LSjjnH5I7 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887312" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887312" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530973" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530973" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:51 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 30/34] x86/fred: allow FRED systems to use interrupt vectors 0x10-0x1f Date: Wed, 1 Mar 2023 21:25:07 -0800 Message-Id: <20230302052511.1918-31-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234923940404237?= X-GMAIL-MSGID: =?utf-8?q?1759234923940404237?= From: "H. Peter Anvin (Intel)" FRED inherits the Intel VT-x enhancement of classified events with a two-level event dispatch logic. The first-level dispatch is on the event type, and the second-level is on the event vector. This also means that vectors in different event types are orthogonal, thus, vectors 0x10-0x1f become available as hardware interrupts. Enable interrupt vectors 0x10-0x1f on FRED systems (interrupt 0x80 is already enabled.) Most of these changes are about removing the assumption that the lowest-priority vector is hard-wired to 0x20. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/idtentry.h | 4 ++-- arch/x86/include/asm/irq.h | 5 +++++ arch/x86/include/asm/irq_vectors.h | 15 +++++++++++---- arch/x86/kernel/apic/apic.c | 11 ++++++++--- arch/x86/kernel/apic/vector.c | 8 +++++++- arch/x86/kernel/fred.c | 4 ++-- arch/x86/kernel/idt.c | 6 +++--- arch/x86/kernel/irq.c | 2 +- arch/x86/kernel/traps.c | 2 ++ 9 files changed, 41 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentry.h index bd43866f9c3e..57c891148b59 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -546,8 +546,8 @@ __visible noinstr void func(struct pt_regs *regs, \ */ .align IDT_ALIGN SYM_CODE_START(irq_entries_start) - vector=FIRST_EXTERNAL_VECTOR - .rept NR_EXTERNAL_VECTORS + vector=FIRST_EXTERNAL_VECTOR_IDT + .rept FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR_IDT UNWIND_HINT_IRET_REGS 0 : ENDBR diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 768aa234cbb4..e4be6f8409ad 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -11,6 +11,11 @@ #include #include +/* + * The first available IRQ vector + */ +extern unsigned int __ro_after_init first_external_vector; + /* * The irq entry code is in the noinstr section and the start/end of * __irqentry_text is emitted via labels. Make the build fail if diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h index 43dcb9284208..cb3670a7c18f 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h @@ -31,15 +31,23 @@ /* * IDT vectors usable for external interrupt sources start at 0x20. - * (0x80 is the syscall vector, 0x30-0x3f are for ISA) + * (0x80 is the syscall vector, 0x30-0x3f are for ISA). + * + * With FRED we can also use 0x10-0x1f even though those overlap + * exception vectors as FRED distinguishes exceptions and interrupts. + * Therefore, FIRST_EXTERNAL_VECTOR is no longer a constant. */ -#define FIRST_EXTERNAL_VECTOR 0x20 +#define FIRST_EXTERNAL_VECTOR_IDT 0x20 +#define FIRST_EXTERNAL_VECTOR_FRED 0x10 +#define FIRST_EXTERNAL_VECTOR first_external_vector /* * Reserve the lowest usable vector (and hence lowest priority) 0x20 for * triggering cleanup after irq migration. 0x21-0x2f will still be used * for device interrupts. */ +#define IRQ_MOVE_CLEANUP_VECTOR_IDT FIRST_EXTERNAL_VECTOR_IDT +#define IRQ_MOVE_CLEANUP_VECTOR_FRED FIRST_EXTERNAL_VECTOR_FRED #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR #define IA32_SYSCALL_VECTOR 0x80 @@ -48,7 +56,7 @@ * Vectors 0x30-0x3f are used for ISA interrupts. * round up to the next 16-vector boundary */ -#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq) +#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR_IDT + 16) & ~15) + irq) /* * Special IRQ vectors used by the SMP architecture, 0xf0-0xff @@ -114,7 +122,6 @@ #define FIRST_SYSTEM_VECTOR NR_VECTORS #endif -#define NR_EXTERNAL_VECTORS (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) #define NR_SYSTEM_VECTORS (NR_VECTORS - FIRST_SYSTEM_VECTOR) /* diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 20d9a604da7c..eef67f64aa81 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1621,12 +1621,17 @@ static void setup_local_APIC(void) /* * Set Task Priority to 'accept all except vectors 0-31'. An APIC * vector in the 16-31 range could be delivered if TPR == 0, but we - * would think it's an exception and terrible things will happen. We - * never change this later on. + * would think it's an exception and terrible things will happen, + * unless we are using FRED in which case interrupts and + * exceptions are distinguished by type code. + * + * We never change this later on. */ + BUG_ON(!first_external_vector); + value = apic_read(APIC_TASKPRI); value &= ~APIC_TPRI_MASK; - value |= 0x10; + value |= (first_external_vector - 0x10) & APIC_TPRI_MASK; apic_write(APIC_TASKPRI, value); /* Clear eventually stale ISR/IRR bits */ diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index c1efebd27e6c..f4325445fd78 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -46,6 +46,7 @@ static struct irq_matrix *vector_matrix; #ifdef CONFIG_SMP static DEFINE_PER_CPU(struct hlist_head, cleanup_list); #endif +unsigned int first_external_vector = FIRST_EXTERNAL_VECTOR_IDT; void lock_vector_lock(void) { @@ -796,7 +797,12 @@ int __init arch_early_irq_init(void) * Allocate the vector matrix allocator data structure and limit the * search area. */ - vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, + if (cpu_feature_enabled(X86_FEATURE_FRED)) + first_external_vector = FIRST_EXTERNAL_VECTOR_FRED; + else + first_external_vector = FIRST_EXTERNAL_VECTOR_IDT; + + vector_matrix = irq_alloc_matrix(NR_VECTORS, first_external_vector, FIRST_SYSTEM_VECTOR); BUG_ON(!vector_matrix); diff --git a/arch/x86/kernel/fred.c b/arch/x86/kernel/fred.c index 827b58fd98d4..04f057219c6e 100644 --- a/arch/x86/kernel/fred.c +++ b/arch/x86/kernel/fred.c @@ -51,7 +51,7 @@ void __init fred_setup_apic(void) { int i; - for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) + for (i = 0; i < FIRST_EXTERNAL_VECTOR_FRED; i++) set_bit(i, system_vectors); /* @@ -60,7 +60,7 @@ void __init fred_setup_apic(void) * /proc/interrupts. */ #ifdef CONFIG_SMP - set_bit(IRQ_MOVE_CLEANUP_VECTOR, system_vectors); + set_bit(IRQ_MOVE_CLEANUP_VECTOR_FRED, system_vectors); #endif for (i = 0; i < NR_SYSTEM_VECTORS; i++) { diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index a58c6bc1cd68..d3fd86f85de9 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -131,7 +131,7 @@ static const __initconst struct idt_data apic_idts[] = { INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi), INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function), INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single), - INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup), + INTG(IRQ_MOVE_CLEANUP_VECTOR_IDT, asm_sysvec_irq_move_cleanup), INTG(REBOOT_VECTOR, asm_sysvec_reboot), #endif @@ -274,13 +274,13 @@ static void __init idt_map_in_cea(void) */ void __init idt_setup_apic_and_irq_gates(void) { - int i = FIRST_EXTERNAL_VECTOR; + int i = FIRST_EXTERNAL_VECTOR_IDT; void *entry; idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true); for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) { - entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR); + entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR_IDT); set_intr_gate(i, entry); } diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 7e125fff45ab..b7511e02959c 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -359,7 +359,7 @@ void fixup_irqs(void) * vector_lock because the cpu is already marked !online, so * nothing else will touch it. */ - for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { + for (vector = first_external_vector; vector < NR_VECTORS; vector++) { if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector]))) continue; diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index c7253b4901f0..c46eba091728 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1544,6 +1544,8 @@ DEFINE_IDTENTRY_IRQ(spurious_interrupt) pr_info("Spurious interrupt (vector 0x%x) on CPU#%d, should never happen.\n", vector, smp_processor_id()); } + +unsigned int first_external_vector = FIRST_EXTERNAL_VECTOR_IDT; #endif /* From patchwork Thu Mar 2 05:25:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63239 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4067776wrd; Wed, 1 Mar 2023 22:06:02 -0800 (PST) X-Google-Smtp-Source: AK7set9HEvINSsU2hipwzi4wrDJOPe+CmKaK1TuQm+0r5FYdYJJxb6G953T2ssT039yJWqSx226u X-Received: by 2002:a62:5e05:0:b0:5e8:6839:1f13 with SMTP id s5-20020a625e05000000b005e868391f13mr8023535pfb.10.1677737161727; Wed, 01 Mar 2023 22:06:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677737161; cv=none; d=google.com; s=arc-20160816; b=pZSt6/6WIY+klolEUt9zvtMrS0s5k9m8IdPLYkPxWxGNwp1XKn64o345Yt2n8xNc2I VG4TM4XwR9CIg1rWWSg4mAvd/dmAA7orlK3TXDamzw5iNGrEaS08EkpVYTezSi6c2WBz LvN/NRBhrwrVvTcKKpyTen0Bz1rMrl8CAyjCVzDhsW8qkPAS2ESQdDZdO1rDsmgIXTFN oGXKZFGNtrwg4UiPjLj8Ddo16KnHHf1jsBlRW/zjw5XgPUH+195u9MQfgPd5zts3yoMa SmvMvBLU5UHH/Z7eB8/1Ty6iAWKUk2LRyD/gnuypJqn5BiZgw8RWExgD9ZSJe0ShHFvv kfzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lR12Ii/1HJ0KqlHsbilDN4OUueFy6zTaiQX+lSvNuzQ=; b=iB0kLu6JcEMF3accdYETsVlpwWlRI0I+JJVhINcMCthJQP9tMUD2hBedQX67b+8+KI 4AEnGUkfIf4xmgRPCrmS9KCS/0XunwSs54Tpr8p3yiHzi9svEns6QoQNJVUqRK34qkiO 9yCNZE5VPwgO1ZB4oFJQbYreXhucY4Fl6HmOdI5xMzum1r/v5zgqf9Dn7eNeY1qv3XK+ dluvYlKuc4V9LzStshSbOsAmRJSjivBV79LBvOVnEL4HueCm7cZ915SkReaxqb4hGcRI XCQlIhTujKgqwGHSxgmfIr2lpdkVTueDBCaufDAgeubCO8fPCt6i6NsOtU1Km/fFbPcW 8Ixg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Qj3sL9En; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j191-20020a638bc8000000b005031ab2ff9csi14848042pge.430.2023.03.01.22.05.49; Wed, 01 Mar 2023 22:06:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Qj3sL9En; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230239AbjCBFxZ (ORCPT + 99 others); Thu, 2 Mar 2023 00:53:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230093AbjCBFwu (ORCPT ); Thu, 2 Mar 2023 00:52:50 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40FE54ECCF; Wed, 1 Mar 2023 21:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736303; x=1709272303; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=drfdD72JCLwJTt7+cCB8NZK4k9Ahl+N6L18C1+Wvw8g=; b=Qj3sL9EngmGSQ9M5/NiZ4s5IsUiGdOMLa/D0AeebXWzpcz/HJiIkPj0r 6i9CFxCdv6IjYRL8l0PTTvR40W+btQREN0t57mHP2Iy1ZEXLuOv69DKG7 vR+RiUUzIwtB9lKIkr2lsyn3+NN5sbWKwNgTLBsB2YvyjCHF0OQQT3J91 q4/I+4FKtTSxFWt9onoOxwJ/GjMFnF9XXnrnJj+kXAt7lmHTuONlQXvab ASoJ8bu/aSNGYakm9g933m1VIlF4eL2aS+48inv0Ii0JaM3JMQwpKuASQ +R2iiQetsK1gK1YuMjUnl+QpqV/Id72hjSveQCpElM+IBrvfOLvC+d2ZM A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887326" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887326" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530976" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530976" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:51 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 31/34] x86/fred: allow dynamic stack frame size Date: Wed, 1 Mar 2023 21:25:08 -0800 Message-Id: <20230302052511.1918-32-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234921759727635?= X-GMAIL-MSGID: =?utf-8?q?1759234921759727635?= A FRED stack frame could contain different amount of information for different event types, or perhaps even for different instances of the same event type. Thus we need to eliminate the need of any advance information of the stack frame size to allow dynamic stack frame size. Implement it through: 1) add a new field user_pt_regs to thread_info, and initialize it with a pointer to a virtual pt_regs structure at the top of a thread stack. 2) save a pointer to the user-space pt_regs structure created by fred_entrypoint_user() to user_pt_regs in fred_entry_from_user(). 3) initialize the init_thread_info's user_pt_regs with a pointer to a virtual pt_regs structure at the top of init stack. This approach also works for IDT, thus we unify the code. Suggested-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/entry/entry_32.S | 2 +- arch/x86/entry/entry_fred.c | 2 ++ arch/x86/include/asm/entry-common.h | 3 +++ arch/x86/include/asm/processor.h | 12 +++------ arch/x86/include/asm/switch_to.h | 3 +-- arch/x86/include/asm/thread_info.h | 41 ++++------------------------- arch/x86/kernel/head_32.S | 3 +-- arch/x86/kernel/process.c | 5 ++++ kernel/fork.c | 6 +++++ 9 files changed, 27 insertions(+), 50 deletions(-) diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S index 91397f58ac30..5adc4cf33d92 100644 --- a/arch/x86/entry/entry_32.S +++ b/arch/x86/entry/entry_32.S @@ -1244,7 +1244,7 @@ SYM_CODE_START(rewind_stack_and_make_dead) xorl %ebp, %ebp movl PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %esi - leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp + leal -PTREGS_SIZE(%esi), %esp call make_task_dead 1: jmp 1b diff --git a/arch/x86/entry/entry_fred.c b/arch/x86/entry/entry_fred.c index 8d3e144670d6..a72167c83923 100644 --- a/arch/x86/entry/entry_fred.c +++ b/arch/x86/entry/entry_fred.c @@ -178,6 +178,8 @@ __visible noinstr void fred_entry_from_user(struct pt_regs *regs) [EVENT_TYPE_OTHER] = fred_syscall_slow }; + current->thread_info.user_pt_regs = regs; + /* * FRED employs a two-level event dispatch mechanism, with * the first-level on the type of an event and the second-level diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/entry-common.h index 117903881fe4..5b7d0f47f188 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -12,6 +12,9 @@ /* Check that the stack and regs on entry from user mode are sane. */ static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) { + if (!cpu_feature_enabled(X86_FEATURE_FRED)) + current->thread_info.user_pt_regs = regs; + if (IS_ENABLED(CONFIG_DEBUG_ENTRY)) { /* * Make sure that the entry code gave us a sensible EFLAGS diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 8d73004e4cac..4a50d2a2c14b 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -626,17 +626,11 @@ static inline void spin_lock_prefetch(const void *x) prefetchw(x); } -#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ - TOP_OF_KERNEL_STACK_PADDING) +#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack)) -#define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1)) +#define task_top_of_stack(task) ((unsigned long)task_stack_page(task) + THREAD_SIZE) -#define task_pt_regs(task) \ -({ \ - unsigned long __ptr = (unsigned long)task_stack_page(task); \ - __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ - ((struct pt_regs *)__ptr) - 1; \ -}) +#define task_pt_regs(task) ((task)->thread_info.user_pt_regs) #ifdef CONFIG_X86_32 #define INIT_THREAD { \ diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h index 00fd85abc1d2..0a31da150808 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -72,8 +72,7 @@ static inline void update_task_stack(struct task_struct *task) /* * Will use WRMSRNS/WRMSRLIST for performance once it's upstreamed. */ - wrmsrl(MSR_IA32_FRED_RSP0, - task_top_of_stack(task) + TOP_OF_KERNEL_STACK_PADDING); + wrmsrl(MSR_IA32_FRED_RSP0, task_top_of_stack(task)); } else if (cpu_feature_enabled(X86_FEATURE_XENPV)) { /* Xen PV enters the kernel on the thread stack. */ load_sp0(task_top_of_stack(task)); diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h index 998483078d5f..ced0a01e0a3e 100644 --- a/arch/x86/include/asm/thread_info.h +++ b/arch/x86/include/asm/thread_info.h @@ -13,42 +13,6 @@ #include #include -/* - * TOP_OF_KERNEL_STACK_PADDING is a number of unused bytes that we - * reserve at the top of the kernel stack. We do it because of a nasty - * 32-bit corner case. On x86_32, the hardware stack frame is - * variable-length. Except for vm86 mode, struct pt_regs assumes a - * maximum-length frame. If we enter from CPL 0, the top 8 bytes of - * pt_regs don't actually exist. Ordinarily this doesn't matter, but it - * does in at least one case: - * - * If we take an NMI early enough in SYSENTER, then we can end up with - * pt_regs that extends above sp0. On the way out, in the espfix code, - * we can read the saved SS value, but that value will be above sp0. - * Without this offset, that can result in a page fault. (We are - * careful that, in this case, the value we read doesn't matter.) - * - * In vm86 mode, the hardware frame is much longer still, so add 16 - * bytes to make room for the real-mode segments. - * - * x86-64 has a fixed-length stack frame, but it depends on whether - * or not FRED is enabled. Future versions of FRED might make this - * dynamic, but for now it is always 2 words longer. - */ -#ifdef CONFIG_X86_32 -# ifdef CONFIG_VM86 -# define TOP_OF_KERNEL_STACK_PADDING 16 -# else -# define TOP_OF_KERNEL_STACK_PADDING 8 -# endif -#else /* x86-64 */ -# ifdef CONFIG_X86_FRED -# define TOP_OF_KERNEL_STACK_PADDING (2*8) -# else -# define TOP_OF_KERNEL_STACK_PADDING 0 -# endif -#endif - /* * low level task data that entry.S needs immediate access to * - this struct should fit entirely inside of one cache line @@ -56,6 +20,7 @@ */ #ifndef __ASSEMBLY__ struct task_struct; +struct pt_regs; #include #include @@ -66,11 +31,14 @@ struct thread_info { #ifdef CONFIG_SMP u32 cpu; /* current CPU */ #endif + struct pt_regs *user_pt_regs; }; +#define INIT_TASK_PT_REGS ((struct pt_regs *)TOP_OF_INIT_STACK - 1) #define INIT_THREAD_INFO(tsk) \ { \ .flags = 0, \ + .user_pt_regs = INIT_TASK_PT_REGS, \ } #else /* !__ASSEMBLY__ */ @@ -240,6 +208,7 @@ static inline int arch_within_stack_frames(const void * const stack, extern void arch_task_cache_init(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); +extern void arch_init_user_pt_regs(struct task_struct *tsk); extern void arch_release_task_struct(struct task_struct *tsk); extern void arch_setup_new_exec(void); #define arch_setup_new_exec arch_setup_new_exec diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S index 67c8ed99144b..0201ddcd7576 100644 --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -517,8 +517,7 @@ SYM_DATA_END(initial_page_table) * reliably detect the end of the stack. */ SYM_DATA(initial_stack, - .long init_thread_union + THREAD_SIZE - - SIZEOF_PTREGS - TOP_OF_KERNEL_STACK_PADDING) + .long init_thread_union + THREAD_SIZE - SIZEOF_PTREGS) __INITRODATA int_msg: diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index b650cde3f64d..e1c6350290ae 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -98,6 +98,11 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) return 0; } +void arch_init_user_pt_regs(struct task_struct *tsk) +{ + tsk->thread_info.user_pt_regs = (struct pt_regs *)task_top_of_stack(tsk)- 1; +} + #ifdef CONFIG_X86_64 void arch_release_task_struct(struct task_struct *tsk) { diff --git a/kernel/fork.c b/kernel/fork.c index f68954d05e89..85c4216bdcd8 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -958,6 +958,10 @@ int __weak arch_dup_task_struct(struct task_struct *dst, return 0; } +void __weak arch_init_user_pt_regs(struct task_struct *tsk) +{ +} + void set_task_stack_end_magic(struct task_struct *tsk) { unsigned long *stackend; @@ -985,6 +989,8 @@ static struct task_struct *dup_task_struct(struct task_struct *orig, int node) if (err) goto free_tsk; + arch_init_user_pt_regs(tsk); + #ifdef CONFIG_THREAD_INFO_IN_TASK refcount_set(&tsk->stack_refcount, 1); #endif From patchwork Thu Mar 2 05:25:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63242 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4068923wrd; Wed, 1 Mar 2023 22:08:53 -0800 (PST) X-Google-Smtp-Source: AK7set8YCdZAOWDSlWPR77+GWBeIF7dBfT3NewOFzcBgGL9qOpW+5b+gpi5bXcJrXDmGhdqo3ROd X-Received: by 2002:a62:6401:0:b0:577:272f:fdb with SMTP id y1-20020a626401000000b00577272f0fdbmr7335253pfb.29.1677737332940; Wed, 01 Mar 2023 22:08:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677737332; cv=none; d=google.com; s=arc-20160816; b=moCjA3nKG8ubp9IjNof8IUPmSzDzEpNbH8hw8RAQhvwLf+ijLshEiZ+PqphUqGxSUj eKwViDz74OFJZAHp2/dcoVkkvIr3bbIzXgG35+0ZSDet1Udx//Ps4HQ2mlhNIjEebt+w haJdNB69vDAMvFcW8sKK2nuenb1EVxUxnoyYNUw9gCvIR3vWCNNmBSrl3aTF0LsHt3PL +8HqF4aCykkxOI7AlGHaDfvROZfho4KkF5pjcfS2nmNZ4hQDm3TtBsCr+sRBa+zQ6sDG +D9sSC0UIABhGxLmtNSmy11Or4T0QKONdLs/MsaV+llhq1ccoVIC9gzc+S10nIrBBCBu bXhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kTBcKAMTLKESJNxm3nGpE/vMc0d6+JyySFIu52kBSMM=; b=c8rku9xLAyzVvnjEFrxzEasgspWxjCNNvxXlUrAwGI/3ERH4KgTLbAOf0Z2WSe3dEb ma3bsf2OxeVr8OdDGEDDUUYr+F1uH03XwxA5kja/LgHSBVjm8IkHLWcx5TIxYL+YJDL9 mC3a2ff4dyrrvCLA966nqBXpS1iqMbar+ylZrYF8oSxpcg/QCFjCKnElMyXFyQu1bdEq q+1/BOR1270eC3aEgfzqSZMKGXoRyfBMioviTJWmy5DI8uHSOzl1G4FDfbfWSPFn5tG/ 1Zzl/oO/re8Rm6U0KgI7Mr/V4PgM1kiV3SNROoWqigcDkK72mQoNYmjlbCW2T/IFLzx1 yQhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nswFl751; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x23-20020a63fe57000000b004fab4df6dfdsi13581494pgj.369.2023.03.01.22.08.40; Wed, 01 Mar 2023 22:08:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=nswFl751; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230223AbjCBFxW (ORCPT + 99 others); Thu, 2 Mar 2023 00:53:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230142AbjCBFwt (ORCPT ); Thu, 2 Mar 2023 00:52:49 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D7BA5678B; Wed, 1 Mar 2023 21:51:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736302; x=1709272302; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nd37h2vxkhLXg5jhh870M6BiFI8TxVn0dDXlR1ukIGo=; b=nswFl751pmmLDFyP37e7gHeibQgkZqHHeplFyVdpc8IzvD5JgDaDPUEf Pk5JBq47p8Z+OPAdgLQ+vwuJ2Y61jmBwDlqQt5Pz2t4ft+9Sv5A+hRPZe l6vNsNq/mqb0EGS/xU9T3Tip9a6BiejlNwIx6DqlP+zfOGa8hGH4n9MGo ldkv4Qgaqs56/O04gRJjR0rUX8ykBzRz1qsXEU62UujgqyA/XdxH5IlZ9 eq5sdiec2qscph1OZ0h8+e0SZq7yIkzvaSU2JVdpRAQniNsGiqD1BoOi6 0Z4vvYtfG91rRYzrUEmXJSgRMLTo9b6ZHLmTHCRYCSZQkiSe+GUAvZuhA Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887327" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887327" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530980" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530980" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:52 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 32/34] x86/fred: disable FRED by default in its early stage Date: Wed, 1 Mar 2023 21:25:09 -0800 Message-Id: <20230302052511.1918-33-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759235101824019307?= X-GMAIL-MSGID: =?utf-8?q?1759235101824019307?= Disable FRED by default in its early stage. To enable FRED, a new kernel command line option "fred" needs to be added. Tested-by: Shan Kang Signed-off-by: Xin Li --- Documentation/admin-guide/kernel-parameters.txt | 4 ++++ arch/x86/kernel/cpu/common.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6221a1d057dd..c55ea60e1a0c 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1498,6 +1498,10 @@ Warning: use of this parameter will taint the kernel and may cause unknown problems. + fred + Forcefully enable flexible return and event delivery, + which is otherwise disabled by default. + ftrace=[tracer] [FTRACE] will set and start the specified tracer as early as possible in order to facilitate early diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index eea41cb8722e..4db5e619fc97 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1467,6 +1467,9 @@ static void __init cpu_parse_early_param(void) char *argptr = arg, *opt; int arglen, taint = 0; + if (!cmdline_find_option_bool(boot_command_line, "fred")) + setup_clear_cpu_cap(X86_FEATURE_FRED); + #ifdef CONFIG_X86_32 if (cmdline_find_option_bool(boot_command_line, "no387")) #ifdef CONFIG_MATH_EMULATION From patchwork Thu Mar 2 05:25:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63238 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4067596wrd; Wed, 1 Mar 2023 22:05:36 -0800 (PST) X-Google-Smtp-Source: AK7set81fQF2Yoa9njVb2phjnv4xjA5UOMvhNka4YogsQFsCC8Lc/9EICr3x43sOuIrsJwZi6v8P X-Received: by 2002:a17:90b:38c7:b0:236:704d:ab8c with SMTP id nn7-20020a17090b38c700b00236704dab8cmr10167514pjb.26.1677737136558; Wed, 01 Mar 2023 22:05:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677737136; cv=none; d=google.com; s=arc-20160816; b=zkp19tIPVL7KdKwG+Ht1cJh3Y69q4JQpKXxpOrVmzSulreMGR++YaQMilahu1AaaGt gbTsI8wJn+PpSvvSz3KkajAQ/EjDZKmUXStBUcHMxG/Gdoal7QrmowIBgbXjhrA9bi66 E5/bkmFNI6CWgaD7UNGC/Vph4QO1720w2MiXrMRjOWzaiGAHun5pdD/1s69pzRYaNbmd r+7QGR0Tx9GvN2THYyYLCY4eINTIVRo79EZMgKsOvbtrddv1meuCnY2bQE6LaLNxw2lv 9UksWCOO20eb1ZxUuuNyH5oLd5ca2dUZr1eHd8TLT2aZh8a4MYOfs/SQ1P8uvuPc6kgN du1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SqHjZXDgyS1oVc60Lvg2+40vBxpCajlVSkR5hchHg+Q=; b=R16LLDB2Hj1ApXP+SVX8kuCxDWqdfuzqssuCFvyDJkMMXOCXuXCLOfPZf67PkakaCr tCy9So+GrwizAd+xn0/oy67YXgE1OjxttmH76sXRh5B5H6i3STK3ekF3rk0V8LDfhHm7 D+ayktagicuoccZTpvgVLQnygRF8bfKvUhgcrjGTu5oCZvZIR+RDLoQXZOu5Qb3onDIR FjkBHldWP7q0qtLyP0QvoHbVSqcLa5JQRerrlO/gIe5M18W122/7IU6i7WUOKbsUFy9r cG4HoQFuBk6nFRa/OM6w1IG/2O+DC3HXcwV5zys6IwbKlaYywj3QS+/Grm6dKMtBj6IN 5egA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Swxnp4HC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 11-20020a17090a004b00b0021918bc9a47si1391517pjb.174.2023.03.01.22.05.22; Wed, 01 Mar 2023 22:05:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Swxnp4HC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229982AbjCBFxL (ORCPT + 99 others); Thu, 2 Mar 2023 00:53:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229910AbjCBFwp (ORCPT ); Thu, 2 Mar 2023 00:52:45 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 513B14BE9D; Wed, 1 Mar 2023 21:51:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736298; x=1709272298; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RB+pcoV+8WefgwtLPP9+JmvXNsCQtNuVUpY6dnzCLDE=; b=Swxnp4HCb91tti4020hv6rCY46wgARud6jyH+qTRuPT64oW1y3CdwNzL XuogKFv7751KYpgY7olljw5k5I9EA0p8l9/Jt48CzCzgyfgTdEomFeSuR nN8zb8hbxLP/D3JBgsIXlmqE9l80khtINTXnKBiA7Iy1rOgPA3Aewnjlu QNl/ytgKDyoG2s0/zT+AJgGe2nIb6qqRVm/oO+OomLBO4zZlxqNKSLOi5 LQJdtQvXC9nz9R+Di6tGy0jud/4Y0ldAi6mW0//J+YPanqK9xhhPQ6WZE isreuOdhxkltPB2NcxhFwWSQFriTYA0rOU7HBJeVmN+mou2U2WTPUvyUR A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887332" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887332" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530983" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530983" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:52 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 33/34] KVM: x86/vmx: call external_interrupt() for IRQ reinjection when FRED is enabled Date: Wed, 1 Mar 2023 21:25:10 -0800 Message-Id: <20230302052511.1918-34-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234895282555515?= X-GMAIL-MSGID: =?utf-8?q?1759234895282555515?= When FRED is enabled, IDT is gone, thus call external_interrupt() for IRQ reinjection. Create an event return stack frame with the host context immediately after a VM exit for calling external_interrupt(). All other fields of the pt_regs structure are cleared to 0. Refer to the discussion about the register values in the pt_regs structure at: https://lore.kernel.org/kvm/ef2c54f7-14b9-dcbb-c3c4-1533455e7a18@redhat.com/ Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kvm/vmx/vmx.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index bcac3efcde41..30f854015c8c 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -47,6 +47,7 @@ #include #include #include +#include #include #include @@ -6923,7 +6924,26 @@ static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) return; kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); - vmx_do_interrupt_irqoff(gate_offset(desc)); + if (cpu_feature_enabled(X86_FEATURE_FRED)) { + struct vcpu_vmx *vmx = to_vmx(vcpu); + struct pt_regs regs = {}; + + /* + * Create an event return stack frame with the + * host context immediately after a VM exit. + * + * All other fields of the pt_regs structure are + * cleared to 0. + */ + regs.ssx = __KERNEL_DS; + regs.sp = vmx->loaded_vmcs->host_state.rsp; + regs.flags = X86_EFLAGS_FIXED; + regs.csx = __KERNEL_CS; + regs.ip = (unsigned long)vmx_vmexit; + + external_interrupt(®s, vector); + } else + vmx_do_interrupt_irqoff(gate_offset(desc)); kvm_after_interrupt(vcpu); vcpu->arch.at_instruction_boundary = true; From patchwork Thu Mar 2 05:25:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 63237 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4067386wrd; Wed, 1 Mar 2023 22:05:08 -0800 (PST) X-Google-Smtp-Source: AK7set8EChU7ztE02n5sTJ4JWffJLAtSU80bLBxvvgx72sKvMH+MRwxK4RhvUn3g1ADu1e9Kexxw X-Received: by 2002:a17:90a:190d:b0:237:659a:a456 with SMTP id 13-20020a17090a190d00b00237659aa456mr10076628pjg.49.1677737108561; Wed, 01 Mar 2023 22:05:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677737108; cv=none; d=google.com; s=arc-20160816; b=VNFgt1ccZTEkZb2skCpS88VQKt3iCeNwIncgNplPNqn3iHzKObMyyD26d77dFkG+QI 9FVB4D/OPgjkbFRPLkzMlVVKDKMyDeZEh58Qpo9qZ347cXwYX3IYQx7VjMhp030QIhaN qAbqWSUvwPiLzN+bcvCIHCC6AtEsO64pvpsE2IblmAiyDwO1bIANehoL0G6orUT6mxtW I46Kx6HVsokmyok2Yp5WcycsFdQqnQEHCOiAiVJ5kTGqxxT/2jJQQvmETTea+svcfIKd qwbF24WMzp8Xf72DpnYtM6ZuqRQ9kGeoDpjIGwOWZTqd4oUhk8sn2UMQNG+w1yxQwxa8 o6/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qNazW7SX8KMj5ZY7lzPccvEmZuUliNNIPrFxMrj6GD4=; b=vqBud4NTMeVJs+yF1esVyBdLGGhIf4rgpAJpQnbdCLUADqqHyNYy9PKHgVCoy54u7N Jo7LVv6TrjL1gL+GZ1o8mCTXeNI/C30Eft8yZMaFVeJPoLa/G6uMkayBP2lWE/Jit5Yb iTyjIbguoGVOiRq+tv/9WaYRd9Cyy/7NbehKVMlYbe2ejW4JJJk4pMH3L670hFCAL/lr u4slNCz/tAXhLHLRRt0Gj5EUNwy4DwOjZ+U2ehBiBz36TQLtnQgGi/CZaRUpWHhktIbK 2zWk1tW77dAm+b/s8JXGaNh2u56zxzSKmUcIjZ6cbWwHO5rix/TL/+acnLuk80frl72V qYzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=iM7D+6tm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ci22-20020a17090afc9600b0023027272515si1547484pjb.101.2023.03.01.22.04.52; Wed, 01 Mar 2023 22:05:08 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=iM7D+6tm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230210AbjCBFxP (ORCPT + 99 others); Thu, 2 Mar 2023 00:53:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229620AbjCBFwj (ORCPT ); Thu, 2 Mar 2023 00:52:39 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D42F656512; Wed, 1 Mar 2023 21:51:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677736296; x=1709272296; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GKXTMdUzJkVqC+CQLNZb60zKnOqG48lGuDswKhO/vhg=; b=iM7D+6tmWbngB+ozKYoez+Sjj5eS96l2s7u3MhLA+ehoPe1/0BVktJiR UmSkaDDo8MPeFpQqSUGlauWrqPtastnmLFd11Gm/gDE/TFmkQKrf0Ji48 shIUEd18M92hNCfz9t5b4gePB4e0eH07pPHaUbfeVWhdGgutABtURPb4B 1h/RnYBPw9W1SZ28dn9RNe/yFajNUaQdOm17ISkZrz4HpJ28AWn53f4u0 UhI4OLxrBUhD6+F+kiC8s3m7sCqBC26Tci4NB0k1jnD2U2l8n/zcEAOQc DakJqKcyOZt09qYsZgFN/nG4NJMGTEFpNMJr7R0R/0fNULDE0WlPNmcbb Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420887335" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="420887335" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 21:50:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="920530987" X-IronPort-AV: E=Sophos;i="5.98,226,1673942400"; d="scan'208";a="920530987" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga006.fm.intel.com with ESMTP; 01 Mar 2023 21:50:52 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [PATCH v4 34/34] KVM: x86/vmx: execute "int $2" for NMI reinjection when FRED is enabled Date: Wed, 1 Mar 2023 21:25:11 -0800 Message-Id: <20230302052511.1918-35-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302052511.1918-1-xin3.li@intel.com> References: <20230302052511.1918-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759234866517585234?= X-GMAIL-MSGID: =?utf-8?q?1759234866517585234?= Execute "int $2" for NMI reinjection when FRED is enabled. Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/kvm/vmx/vmx.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 30f854015c8c..b9644bd37672 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7229,7 +7229,10 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu, if ((u16)vmx->exit_reason.basic == EXIT_REASON_EXCEPTION_NMI && is_nmi(vmx_get_intr_info(vcpu))) { kvm_before_interrupt(vcpu, KVM_HANDLING_NMI); - vmx_do_nmi_irqoff(); + if (cpu_feature_enabled(X86_FEATURE_FRED)) + asm volatile("int $2"); + else + vmx_do_nmi_irqoff(); kvm_after_interrupt(vcpu); }