From patchwork Wed Mar 1 23:47:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63116 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930124wrd; Wed, 1 Mar 2023 15:38:38 -0800 (PST) X-Google-Smtp-Source: AK7set/fAHezCHiQyu6M9EQu8uDE47CYz8dNmzQfjw5ggGFhHJITDk7LopEx8u0bh0B2a6F7x5V4 X-Received: by 2002:a17:903:41c9:b0:199:10d2:b9da with SMTP id u9-20020a17090341c900b0019910d2b9damr8836865ple.58.1677713918641; Wed, 01 Mar 2023 15:38:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713918; cv=none; d=google.com; s=arc-20160816; b=P8YcY4A3VQKat9IHMa+Agd8zINjgbzfZh7h2qJeo/ON4+Wee/MV0hTp0UvmR3z8b5C A3ZRGwjxMVGRFaiFv5dmkhHX4jNDrRCxCJuzDfGrTh8wcPoKQPcKV6Mp3y8MLZMjFaWT D98q9+YlHm3Kni4k/Eox2YFQXLHWzRlRrF9sVdtAElcJKrujUvJF4TniCWiq8VIzm759 3eTJbv2iguCWX6WENUfj4euWBDXAj4B6nO/obuNbVGVyfCtUnG2MvjxV9jYFcFP0G0Qw NN3H5cMCBq1zJANqqkTepNXIWLES6GIpCoRCMqbwPYTP6fcSWf6BYUOgMr5/RlROH2wK kOXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=td0bg65O/hn+p0o81VE6h7CSn2Vwjm9D5XZXG0khKdg=; b=enTBQanVIGvVdkYxk9H/7jJqu2xCXaxFWx4sqQc29BsMdX6c+VeyQise/r91KcNoBW kVA+CxDKB20Aosw4P58Brd4hG+ZFnU2C2aMQtL1rbvK7lP1zYN8PoShHwphmcy5IKhpn 7fqercEvhYPcsB1EAU9BLVWgQVC/BMe8cLE7BO5BkX7m1c9cbMduir0nU99TbPN+BXBS hWIxNtqzMoNshLluWQvZGA8+P1JEl6OkhOurQ3ZhKNbbJAtT6m0qUuD8aXqMeJep+MyI pFSavH5JOcXyaQzK2E3oUpagci062KquIz9ad9f3PF77l0kP1AiqpMos6zn1U9PGROMH 82ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Rbp29A0L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id kp11-20020a170903280b00b0019c3ce49a13si12667290plb.372.2023.03.01.15.38.25; Wed, 01 Mar 2023 15:38:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Rbp29A0L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229722AbjCAXiF (ORCPT + 99 others); Wed, 1 Mar 2023 18:38:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229668AbjCAXiA (ORCPT ); Wed, 1 Mar 2023 18:38:00 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FB4583EA for ; Wed, 1 Mar 2023 15:37:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713877; x=1709249877; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Lma7M0NQuejLahUyWUzCNBxEauMnVUBUBK0aoIXgw+I=; b=Rbp29A0LomMKJkyDvD7JdSEuL8Cq3xnbRUldelPxgwWyAo62+UmZT4kA tSFVsLkW5axnUJ5VSc94eRgDBamO8sLM4lkl4ihHqOo7eGS0nzI7lWl9k Oey860/m8I7pbJtLmzhwSf63jz3EnTWpq8qcN2C0cdY0KBKqvw9VaC2Nm Tg7irCmwNAh8H06XCTPCe8UIv4fnrIaUJtJ18FRwlJ9RTiGrSGixL4+qN /R2cv2akakWlOzfwTfJO/SuY0qRgnKZdmxTzESiaJmgRDOyMfhEA+tssb j9TMDOng5eKtDBDC+SaBjEbKSSbit2Bk0LCE3U5l96K16VSIg2u4+ye+g g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818679" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818679" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826785" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826785" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:55 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 01/24] x86/apic: Add irq_cfg::delivery_mode Date: Wed, 1 Mar 2023 15:47:30 -0800 Message-Id: <20230301234753.28582-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210550030612518?= X-GMAIL-MSGID: =?utf-8?q?1759210550030612518?= There are no restrictions in hardware to configure the delivery mode of each interrupt individually. Also, certain interrupts need to be configured with a specific delivery mode (e.g., non-maskable interrupts). Add a new member, delivery_mode, to struct irq_cfg to this effect. To keep the current behavior, use the delivery mode of the APIC driver when allocating a vector for an interrupt in the root domain (i.e., x86_vector_domain). Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Ashok Raj Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Reworded the commit message to accurately state that the root domain allocates a vector for an interrupt, not an interrupt. (Thomas) * Removed stray newline. (Thomas) * Replaced 'irq' with 'interrupt' in the changelog and in the code. (Thomas). Changes since v5: * Updated indentation of the existing members of struct irq_cfg. * Reworded the commit message. Changes since v4: * Rebased to use new enumeration apic_delivery_modes. Changes since v3: * None Changes since v2: * Reduced scope to only add the interrupt delivery mode in struct irq_alloc_info. Changes since v1: * Introduced this patch. --- arch/x86/include/asm/hw_irq.h | 5 +++-- arch/x86/kernel/apic/vector.c | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h index d465ece58151..5ac5e6c603ee 100644 --- a/arch/x86/include/asm/hw_irq.h +++ b/arch/x86/include/asm/hw_irq.h @@ -88,8 +88,9 @@ struct irq_alloc_info { }; struct irq_cfg { - unsigned int dest_apicid; - unsigned int vector; + unsigned int dest_apicid; + unsigned int vector; + enum apic_delivery_modes delivery_mode; }; extern struct irq_cfg *irq_cfg(unsigned int irq); diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index c1efebd27e6c..633b442c8f84 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -573,6 +573,12 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, /* Don't invoke affinity setter on deactivated interrupts */ irqd_set_affinity_on_activate(irqd); + /* + * A delivery mode may be specified in the interrupt allocation + * info. If not, use the delivery mode of the APIC. + */ + apicd->hw_irq_cfg.delivery_mode = apic->delivery_mode; + /* * Legacy vectors are already assigned when the IOAPIC * takes them over. They stay on the same vector. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 02/24] x86/apic/msi: Use the delivery mode from irq_cfg for message composition Date: Wed, 1 Mar 2023 15:47:31 -0800 Message-Id: <20230301234753.28582-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210545439689008?= X-GMAIL-MSGID: =?utf-8?q?1759210545439689008?= irq_cfg provides a delivery mode for each interrupt. Use it instead of the hardcoded APIC_DELIVERY_MODE_FIXED. This allows to compose messages for NMI delivery mode which is required to implement a HPET- based NMI watchdog. No functional change as the default delivery mode is set to APIC_DELIVERY_MODE_FIXED. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Reworded changelog as per suggestion from Thomas. Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/kernel/apic/apic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 20d9a604da7c..352738238e52 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2562,7 +2562,7 @@ void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical; msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF; - msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED; + msg->arch_data.delivery_mode = cfg->delivery_mode; msg->arch_data.vector = cfg->vector; msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; From patchwork Wed Mar 1 23:47:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63117 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930141wrd; Wed, 1 Mar 2023 15:38:41 -0800 (PST) X-Google-Smtp-Source: AK7set+CxVlz4zCZstHRMiK2FzY3LRAVhSmStVZgEusoYmJQOurOB7xYuhJO68sPnTmW4NrOqZaT X-Received: by 2002:aa7:9f04:0:b0:5df:3aa1:10c5 with SMTP id g4-20020aa79f04000000b005df3aa110c5mr7715123pfr.14.1677713920945; Wed, 01 Mar 2023 15:38:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713920; cv=none; d=google.com; s=arc-20160816; b=xFKi9KyJQs1/9O6K7rATcOhtH9DExFENuvTMPbQrr9eqHlL4qpeOv59t3B3AR0ElVO +RKAgxOX0BvYYr1fhWwyJsxGBA9ls4UY7devFjcqVqhGjiIF24DeeLZKtT039IhCrR05 9G9uz9MTzvf4WEGIaE8RkyDnZjzFQEltIoytphY09j9RGL+k1Jh4yiG8t8g/P3HttXrp 5xn7KZ+NBGkYX1vLzEts2RH3CJZPZakJ5y5DJhjPw+ZheAmI4KeSNeVwQlrlNdMIQ07k DkBgCb+NJWeY7UlTWQXv2+qfQxD+fTbcGy3nvlHx7kCnJF9OcWuYa0afQINJnwn/f0vb KwcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=t9OmpV+zajdqs2vAcLxvmf6pJ/GGJn3s5SvX/jFumSk=; b=TZEGJU07gpuuTnQMIlmBHfhdB6WMlBdqdo5NaZu8uA6Y6UIPnxBVuGC+FhJdekQwhJ YFUwUnoWsP7z+ujgJnnLUIx4qxHss6NCKOAgbLBohDMojv7MbEjFx8+mIHyFEvPZ7MXT CpfK0iBdjtQHe2h7biEWQRdIOJ8waDA+Pia50QCAdvCafEIqy5BK/IJSsqzL0aGmKSKr KEO7pPu3WVVo3CJTPf6xVjQ6LqTTOs/Qnz1O2eFBczm0S6IHOf0XDluyCRTyTsougYnM BR1oatMEXr6wRgnU2F5gVLau2lAte+BHW5AwCmxyASRJz3tf3z3CnWFD4Z893yy9gxfG pWfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=AG6EEcZN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 03/24] x86/apic: Add the X86_IRQ_ALLOC_AS_NMI interrupt allocation flag Date: Wed, 1 Mar 2023 15:47:32 -0800 Message-Id: <20230301234753.28582-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210552011944124?= X-GMAIL-MSGID: =?utf-8?q?1759210552011944124?= There are cases in which it is necessary to set the delivery mode of an interrupt as NMI. Add a new flag that callers can specify when allocating an interrupt. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/include/asm/irqdomain.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/irqdomain.h b/arch/x86/include/asm/irqdomain.h index 30c325c235c0..e13f02c6fe95 100644 --- a/arch/x86/include/asm/irqdomain.h +++ b/arch/x86/include/asm/irqdomain.h @@ -8,6 +8,7 @@ #ifdef CONFIG_X86_LOCAL_APIC enum { X86_IRQ_ALLOC_LEGACY = 0x1, + X86_IRQ_ALLOC_AS_NMI = 0x2, }; extern int x86_fwspec_is_ioapic(struct irq_fwspec *fwspec); From patchwork Wed Mar 1 23:47:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63118 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930188wrd; Wed, 1 Mar 2023 15:38:46 -0800 (PST) X-Google-Smtp-Source: AK7set97wbUQJaLHroI71UQOiLdT9XY9SQBE5S5z3BeC/U++MO3Np/ZaU2YtRP6PP1K7Dvlf4bTb X-Received: by 2002:a17:902:e5c9:b0:19e:68b1:65b9 with SMTP id u9-20020a170902e5c900b0019e68b165b9mr920166plf.12.1677713925848; Wed, 01 Mar 2023 15:38:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713925; cv=none; d=google.com; s=arc-20160816; b=y81gFNB6B0ELHT32hZu5oyTEIW7XmF/zR2H7+wKCbNSst8jy0iUjDui56ykdYFQX0E RGdYDxYkR9kJuS1R49CWoFNhXBWOgdeLvqyTi6QNQkFNikI39o3EvrXcuF7MfuniQH8b ef3xg2djUb9yX+uSopNzKiS25WqOIBMgYpfQiigxaeDgueoHdeQK+fw1dDoFW94ri4lf Jp2+BuIR84EwTqEhoj09ZIBzxQe+WDm15/rC1pwGj90JQ+x6bHUGw8kj0g4KHJBJynPU Tzzt4RZYAkynDu8QEJJ2Nrpv0UaOOVAWb/RWMpSjpQllxzuzAY37wsXofzx5ODQHs4II SkLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=WcZs4H84cZUR6K5ts1I15i3nzh2UFphkMr1RwhRpDWs=; b=wcQAt9m1j/6MqC2DKh7FPnhtzBi6uiMvk44dGdVZBUdYv1KGKQPmRR2Kl8rKvf6O+u OHMAQR4+Z7x9Vyz2k6ohy4Ke1rzaGUl9F+SVJ1/b7AxGPHC9nhZ+mKT527TOB4zlaTVa +vBLThla4+a6HxJfX+e9AYw6XJFVrQkHN1yrXCRC7TgkwEzXMaaW+P5tWu3euwnvNWjL Sn45PWNjz5Tx77BNi07reZIB/734mH5fMqialkzGdYXUuT2GxdMmN8fOlB74dG/1vTtz 0JjlwuA1bVZxzon9zmvZdNBrufNiQ67bvsncVhkJ+43KBuLkid8BV09Cjl41R9UOOHsk ChpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=i2Gz5+Gk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id kr15-20020a170903080f00b0019a5aa4d768si13490829plb.611.2023.03.01.15.38.32; Wed, 01 Mar 2023 15:38:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=i2Gz5+Gk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229760AbjCAXiL (ORCPT + 99 others); Wed, 1 Mar 2023 18:38:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229698AbjCAXiC (ORCPT ); Wed, 1 Mar 2023 18:38:02 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 896E712048 for ; Wed, 1 Mar 2023 15:38:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713880; x=1709249880; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=elKTscyLR7FY5NmvjkmQhnEbe/r3S/2u7x+nfhQMrvU=; b=i2Gz5+Gk6raZEHI3nT/mpotyDkHDlrTfR9iMvhRCAAMYDPx24s+FifsW FuOaDGNzzk8lR2L8GKMFSaZywPoanaTWYZVZnvYs6PXayBli7NR7XksAy i5KHTp3jjbD0gGoXgN0Koy0cKjC4DdnHO5tqheKiDVoDtPw8/lr9OpxAE //yHY5xZs/4juYFxOlEqQ9kF0ww8k9rRGGeiFzwG0vrVrvmDuCCwHgpvK KZTA7CZb7gUm/u8G8qeV1Sol4dycamKaYJb1jcNiMCrw+t+nH3RUWTyF+ XMjEZB17bHWtTwveov1zsdmz1zxibmjSj+YD2qaaUM8pmBi58y6pWcEa1 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818693" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818693" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826798" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826798" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:56 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 04/24] x86/apic/vector: Implement a local APIC NMI controller Date: Wed, 1 Mar 2023 15:47:33 -0800 Message-Id: <20230301234753.28582-5-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210557483970100?= X-GMAIL-MSGID: =?utf-8?q?1759210557483970100?= Add a separate local APIC NMI controller to handle NMIs apart from the regular APIC management. This controller will be used to handle the NMI vector of the HPET NMI watchdog. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Thomas Gleixner Signed-off-by: Ricardo Neri --- Changes since v6: * Reworked patch "x86/apic/vector: Implement support for NMI delivery mode" into a separate local APIC NMI controller. (Thomas) Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/kernel/apic/vector.c | 57 +++++++++++++++++++++++++++++++++++ include/linux/irq.h | 5 +++ 2 files changed, 62 insertions(+) diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index 633b442c8f84..a4cf041427cb 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -42,6 +42,7 @@ EXPORT_SYMBOL_GPL(x86_vector_domain); static DEFINE_RAW_SPINLOCK(vector_lock); static cpumask_var_t vector_searchmask; static struct irq_chip lapic_controller; +static struct irq_chip lapic_nmi_controller; static struct irq_matrix *vector_matrix; #ifdef CONFIG_SMP static DEFINE_PER_CPU(struct hlist_head, cleanup_list); @@ -451,6 +452,10 @@ static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd, trace_vector_activate(irqd->irq, apicd->is_managed, apicd->can_reserve, reserve); + /* NMI has a fixed vector. No vector management required */ + if (apicd->hw_irq_cfg.delivery_mode == APIC_DELIVERY_MODE_NMI) + return 0; + raw_spin_lock_irqsave(&vector_lock, flags); if (!apicd->can_reserve && !apicd->is_managed) assign_irq_vector_any_locked(irqd); @@ -472,6 +477,10 @@ static void vector_free_reserved_and_managed(struct irq_data *irqd) trace_vector_teardown(irqd->irq, apicd->is_managed, apicd->has_reserved); + /* NMI has a fixed vector. No vector management required */ + if (apicd->hw_irq_cfg.delivery_mode == APIC_DELIVERY_MODE_NMI) + return; + if (apicd->has_reserved) irq_matrix_remove_reserved(vector_matrix); if (apicd->is_managed) @@ -539,6 +548,10 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, if (disable_apic) return -ENXIO; + /* Only one IRQ per NMI */ + if ((info->flags & X86_IRQ_ALLOC_AS_NMI) && nr_irqs != 1) + return -EINVAL; + /* * Catch any attempt to touch the cascade interrupt on a PIC * equipped system. @@ -573,6 +586,25 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, /* Don't invoke affinity setter on deactivated interrupts */ irqd_set_affinity_on_activate(irqd); + if (info->flags & X86_IRQ_ALLOC_AS_NMI) { + /* + * NMIs have a fixed vector and need their own + * interrupt chip so nothing can end up in the + * regular local APIC management code except the + * MSI message composing callback. + */ + apicd->hw_irq_cfg.delivery_mode = APIC_DELIVERY_MODE_NMI; + irqd->chip = &lapic_nmi_controller; + /* + * Exclude NMIs from balancing. This cannot work with + * the regular affinity mechanisms. The local APIC NMI + * controller provides a set_affinity() callback for the + * intended HPET NMI watchdog use case. + */ + irqd_set_no_balance(irqd); + return 0; + } + /* * A delivery mode may be specified in the interrupt allocation * info. If not, use the delivery mode of the APIC. @@ -872,8 +904,27 @@ static int apic_set_affinity(struct irq_data *irqd, return err ? err : IRQ_SET_MASK_OK; } +static int apic_nmi_set_affinity(struct irq_data *irqd, + const struct cpumask *dest, bool force) +{ + struct apic_chip_data *apicd = apic_chip_data(irqd); + static struct cpumask tmp_mask; + int cpu; + + cpumask_and(&tmp_mask, dest, cpu_online_mask); + if (cpumask_empty(&tmp_mask)) + return -ENODEV; + + cpu = cpumask_first(&tmp_mask); + apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); + irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK; +} + #else # define apic_set_affinity NULL +# define apic_nmi_set_affinity NULL #endif static int apic_retrigger_irq(struct irq_data *irqd) @@ -914,6 +965,12 @@ static struct irq_chip lapic_controller = { .irq_retrigger = apic_retrigger_irq, }; +static struct irq_chip lapic_nmi_controller = { + .name = "APIC-NMI", + .irq_set_affinity = apic_nmi_set_affinity, + .irq_compose_msi_msg = x86_vector_msi_compose_msg, +}; + #ifdef CONFIG_SMP static void free_moved_vector(struct apic_chip_data *apicd) diff --git a/include/linux/irq.h b/include/linux/irq.h index b1b28affb32a..c8738b36e316 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -263,6 +263,11 @@ static inline bool irqd_is_per_cpu(struct irq_data *d) return __irqd_to_state(d) & IRQD_PER_CPU; } +static inline void irqd_set_no_balance(struct irq_data *d) +{ + __irqd_to_state(d) |= IRQD_NO_BALANCING; +} + static inline bool irqd_can_balance(struct irq_data *d) { return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); From patchwork Wed Mar 1 23:47:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63120 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930215wrd; Wed, 1 Mar 2023 15:38:50 -0800 (PST) X-Google-Smtp-Source: AK7set9drDWRJ5MBm70IFNszfbc5fN6oq2RmH6Xi1awBOjDKd1EFIkDpSY0sXoOMDDT6eEMfsgXQ X-Received: by 2002:a17:90b:3505:b0:237:9fbd:31c8 with SMTP id ls5-20020a17090b350500b002379fbd31c8mr9371079pjb.15.1677713930151; Wed, 01 Mar 2023 15:38:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713930; cv=none; d=google.com; s=arc-20160816; b=z8xl8A2/SHUMNPCaUJHO9sbJDBoE6pZGFtMTKIsZa1IEqns2P08uNm9Vgfip/kP082 cnV16wKjxDqGqtlAAPe53KI+SCiAZYrJhCi0amqt7o1oEMKvwEdFi3YvvDGkEGT6ZH+n F3XUaVdtn5ZT8buPkwDrcxJqfE3R8ceXqDU/Ep7hCr2uKUY6Vl3rvUcMCyDHibFImrK+ CztVhNZH9bno2s+4Q7yN7+CPCY9K3Uw87YNejPvHIGF+YYl/fP+sWAuGIs9hnY6KP0G9 rk8NbLLuseo/dI5HMR8BZ+QkFFFcHzz2MCuWz+6zXjT2MnT0M32/xgBJjGa1PFTC9OfZ UtnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=QLQ2l4OCpPhLz+/QptXDjpPD8B24m3g4SwjZHSbQdlU=; b=dqmYbc3iXsLOE+xar17WCwsCLIyt20eZM4J9mmXDg+2C/0ikTTLEIlSIzcY9Y2RpYd 3SHA91zQ/sln54Q4ebALm32E0OTNTFqqHC0AWscSDEB30qxlrD/bxLlCziJzJMXnSMNM 5e5PBhRcVBfRcvP+wLWMWSVXFYuKfTfJ9RUOUDzVm3tTS7nX9gEGRkDSNwdK48+pKxLa 9+R+uhpOkwKX+9rzzfFXbOzXDCDk7eNXov+qBOUsvn2Sn8sYorYoEa2gkhLYN6qLyfh0 SWPUdt1n5JeOpPvyw+W6XWBb3z/JNam1Br3HXr+12+E5IXhBCdDSW/sEgqUqaVcL8saj 4S1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="Gsiwbs/i"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 05/24] x86/apic/vector: Skip cleanup for the NMI vector Date: Wed, 1 Mar 2023 15:47:34 -0800 Message-Id: <20230301234753.28582-6-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210561788801244?= X-GMAIL-MSGID: =?utf-8?q?1759210561788801244?= The NMI vector is fixed. No cleanup is needed after updating affinity. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * Introduced this patch. Changes since v5: * N/A Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/kernel/apic/vector.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index a4cf041427cb..3045823ecc1b 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -1050,6 +1050,10 @@ void send_cleanup_vector(struct irq_cfg *cfg) { struct apic_chip_data *apicd; + /* NMI has a fixed vector. No vector management required. */ + if (cfg->delivery_mode == APIC_DELIVERY_MODE_NMI) + return; + apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); if (apicd->move_in_progress) __send_cleanup_vector(apicd); From patchwork Wed Mar 1 23:47:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63119 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930203wrd; Wed, 1 Mar 2023 15:38:48 -0800 (PST) X-Google-Smtp-Source: AK7set/ZhO3SwfIHFzb9vdQGEjhnkoNq2EbkGdC8atjurrmNYjgcAs+0ygRVCNUbroQhGaAtb3TY X-Received: by 2002:a17:902:c40a:b0:19a:5958:15e7 with SMTP id k10-20020a170902c40a00b0019a595815e7mr221945plk.15.1677713928051; Wed, 01 Mar 2023 15:38:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713928; cv=none; d=google.com; s=arc-20160816; b=YUqyTw2TKFh9k80ssFPD5YD60C7rKVFCJX4iAMP4DxR4MoAdPZ7ykqN4mdtGmzOCwu E6DB+uFTKGMB3WonvglBdadDxDZB0cFxk7gYlZCiJOlyyeAWRbhDKKNvROXmxFUam5py P3U5KI6IWKG3cns+zD9cx0GcL87g4LTn/ZeBmNLvXNelk71CcZWszsQ32CSfcxghT8HD MixXuBMZ1IVgzp5LU8dzZxuQX0HJpiCSc8noHKUvgR2fqo3dzPQ3gp+gW4KnKokyJuGs bt/7nxhFpZ/w4zCjSTzHJ5E5g0moEdTI2zkYBgFeKerWJlTHGDA+Tikj257NBlNRip0Z K4cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=VesRT7Uenz+82/JojPKqw9GKagrHXkP9877mGWnY20M=; b=gHnXNqBdyp6dwuMhny/MA/hbr0l/3u6ASu66p0BaBGqBX71j3FafwXH13PYNFS8a6c Oj0bjTOshj+c3WPoFZWFvpPyU3L1V16NW5Jn5ssaIEI3+wcfPwrTm6Nm9O7ODIn+JQJG QvVvLg6I4r7PKC9DmvvMNI1ncejyw/q6jVxJGYDAyOLurh3kQ2HU6DSmtUTPouVuNRIg 8JQSCb6Em/unTjqNZMNWCOVB7yRSEUjS0NHEzfNd/jskCWgthB2AqzT7kdHeYDY84y75 XHi6M/TAPAfkK4lmYWNnvAOqMacEyBUvZ3/38JnFod9AyvML6qMsSacoMl0V5fP08kLI cdRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="Aql3E/Zu"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id jd1-20020a170903260100b00177568a0e53si13422907plb.252.2023.03.01.15.38.34; Wed, 01 Mar 2023 15:38:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="Aql3E/Zu"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229740AbjCAXiP (ORCPT + 99 others); Wed, 1 Mar 2023 18:38:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229564AbjCAXiD (ORCPT ); Wed, 1 Mar 2023 18:38:03 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21456191 for ; Wed, 1 Mar 2023 15:38:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713882; x=1709249882; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=X+fPhGM+miLCMioUQX1fq5QvQADp974IGsVIuBa8IIM=; b=Aql3E/ZuO4ARPqEBFylMJIskEl/mwYpErfaS7ZlfOX0oX67sUtAA8RYr iZQWNXj2ZEHYfxAXbTvJtX4BpjRGycs4demGZ7p+BRFcd6mv0T2L1S/iC nDMBZXynt5uPwD+/2YEFjWYwXB/Vgwbct0936YK5Lm49SYseYo2FVlpF1 j74CQlOjyL0pbnbIR4ezJQmA2li6Ug5nOHRwQyUzms5TVbn59ySHr8bHD fOcfxB0nxQ5xM2YFf7MowjPvr1kqCYbKZlQS1Wrqs7P49yRqVQ7ikCJE5 UTCSvTk3BtwtkZwxggOynuUZBTXJ6Cqri3OOYqyaKyfLxvz3eYahGSacx w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818700" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818700" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826807" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826807" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:56 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri , David Woodhouse , Lu Baolu Subject: [PATCH v7 06/24] iommu/vt-d: Clear the redirection hint when the destination mode is physical Date: Wed, 1 Mar 2023 15:47:35 -0800 Message-Id: <20230301234753.28582-7-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210559901921873?= X-GMAIL-MSGID: =?utf-8?q?1759210559901921873?= When the destination mode of an interrupt is physical APICID, the interrupt is delivered only to the single CPU of which the physical APICID is specified in the destination ID field. The redirection hint is meaningless. Furthermore, on certain processors, the IOMMU does not deliver the interrupt when the delivery mode is NMI, the redirection hint is set, and the destination mode is physical. Clearing the redirection hint ensures that the NMI is delivered. Cc: Andi Kleen Cc: David Woodhouse Cc: "Ravi V. Shankar" Cc: Lu Baolu Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Ashok Raj Reviewed-by: Lu Baolu Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/intel/irq_remapping.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c index 6d01fa078c36..2d68f94ae0ee 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1123,7 +1123,17 @@ static void prepare_irte(struct irte *irte, int vector, unsigned int dest) irte->dlvry_mode = apic->delivery_mode; irte->vector = vector; irte->dest_id = IRTE_DEST(dest); - irte->redir_hint = 1; + + /* + * When using the destination mode of physical APICID, only the + * processor specified in @dest receives the interrupt. The redirection + * hint is meaningless. + * + * Furthermore, on some processors, NMIs with physical delivery mode + * and the redirection hint set are delivered as regular interrupts + * or not delivered at all. + */ + irte->redir_hint = apic->dest_mode_logical; } struct irq_remap_ops intel_irq_remap_ops = { From patchwork Wed Mar 1 23:47:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63122 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930269wrd; Wed, 1 Mar 2023 15:38:59 -0800 (PST) X-Google-Smtp-Source: AK7set8QxQifxA1Nei3x664znR/EeyVJQmLEZ+jCn+vPLb6eqCb8+9YQeCXroinjNojlHaVFliFs X-Received: by 2002:a05:6a20:9388:b0:ce:521b:f542 with SMTP id x8-20020a056a20938800b000ce521bf542mr2882363pzh.17.1677713939627; Wed, 01 Mar 2023 15:38:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713939; cv=none; d=google.com; s=arc-20160816; b=jom/eolZnxMrn7fQseZKpejQ+Dh1JLPXIAh8O/JGmVeVIgNboyn0yvwoHlB6j2iHd3 SP392nRXqbRMfLIX8HcF+X4ove1SKsoLapoR46gSd2nNDXQB00TcY1ESVdL8NlQpWgQx d457AlPH3sp106ESfvXwzE0MRb0IeIq4RhEqHMocPE+2ZIhgyR6v7GkGrkTpXVeI9sum 203/Ah3uuQRIfIaUGNaftZRyol4hlH6qBrRx8j3Qqsz3TpmENkt52e5jpRwFBMtCzxEm ZS99OxMHpbyfgG3wslkfH1SgQR943Ol86ZDvvZvOfwvphgGLmrmmWF6Y/ZxTQ5nb5sWe VOrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=VB3yKuhy+lae8GnAC03BLYxR1wHM9LfY/DJKuaQfTQk=; b=wuIQyCpdCsIN5UP3lXo3V/gQI46fdxmC/0a1v+iJ6jkvgsgv59rUQp0gics949eKV5 v9mVrHkap9rw+a4+OWLfW6hh9PicFBXHUoXgkIyzZGRfZkXY6vxZrqVBxHYbb5g1lVKf DXFUv4DUwLQwVFyRrHxezk/Sw9vxwbQTXbg43nr7m935+UlFizQhcrqaCPKXvT0gum79 kngjggW3KB9hVvNsUbpzZkypZRXeYs67I2PYg3xgcxPiybOYPIJX8MkuWEmnB3o9QwlM XY7zwMQQzO3xzbOrKu+wsUK60C4QZmDyRoKnWqn4E1x/hKss1FTuWnU6cLrjM+khni/2 J5Jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=AKCGxFLa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w66-20020a636245000000b004b64bdc0c7dsi13511967pgb.82.2023.03.01.15.38.47; Wed, 01 Mar 2023 15:38:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=AKCGxFLa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229914AbjCAXi1 (ORCPT + 99 others); Wed, 1 Mar 2023 18:38:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229700AbjCAXiE (ORCPT ); Wed, 1 Mar 2023 18:38:04 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C60B83EA for ; Wed, 1 Mar 2023 15:38:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713883; x=1709249883; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Q7jaVeyNCbxgl24yqNhvX8ZvPUYdNFgf6LLRZb5QSGE=; b=AKCGxFLalYec2NWgmIaIktdU+xajIV3jWoz0Ga81tW3XT7RFQoTZ6ipV geeHT1gTqzhBhlWKqXTOI2BkSmV6kN0l0v7lN4YNBCw0TeqjhSyVxmPH/ zXDH6QsrP16hhF45cIW6dc6iFsbZnvYpnNubpsQilrd6rmeCRdSip9pTu tc0IIvztZxxo4c/JokOoBLj/+H+yJw57EGQvLoHU0ZCroOiyUDKcnLwi5 H8L+tDzjh99RfcQi0D6MFlIiIxPqlZUvIv9Zu2nbEIzREfSZXOwSn2qal p7ekWNF6evMsMcHxoZfjfGZVYOe32bv9wRKS7x1JNYqOSNsu5RZFRInRj A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818707" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818707" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826811" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826811" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:56 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri , David Woodhouse , Lu Baolu , x86@kernel.org Subject: [PATCH v7 07/24] iommu/vt-d: Rework prepare_irte() to support per-interrupt delivery mode Date: Wed, 1 Mar 2023 15:47:36 -0800 Message-Id: <20230301234753.28582-8-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210572019839650?= X-GMAIL-MSGID: =?utf-8?q?1759210572019839650?= struct irq_cfg::delivery_mode specifies the delivery mode of each interrupt separately. Configuring the delivery mode of an IRTE would require adding a third argument to prepare_irte(). Instead, take a pointer to the irq_cfg for which an IRTE is being configured. No functional changes. Cc: Andi Kleen Cc: David Woodhouse Cc: "Ravi V. Shankar" Cc: Lu Baolu Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Cc: x86@kernel.org Reviewed-by: Ashok Raj Reviewed-by: Tony Luck Reviewed-by: Lu Baolu Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Only change the signature of prepare_irte(). A separate patch changes the setting of the delivery_mode. Changes since v4: * None Changes since v3: * None Changes since v2: * None Changes since v1: * Introduced this patch. --- drivers/iommu/intel/irq_remapping.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c index 2d68f94ae0ee..1fe30c31fcbe 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1106,7 +1106,7 @@ void intel_irq_remap_add_device(struct dmar_pci_notify_info *info) dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev)); } -static void prepare_irte(struct irte *irte, int vector, unsigned int dest) +static void prepare_irte(struct irte *irte, struct irq_cfg *irq_cfg) { memset(irte, 0, sizeof(*irte)); @@ -1121,8 +1121,8 @@ static void prepare_irte(struct irte *irte, int vector, unsigned int dest) */ irte->trigger_mode = 0; irte->dlvry_mode = apic->delivery_mode; - irte->vector = vector; - irte->dest_id = IRTE_DEST(dest); + irte->vector = irq_cfg->vector; + irte->dest_id = IRTE_DEST(irq_cfg->dest_apicid); /* * When using the destination mode of physical APICID, only the @@ -1273,8 +1273,7 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, { struct irte *irte = &data->irte_entry; - prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid); - + prepare_irte(irte, irq_cfg); switch (info->type) { case X86_IRQ_ALLOC_TYPE_IOAPIC: /* Set source-id of interrupt request */ From patchwork Wed Mar 1 23:47:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63121 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930262wrd; Wed, 1 Mar 2023 15:38:58 -0800 (PST) X-Google-Smtp-Source: AK7set+INjB/uz5QUv23MMf2TIDkh1L+L00kUumFBYtOp70HIlXb/tc2sSzpJPhi+xmM5/xrR8vZ X-Received: by 2002:a17:90a:19e:b0:237:62f7:3106 with SMTP id 30-20020a17090a019e00b0023762f73106mr9470917pjc.17.1677713937955; Wed, 01 Mar 2023 15:38:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713937; cv=none; d=google.com; s=arc-20160816; b=pEWZNHeTdpYpRn+f2sIEtu3DrMXpJkqKG0vS+3rttk/yd6ilhsW4QN2wfhdUdcOsUF S1siX86f89FsRh8BMcVq7YH/kL7kDwHsS3c4ixOBlvMtbwfOzAg2xBBdGfCZqi6FvLVH 3J0s/dGBm2BWtH00Oe1JBU76sWW5KfxnxWzV1lJTj8SFYI5a1CK2Fphmp45lwRq5f05X 1HlBCvvNKcqZR73K9WhT4qnYldJEM9y8J8pRUjVKi9Tu7OtlH5EkwxGEFMrAH6fQPz9M s33Mf9P315KmF36sv+k2et+L2aJv2d2xPv1oI/eMt/fElxGTeZiNccBEEyHHlIDE+B1x Z9wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=uGrss+OmaJlj4AFy2vfdQ6HLwWP8VpVgVNMyHqWin8k=; b=ZXnzxBkTQb3ANuLzfZWOFsAYfy+6ZNt0Ipvu2Irsh+zTj3GhxEt8ATl5TlklGWRaGS RZQpZweId3zrcBFuxckFX55ysjl19RmwtqodDZ2animps1O3CpGQWGZIqUM7D8kNBFxo lb5IEwWG3gvNUY4boTUgDfaYS09M5OOarDXM8TF05jXOqeKlmSeWx/5OYcruSuSVeSkV tGjCODHr3KovzaW6ZlVCpk+I5PSMAAY0V5E7wUX/7AiFpvOdTUODiINsAFgENEwqNrXx xlnDcc4Ku9zh/OHdUMtUomRqmhwqOnZYrEtLVaxlvAgqH5OSG2BGJhD4TpddU6Ufb/+c ydwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BOpMBGGN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y3-20020a17090a8b0300b002296a8ff568si663597pjn.152.2023.03.01.15.38.44; Wed, 01 Mar 2023 15:38:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BOpMBGGN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229908AbjCAXiX (ORCPT + 99 others); Wed, 1 Mar 2023 18:38:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229708AbjCAXiE (ORCPT ); Wed, 1 Mar 2023 18:38:04 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C7BD86BB for ; Wed, 1 Mar 2023 15:38:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713883; x=1709249883; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=iAMY6btPT3LkFo8ii1+Ro1+SLEC/lk7JJlUCyqpnpJM=; b=BOpMBGGNMkAjry1BtH/w4hpprv1UV7IiYs5xh5/xYBHNcnFlprWhpev4 4V6Okvb51GPCOGvqr+A3P0KGlUutzb/EVsPlFG9WwXsN7Rst2ULJm9V3m KLn/O3gZFM3xtLRfeDWwQMds8xgWlJ3VfJUunOiE6DSeLAKcas8efieHd xIkL6ngwbxZckEkS3ehGQrkV9MQJ8BlWxUnH0KuJpkMJsVQUA6UdSnm+V YeUURNkBC+hmkqY5dgBZOdKEHBiCMSARUgGzP/5tzwj3jFwDQbQ8N4eq6 SOFkyW/XAoHDOjq19SAh7sVOGImC84rPPO5LlAwOQXhlUz7CjjwOsMt5s A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818714" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818714" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826817" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826817" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:57 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri , David Woodhouse , Lu Baolu Subject: [PATCH v7 08/24] iommu/vt-d: Set the IRTE delivery mode individually for each interrupt Date: Wed, 1 Mar 2023 15:47:37 -0800 Message-Id: <20230301234753.28582-9-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210570344753714?= X-GMAIL-MSGID: =?utf-8?q?1759210570344753714?= Use the mode specified in the provided interrupt hardware configuration data to set the delivery mode. Since most interrupts are configured to use the delivery mode of the APIC driver, there are no functional changes. The only exception are interrupts that do specify a different delivery mode. Cc: Andi Kleen Cc: David Woodhouse Cc: "Ravi V. Shankar" Cc: Lu Baolu Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Reviewed-by: Lu Baolu Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/intel/irq_remapping.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c index 1fe30c31fcbe..7b58406ea8d2 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1120,7 +1120,7 @@ static void prepare_irte(struct irte *irte, struct irq_cfg *irq_cfg) * irq migration in the presence of interrupt-remapping. */ irte->trigger_mode = 0; - irte->dlvry_mode = apic->delivery_mode; + irte->dlvry_mode = irq_cfg->delivery_mode; irte->vector = irq_cfg->vector; irte->dest_id = IRTE_DEST(irq_cfg->dest_apicid); From patchwork Wed Mar 1 23:47:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63123 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930285wrd; Wed, 1 Mar 2023 15:39:02 -0800 (PST) X-Google-Smtp-Source: AK7set8u3gWSi5WgAwTgRCxfzdlQVXt3x6y/3p8IROdBm4mnIMoqjLacdXaMlIigR3fINK1JEL7W X-Received: by 2002:a17:902:db02:b0:19c:bfe3:6f73 with SMTP id m2-20020a170902db0200b0019cbfe36f73mr140080plx.16.1677713942044; Wed, 01 Mar 2023 15:39:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713942; cv=none; d=google.com; s=arc-20160816; b=Adqc1wxBUpeEbj5EWG5qwZzUjlRdnJcqj9nJz/1XyRrM4h1reZ3SJWbNHcH3jtfycw AM+PzZ+mqv7rDioqmibjt3ZBPMrjMP0j9/tZxTibJnAyG3bJ3bY921aYOqqsK+lY+Q+A FN4BItp1bGOt163f+3HNRikhlBz9epKD3mow6+ps16uZ2ag7W12MJ+fL9itVBb47+KoD Xf6OSOXYFrEObIPGD/UIKb1wVcOokevKn//+usSAAEyowt+xVtXvwAq5rinI4M+vYDRD xvWLh8Ce5mXjSJuCMkgdrdaGnKcOM8VxqR9jxrBNEaaBRQcQxh2JKVXFRzl0B+wvF7Q6 f5+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=lBp533q6suGXBCk9rksYJ6NJlKIi3n/LVK7plY1NtGk=; b=ArIEyhqblexhC9APQ1ohLhwS6x/0u3aLzmndqRCoeUdyYNiUeD/oaW6qLn5sL1+9RU MkDlxZ6Zt2IYzVHF4XrGmWKjTK05VQpyNiIA5tjKUeWuvqzxdp+2WVU8xObbQLrI/Mo0 yknM9RPDVAYlLJPkMf976joW6vM+tt5zinQkpLkgOjJiiEgjtB6bLc3bVThf+++LU9EG WNlxny9roHnB/uqoSXlQYbTR+3J7aqfnuzivC4oJUDfGfZvfswdCNLFMByChzdDHGK4T syFTArygnEef+VSz07BzKDg4MRLDIIEfEn3SDYnhT3/Ju0LB+Z2zhx9w9BB9qT/bcJQL Rg1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=fu1OLrmX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri , Joerg Roedel , Suravee Suthikulpanit Subject: [PATCH v7 09/24] iommu/amd: Expose [set|get]_dev_entry_bit() Date: Wed, 1 Mar 2023 15:47:38 -0800 Message-Id: <20230301234753.28582-10-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210574758248699?= X-GMAIL-MSGID: =?utf-8?q?1759210574758248699?= If an interrupt is allocated with NMI as delivery mode, the Device Table Entry needs to be modified accordingly in irq_remapping_alloc(). No functional changes. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Joerg Roedel Cc: Suravee Suthikulpanit Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/amd/amd_iommu.h | 3 +++ drivers/iommu/amd/init.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index c160a332ce33..b9b87a8cd48e 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -141,4 +141,7 @@ extern u64 amd_iommu_efr; extern u64 amd_iommu_efr2; extern bool amd_iommu_snp_en; + +extern void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit); +extern int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit); #endif diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 19a46b9f7357..559a9ecb785f 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -999,7 +999,7 @@ static void __set_dev_entry_bit(struct dev_table_entry *dev_table, dev_table[devid].data[i] |= (1UL << _bit); } -static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) +void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) { struct dev_table_entry *dev_table = get_dev_table(iommu); @@ -1015,7 +1015,7 @@ static int __get_dev_entry_bit(struct dev_table_entry *dev_table, return (dev_table[devid].data[i] & (1UL << _bit)) >> _bit; } -static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) +int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) { struct dev_table_entry *dev_table = get_dev_table(iommu); From patchwork Wed Mar 1 23:47:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63128 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930405wrd; Wed, 1 Mar 2023 15:39:20 -0800 (PST) X-Google-Smtp-Source: AK7set+ANrTGaSlxLSePGkqvL3G8/ITqoFRzgMPRfwwvWL3+lg8JvrsPKAVeeWAyN9B9PITHZEe4 X-Received: by 2002:a17:902:a513:b0:19d:6f7:70d2 with SMTP id s19-20020a170902a51300b0019d06f770d2mr6350347plq.50.1677713959844; Wed, 01 Mar 2023 15:39:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713959; cv=none; d=google.com; s=arc-20160816; b=FsS3prE2hTLkp0o9cHSIlV0YoLS84NsG8mFTrhB+D1AS7bWi69NTJ/Qw03oVznKbTA Nb7ZAQhf8GF2r3qFd3wmC9NoInXNbhG/CqvBnwj+Lk43sQVNfHST6JH9w9tpbDIb6ZfS URYVNqfWaCfFb+dYhfPfa7j7CaNFcoNaKRvGfHGoslgV71DRaA5+cC8nNQ9BqQ4WT5qg XB5kkiqBxrtGPKfPoZ5PglSf/TYr2+mQYGJbtixZ/yEaswVYvIUq01E1YIvYg/VvW786 8aXFEbZq/lvDC9dmFxCDHd1h8y6mPpxUtOI8ohRIYeKXZML+MO5wbKq7ctfAADiZVd1w qIbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=93Rrtn/KuWMPbBsukAVre02DsY250DNQUrBaIOXFk6A=; b=toEC4IEC5ywbQH9Ru16x7+IcJi1dW8dUbENwxtGuiUJrj/4P9mE2IpI59c7Hal1jZJ nuxjBqjvBy7faJy0ZXozu9pjLiirTrfQmSkCuvNHhXl/+32lZIZRko9UwQU5dH++nDvv rlb3bG3k6aN+7EwxKO9tbJe5GPc9UDiNEYxmRSWAqnL0o5j8rxH63wffuWoWvkLmCpKq by+xDYi0BUuOEcZ6z9C/x/JYIF5OmCA/IV9fduQOTq7OwNdL0GUFO+J/ZSelX534wuN4 KSzEI28J93Y8CwTHJ9LNeSxoUAPMfRhoUVIWZx9EVGK4JvhVmNzm9iVGtbVzuxEg1NG9 6tQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=A+xZZ4dO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q3-20020a170902b10300b0019d20ff7e21si7952952plr.47.2023.03.01.15.39.05; Wed, 01 Mar 2023 15:39:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=A+xZZ4dO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229955AbjCAXip (ORCPT + 99 others); Wed, 1 Mar 2023 18:38:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229698AbjCAXiN (ORCPT ); Wed, 1 Mar 2023 18:38:13 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 754B93B3CB for ; Wed, 1 Mar 2023 15:38:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713885; x=1709249885; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=btyWt/qyY31uspGHtLUS5h0GneCtSdCDc61owotTsK4=; b=A+xZZ4dONmyFBxhBz8CvYHZFjQ++OJeOSRNFyyrYvSMYJoIgXM8D/cVy 5uoZtGkufpxe+HiXVhLLkpNY0cIUwDeHD8MHPtqGxmmaSyyhK0ws92JEZ AxIrm/JIV0JJPvSRBpNSj5Wh0VVSDSFZskXCKjZJzP94pLQ1QBPDmEyit mqXDEW5l9eqwbp19C20g43nXlQU4AJCns9uOPia1v+Y/qIDimIHCfyuLW W0d9QanCcfAu3yDzRx+PG32V0k4naM7t0HPnkUcSYw5WhchB1rryrm/1P xvpUK9B4toDkbtuk32Dp4FmIpssBNT6AkqYsKQYbBgZiGbA64viOx3yDl A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818728" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818728" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826826" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826826" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:57 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri , Joerg Roedel , Suravee Suthikulpanit Subject: [PATCH v7 10/24] iommu/amd: Enable NMIPass when allocating an NMI Date: Wed, 1 Mar 2023 15:47:39 -0800 Message-Id: <20230301234753.28582-11-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210593216158156?= X-GMAIL-MSGID: =?utf-8?q?1759210593216158156?= As per the AMD I/O Virtualization Technology (IOMMU) Specification, the AMD IOMMU only remaps fixed and arbitrated MSIs. NMIs are controlled by the NMIPass bit of a Device Table Entry. When set, the IOMMU passes through NMI interrupt messages unmapped. Otherwise, they are aborted. Also, Section 2.2.5 Table 19 states that the IOMMU will abort NMIs when the destination mode is logical. Update the NMIPass setting of a device's DTE when an NMI is being allocated. Only do so when the destination mode of the APIC is not logical. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Joerg Roedel Cc: Suravee Suthikulpanit Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * Removed check for nr_irqs in irq_remapping_alloc(). Allocation had been rejected already in the root domain. (Thomas) Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/amd/iommu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 5a505ba5467e..9bf71e7335f5 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3299,6 +3299,10 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI) return -EINVAL; + /* NMIs are aborted when the destination mode is logical. */ + if (info->flags & X86_IRQ_ALLOC_AS_NMI && apic->dest_mode_logical) + return -EPERM; + sbdf = get_devid(info); if (sbdf < 0) return -EINVAL; @@ -3348,6 +3352,13 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, goto out_free_parent; } + if (info->flags & X86_IRQ_ALLOC_AS_NMI) { + if (!get_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS)) { + set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS); + iommu_flush_dte(iommu, devid); + } + } + for (i = 0; i < nr_irqs; i++) { irq_data = irq_domain_get_irq_data(domain, virq + i); cfg = irq_data ? irqd_cfg(irq_data) : NULL; From patchwork Wed Mar 1 23:47:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63124 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930302wrd; Wed, 1 Mar 2023 15:39:04 -0800 (PST) X-Google-Smtp-Source: AK7set9nEDbpv5wKpiorhs/gkYKLua6os7e03pD+RM85FAzNmSU2wj7sUXPQnGSsM8OYSSSjeQ7w X-Received: by 2002:a62:1ad2:0:b0:5a8:51a3:7f69 with SMTP id a201-20020a621ad2000000b005a851a37f69mr244496pfa.2.1677713944545; Wed, 01 Mar 2023 15:39:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713944; cv=none; d=google.com; s=arc-20160816; b=yvuJ/qUjPYD2DSGSjTEizM5J27DU7fqWMrbALfsVSrcu2a1wT2jnsUzYOlr7DGVNcf QDyPq5ErN73r1VKAavfCc3VrQNRY578SRM0iL2H8sVt8vZ4sKh7J3LkNtrJEtXWt6jjS FRd6GPhoJq06yvj7rrl55V7k+gTeEdv9WAQVqH9LENDamnaI6LkGdnbgmHnd9PdlczmQ h/dTHCzjkKiUku388vFWpO9FoiAL/5murDtoZ+qL8u32lJx/qS/mg2VsbDc4162uQCgi kEZZOcGbh9bjeoEyBIMHZ7WdYFtPv72eyqTuJ6i9MjFL/EM8M7p7s28p4fNfeWyqKTio NwEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Ts1Iyg0xR+71gSeHRyflUlNbnQ02Q9MxCb5qu2EH6qk=; b=CIzgUUEi/6/jgfMkRT4asF84Z24mt+WiSwpTxWc66RCfiiMAjifY7HH+ecMUSn2lbG Fs8abTkp7phXK+2JbFPG7cw8ecRHHYJlgS4BVd6CtxmRdZj4B8Ck4oabCyjRyzs5951d KhBBWXxNpmpH+yHDh1e9XeYJPtymFsFEzqDzkUiIzcc1rG9rTr1zKY379x4sTPKTV2GM HwDGF+9KwUdxs92dJFXeIs5apBmeIuK4a9JT2GPYrhaWUVLcqYxdcCsX87AYNGEmaIoI CnoRev467KPrVz36FDfVlw+tqmjuAMTuWml4xkP0l6lhknTktRDzwNFkSb7DawD3GGcR jLKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CJBa25oG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri , Joerg Roedel , Suravee Suthikulpanit Subject: [PATCH v7 11/24] iommu/amd: Compose MSI messages for NMIs in non-IR format Date: Wed, 1 Mar 2023 15:47:40 -0800 Message-Id: <20230301234753.28582-12-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210576717236744?= X-GMAIL-MSGID: =?utf-8?q?1759210576717236744?= If NMIPass is enabled in a Device Table Entry, the IOMMU lets NMI interrupt messages pass through unmapped. The contents of the MSI message, not an IRTE, determine how and where the NMI is delivered. The IOMMU driver owns the MSI message of the NMI. Compose it using the non- interrupt-remapping format. Let descendant irqchips write the composed message. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Joerg Roedel Cc: Suravee Suthikulpanit Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * Reworded changelog to remove acronyms. (Thomas) * Removed confusing comment regarding interrupt vector cleanup after changing the affinity of an interrupt. (Thomas) Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- drivers/iommu/amd/iommu.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 9bf71e7335f5..c6b0c365bf33 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3254,7 +3254,16 @@ static void irq_remapping_prepare_irte(struct amd_ir_data *data, case X86_IRQ_ALLOC_TYPE_HPET: case X86_IRQ_ALLOC_TYPE_PCI_MSI: case X86_IRQ_ALLOC_TYPE_PCI_MSIX: - fill_msi_msg(&data->msi_entry, irte_info->index); + if (irq_cfg->delivery_mode == APIC_DELIVERY_MODE_NMI) + /* + * The IOMMU lets NMIs pass through unmapped. Thus, the + * MSI message, not the IRTE, determines the interrupt + * configuration. Since we own the MSI message, + * compose it. + */ + __irq_msi_compose_msg(irq_cfg, &data->msi_entry, true); + else + fill_msi_msg(&data->msi_entry, irte_info->index); break; default: @@ -3643,6 +3652,15 @@ static int amd_ir_set_affinity(struct irq_data *data, */ send_cleanup_vector(cfg); + /* + * When the delivery mode of an interrupt is NMI, the IOMMU lets the NMI + * interrupt messages pass through unmapped. Changes in the destination + * must be reflected in the MSI message, not the IRTE. Descendant + * irqchips must set the affinity and write the MSI message. + */ + if (cfg->delivery_mode == APIC_DELIVERY_MODE_NMI) + return IRQ_SET_MASK_OK; + return IRQ_SET_MASK_OK_DONE; } From patchwork Wed Mar 1 23:47:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63125 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930327wrd; Wed, 1 Mar 2023 15:39:09 -0800 (PST) X-Google-Smtp-Source: AK7set/Kx669lrlcZVq+5mXAHhjW7E4zWXpk4QMr5367jSyCFmlcxdOHBrzxWWhaKIKxs5kHo2BL X-Received: by 2002:a17:902:dac8:b0:19c:fc41:2dfd with SMTP id q8-20020a170902dac800b0019cfc412dfdmr10033107plx.29.1677713949119; Wed, 01 Mar 2023 15:39:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713949; cv=none; d=google.com; s=arc-20160816; b=JaZEcRBRQr1xZaSP9FVknN5xA8I7PdzoSUS93z49YKJQG+3FbB7n1MDriNf86qkcdt +CuwAiqiX0SdX7/B2jPQhD2npHzSuZzgvenZOe24imH7CBS5DLQEYKR2KRWnSeu4hwXU ixF8VvJpZ893ustB3AGQCLhn1DYBmJnev4SHumLUPChKgqLyJCkb1kPt6ohkokpSVsAW sQVn2tpfgr/oJQmMZXUuTcvLxhsSAo7JvShfs/IYlAEa8NYPTxCk4kz4oHV8WXyH6zM4 5g7TCJCYD/npHUm1/Rs++vw0iZW8g902whGFGQmSDpJA19Vn+I7sosG1cCBV9iRHQwma yjbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Pdj8f3+GWrCagv8Avh4BWRKip+9EH7F5wb1lTlQUasY=; b=dwjQ33gnjtSTWWKERa3qNrY/Mkr5Az5cfM7ljwehj4venuRVGYRjpmmwxJHD+HX9XH w54DvqmbSZbl2Az/kBai4vj19CCKch8hU4b0BxzLBkKLSyT+FoeUpuOBd0jQJ2jX6EzF HsrW+XWMFYGYQcQScm0aRhyPVrJDz3tvcuk15gWLMcLC5BlfBEkWqqE4Uik1BUbNxHV6 yressOuAgBGloLYWmV/NKPeZqp45Dao7gcxJWUuikxS5mN+nPB1eYd6CKTNrm/eWnhQ8 /6m/r5wel+VvPPOXc/U9L8ThkI9GydUmYJG5VkYrMNvbpG9aCILSVvuIV+J9Ah6k95Tg /4XQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=jtr3N3+o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 12/24] x86/hpet: Expose hpet_writel() in header Date: Wed, 1 Mar 2023 15:47:41 -0800 Message-Id: <20230301234753.28582-13-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210581518283417?= X-GMAIL-MSGID: =?utf-8?q?1759210581518283417?= In order to allow hpet_writel() to be used by other components (e.g., the HPET-based hardlockup detector), expose it in the HPET header file. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * None Changes since v4: * Dropped exposing hpet_readq() as it is not needed. Changes since v3: * None Changes since v2: * None Changes since v1: * None --- arch/x86/include/asm/hpet.h | 1 + arch/x86/kernel/hpet.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index ab9f3dd87c80..be9848f0883f 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -72,6 +72,7 @@ extern int is_hpet_enabled(void); extern int hpet_enable(void); extern void hpet_disable(void); extern unsigned int hpet_readl(unsigned int a); +extern void hpet_writel(unsigned int d, unsigned int a); extern void force_hpet_resume(void); #ifdef CONFIG_HPET_EMULATE_RTC diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index c8eb1ac5125a..8303fb1b63a9 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -79,7 +79,7 @@ inline unsigned int hpet_readl(unsigned int a) return readl(hpet_virt_address + a); } -static inline void hpet_writel(unsigned int d, unsigned int a) +inline void hpet_writel(unsigned int d, unsigned int a) { writel(d, hpet_virt_address + a); } From patchwork Wed Mar 1 23:47:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63126 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930354wrd; Wed, 1 Mar 2023 15:39:12 -0800 (PST) X-Google-Smtp-Source: AK7set/3rlXjMvPotBISrkOPJRE6dNv27B14Ds8896/JDmEBXDOKntNfvOp1IKliB3kT0WYWtbCj X-Received: by 2002:a17:902:e5c9:b0:199:25d1:e559 with SMTP id u9-20020a170902e5c900b0019925d1e559mr10134114plf.0.1677713951976; Wed, 01 Mar 2023 15:39:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713951; cv=none; d=google.com; s=arc-20160816; b=Cd0QHxRf50e2UfETinW6CtDTtdNfMkOs89wcLUW6r1tRWOCH1ADvvgHYzl1r9tT/ui hMcyf/O8uumRbUT/CUsRDP331nUiJIMaSfBx8D0W3kOocSrnZPGaufL/b77d8uf+2DmA Ma6xY5YbDyuDy6BGjEFLeM3FHMC0LilCwJEekEw4jCme9QLJFipUvPnfq7DrfE0fal4q gnAwo9xNl4W+nIKeLK+/C186XaEt84S6KFtSwmejEj8BMWFffp64tyvzYvOI4h9gXuEv d1ecNPFrfkCU9FYNP5QEzHuYJUkpeCNwvcu7G0RX3hu34d2Ig3H8MYHshPP8Rr2CCjkI TqCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=yAw4ctuMr94dUEk3wt0DYMZlvkQyCVaAKXtAd0NfC4M=; b=XaChKhyRY2ywvY8aniLrS02V6PNhusUzC5Y+Bumdv4ya9Lb2VEZhidV6en8Ui0Hlqs L7OPBYOKYDnMc7/8OuFDlnQZcBAf1Hz9yMA9mZSrjwz+GUip07SEOs/rkDdNNgcfqKqX A1Ufd0NY3tF9ftBcwgFLQ94LHwGXFSdAgWR6fvSTa2iwbMt68J+bW/dqfIsDMsHI2a1e z1pZpCMOA2SE5gLarObhJb/iYMvM8PvNEKthYocn4lDBXfyZHb0eiW1AC/U+Tt6O+/Cw 1un4UUkBAn5YS/ZPZ0bYlNe+4/MGq2uXHABuDp9QzrEumjTC76eExqn8ykH+rDxHBQ/E JgaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ZKM0+u4B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 13/24] x86/hpet: Add helper function hpet_set_comparator_periodic() Date: Wed, 1 Mar 2023 15:47:42 -0800 Message-Id: <20230301234753.28582-14-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210585148582673?= X-GMAIL-MSGID: =?utf-8?q?1759210585148582673?= Programming an HPET channel in periodic mode involves several steps. Besides the HPET clocksource, the HPET-based hardlockup detector may need to program its HPET channel in periodic mode. To avoid code duplication, wrap the programming of the HPET timer in a helper function. Cc: Andi Kleen Cc: Tony Luck Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Originally-by: Suravee Suthikulpanit Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- When programming the HPET channel in periodic mode, a udelay(1) between the two successive writes to HPET_Tn_CMP was introduced in commit e9e2cdb41241 ("[PATCH] clockevents: i386 drivers"). The commit message does not give any reason for such delay. The hardware specification does not seem to require it. The refactoring in this patch simply carries such delay. --- Changes since v6: * Reworded the commit message for clarity. Changes since v5: * None Changes since v4: * Implement function only for periodic mode. This removed extra logic to to use a non-zero period value as a proxy for periodic mode programming. (Thomas) * Added a comment on the history of the udelay() when programming the channel in periodic mode. (Ashok) Changes since v3: * Added back a missing hpet_writel() for time configuration. Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/hpet.h | 2 ++ arch/x86/kernel/hpet.c | 49 ++++++++++++++++++++++++++++--------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index be9848f0883f..486e001413c7 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -74,6 +74,8 @@ extern void hpet_disable(void); extern unsigned int hpet_readl(unsigned int a); extern void hpet_writel(unsigned int d, unsigned int a); extern void force_hpet_resume(void); +extern void hpet_set_comparator_periodic(int channel, unsigned int cmp, + unsigned int period); #ifdef CONFIG_HPET_EMULATE_RTC diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 8303fb1b63a9..3563849c2290 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -294,6 +294,39 @@ static void hpet_enable_legacy_int(void) hpet_legacy_int_enabled = true; } +/** + * hpet_set_comparator_periodic() - Helper function to set periodic channel + * @channel: The HPET channel + * @cmp: The value to be written to the comparator/accumulator + * @period: Number of ticks per period + * + * Helper function for updating comparator, accumulator and period values. + * + * In periodic mode, HPET needs HPET_TN_SETVAL to be set before writing + * to the Tn_CMP to update the accumulator. Then, HPET needs a second + * write (with HPET_TN_SETVAL cleared) to Tn_CMP to set the period. + * The HPET_TN_SETVAL bit is automatically cleared after the first write. + * + * This function takes a 1 microsecond delay. However, this function is supposed + * to be called only once (or when reprogramming the timer) as it deals with a + * periodic timer channel. + * + * See the following documents: + * - Intel IA-PC HPET (High Precision Event Timers) Specification + * - AMD-8111 HyperTransport I/O Hub Data Sheet, Publication # 24674 + */ +void hpet_set_comparator_periodic(int channel, unsigned int cmp, unsigned int period) +{ + unsigned int v = hpet_readl(HPET_Tn_CFG(channel)); + + hpet_writel(v | HPET_TN_SETVAL, HPET_Tn_CFG(channel)); + + hpet_writel(cmp, HPET_Tn_CMP(channel)); + + udelay(1); + hpet_writel(period, HPET_Tn_CMP(channel)); +} + static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt) { unsigned int channel = clockevent_to_channel(evt)->num; @@ -306,19 +339,11 @@ static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt) now = hpet_readl(HPET_COUNTER); cmp = now + (unsigned int)delta; cfg = hpet_readl(HPET_Tn_CFG(channel)); - cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | - HPET_TN_32BIT; + cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_32BIT; hpet_writel(cfg, HPET_Tn_CFG(channel)); - hpet_writel(cmp, HPET_Tn_CMP(channel)); - udelay(1); - /* - * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL - * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL - * bit is automatically cleared after the first write. - * (See AMD-8111 HyperTransport I/O Hub Data Sheet, - * Publication # 24674) - */ - hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel)); + + hpet_set_comparator_periodic(channel, cmp, (unsigned int)delta); + hpet_start_counter(); hpet_print_config(); From patchwork Wed Mar 1 23:47:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63127 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930384wrd; Wed, 1 Mar 2023 15:39:16 -0800 (PST) X-Google-Smtp-Source: AK7set9+2FlT3UIHtATeyHrtZNvsI2QcvwOAoIpPPI+M4VfEh7q3t/yJRPcL29cOCNfUM9Z04+Lc X-Received: by 2002:a17:90a:4583:b0:234:248c:984d with SMTP id v3-20020a17090a458300b00234248c984dmr9185454pjg.26.1677713955757; Wed, 01 Mar 2023 15:39:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713955; cv=none; d=google.com; s=arc-20160816; b=YOpwAL4FyIJIhQC2nJJ+skXUsqbP2bJHjxzqLbu+JFdqFXh/wpGqFuyCSbwwZNG4kO 3v1apLCQBySR67gHo9ssvoMr0H2j9dI/KRpUxMFXDNrUJCXIqfpBHLdII4PBZAO0jdmI 7+55tUYiz02eYcHz6JFnG518MOE52NBQxidDY+AatJ0WeoLhNWpPHWo9JF21+scRE75H P7Un9KYDP/NlQvLvJVjBnam0M5AqZDUP8uc7KZKXlgK4xcN8P94qvY6zXLhzEHs1l8ek aYFQ5gXlW4bGa4qGRVoaJnsPWtHgOIA/P011JIVDd2gWd9ScVnpayayVS2eCcQq5W1ld HFPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Dr6p4EyN89EPFvK3kEhKdM4VuX/BzXSXg27x5GTp1HQ=; b=DgJjWJFgxtKPAXnpSmQU1lbs8sdU5S54H8aSTZCdvSakv2LorRyG5kS6QytmrqZDOT 6OXjBEgA1GzTzefOmEsa9NQGZkHvaK5JN3KONR+Ylj6J5CDvyZP8nK2ecxazzAeggkiQ tTD5CtbO3nB/d0PHtjV0+zs4guS/2+F26XoA1Y77n6lUoCxiSFv+fGyn1fohOmRXi59a 2GUgHky+b5Y3JJuOtfX3JcF/81PMgzRbhtXq9JgukDWcNLvtmQL+oNJnqTW3FU72SqpS pM8R9yme7wEhPjd+rvkWatfQdrdEUuIyNkYU84jqi8FqUK8RcqK+vmp4FYz75rEzkczC 3JWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LL5Fuxxn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 14/24] x86/hpet: Prepare IRQ assignments to use the X86_ALLOC_AS_NMI flag Date: Wed, 1 Mar 2023 15:47:43 -0800 Message-Id: <20230301234753.28582-15-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210588790570886?= X-GMAIL-MSGID: =?utf-8?q?1759210588790570886?= The flag X86_ALLOC_AS_NMI indicates that the interrupts to be allocated in an interrupt domain need to be configured as NMIs. Add an as_nmi argument to hpet_assign_irq(). The HPET clock events do not need NMIs, but the HPET hardlockup detector does. Cc: Andi Kleen Cc: "Ravi V. Shankar" Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch. Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- arch/x86/kernel/hpet.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 3563849c2290..f42ce3fc4528 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -618,7 +618,7 @@ static inline int hpet_dev_id(struct irq_domain *domain) } static int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc, - int dev_num) + int dev_num, bool as_nmi) { struct irq_alloc_info info; @@ -627,6 +627,8 @@ static int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc, info.data = hc; info.devid = hpet_dev_id(domain); info.hwirq = dev_num; + if (as_nmi) + info.flags |= X86_IRQ_ALLOC_AS_NMI; return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); } @@ -755,7 +757,7 @@ static void __init hpet_select_clockevents(void) sprintf(hc->name, "hpet%d", i); - irq = hpet_assign_irq(hpet_domain, hc, hc->num); + irq = hpet_assign_irq(hpet_domain, hc, hc->num, false); if (irq <= 0) continue; From patchwork Wed Mar 1 23:47:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63129 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930466wrd; Wed, 1 Mar 2023 15:39:27 -0800 (PST) X-Google-Smtp-Source: AK7set/KBI8MR2AjQxV0Hu1sDcyk2z64K0Z8Ajw5it7gmSKxtDmA0Ute48mdnxnF7AQvxMT5RwYp X-Received: by 2002:a05:6a20:4923:b0:cc:f47b:9a with SMTP id ft35-20020a056a20492300b000ccf47b009amr7722184pzb.1.1677713967137; Wed, 01 Mar 2023 15:39:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713967; cv=none; d=google.com; s=arc-20160816; b=AYj54YSaMxzWQmAwlcgykC6+znExpaaTFF2nbLCTmv3t01PjUEXiMTl08ul4NPJOkG jvXb6oRV7am9fMYX4f04pq2wXSHVnf0ZXGDv3wJZWCEhILSNkoOBHQeG8CFrTGDaq5fA 4nGlwdLs6RC6du5qNT+bO9QVrhwdEmvwOHxsB4P0nC46FY2uOMRu4VMNI3TGJR/2fiTN eWT7Q50WWQcnXVL3ZpFJgqUxmvVKVs4TZlBnPjIMzVgiVClNuE/6yFpCvYFATcDBzxga nPwd/IFm2Prr5JsE/JbGW0R/W696vm5DCSVqAEcMMbTUdSfhOG9TwBTqah3qXffqJNWt LaKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=1fa+w9a4NMxQkcLWmF94+6XZQabPLGLzpiruf3eBtBU=; b=EcQ4p9B+okV+/3nXxJaSUblDPRxecdG1GJfcTPjSXk+HZqfnJeDlW/JtjRTosyaFK1 OYM/RzhyOGAk2G6NX32yQ04wsWvFubIzoe71SvreDX36eaSFBENg3SlsYNaLuvSh089W T/gYf7hVOC7lokatKQMyU/0GImyDgspSyMrs69lmSq0UOjm7Z6WBtaHWbanHqIH0aPQ2 nQ0BUA5w7dd3QcAf9vLncKhPD3d4UG93dtqOvmCsN5nFtoplCloWLq+PVamy/mFbDzyx pAzXo2TCYB+5nS+S9eRJuoyG+gy62UmdAgysK9WWlHZGddM7/znisV2PyfesT8QalDiV X0LQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=h7ztLmvO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s8-20020a63af48000000b00502eada87f8si13979306pgo.19.2023.03.01.15.39.09; Wed, 01 Mar 2023 15:39:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=h7ztLmvO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229972AbjCAXis (ORCPT + 99 others); Wed, 1 Mar 2023 18:38:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229774AbjCAXiN (ORCPT ); Wed, 1 Mar 2023 18:38:13 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EC6A2A172 for ; Wed, 1 Mar 2023 15:38:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713886; x=1709249886; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+mf2a1s8IDXo9f4g6wZDARhxFh01FpRy/WRIkdf67AA=; b=h7ztLmvOsObfP04Q0XHIGDbvC44K4oMtpmkJu1mY0iyVzZymnQm5vusb PZ1anYW0j85gMrVI2TvixdO/9ujHsxwucFWTPPOcl6Xr58DNIYPuinOPs E6ZFv6cjTyHbrVmYpBoGZbMlGGIr5WPoiTrViA7Kuua1gNnwm8jfbdArm i2Wcx/0WJKEnQVfun9MCcojT1fsval0vWFH3csHWCAAcBF+HXmSPZD2/+ nMx9MdKB0VnUjI0FtHHk9g3r/URlc+3AiMRAb5qNB26bSALZclRUIpkrg OArGl1fy73/PVItsrHGonP6NCAtVks3izMt/PXQks1eHhMlPQqyPdTWfo w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818759" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818759" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826845" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826845" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:58 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 15/24] x86/hpet: Reserve an HPET channel for the hardlockup detector Date: Wed, 1 Mar 2023 15:47:44 -0800 Message-Id: <20230301234753.28582-16-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210600779441440?= X-GMAIL-MSGID: =?utf-8?q?1759210600779441440?= Create a new HPET_MODE_NMI_WATCHDOG mode category to reserve an HPET channel for the hard lockup detector. Only reserve the channel if the HPET frequency is sufficiently low to allow 32-bit register accesses and if Front Side BUS interrupt delivery (i.e., MSI interrupts) is supported. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Reworded the commit message for clarity. * Removed pointless global variable hld_data. Changes since v5: * Added a check for the allowed maximum frequency of the HPET. * Added hpet_hld_free_timer() to properly free the reserved HPET channel if the initialization is not completed. * Call hpet_assign_irq() with as_nmi = true. * Relocated declarations of functions and data structures of the detector to not depend on CONFIG_HPET_TIMER. Changes since v4: * Reworked timer reservation to use Thomas' rework on HPET channel management. * Removed hard-coded channel number for the hardlockup detector. * Provided more details on the sequence of HPET channel reservations. (Thomas Gleixner) * Only reserve a channel for the hardlockup detector if enabled via kernel command line. The function reserving the channel is called from hardlockup detector. (Thomas Gleixner) * Shorten the name of hpet_hardlockup_detector_get_timer() to hpet_hld_get_timer(). (Andi) * Simplify error handling when a channel is not found. (Tony) Changes since v3: * None Changes since v2: * None Changes since v1: * None --- arch/x86/include/asm/hpet.h | 22 ++++++++ arch/x86/kernel/hpet.c | 100 ++++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index 486e001413c7..5762bd0169a1 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -103,4 +103,26 @@ static inline int is_hpet_enabled(void) { return 0; } #define default_setup_hpet_msi NULL #endif + +#ifdef CONFIG_X86_HARDLOCKUP_DETECTOR_HPET +/** + * struct hpet_hld_data - Data needed to operate the detector + * @has_periodic: The HPET channel supports periodic mode + * @channel: HPET channel assigned to the detector + * @channe_priv: Private data of the assigned channel + * @ticks_per_second: Frequency of the HPET timer + * @irq: IRQ number assigned to the HPET channel + */ +struct hpet_hld_data { + bool has_periodic; + u32 channel; + struct hpet_channel *channel_priv; + u64 ticks_per_second; + int irq; +}; + +extern struct hpet_hld_data *hpet_hld_get_timer(void); +extern void hpet_hld_free_timer(struct hpet_hld_data *hdata); +#endif /* CONFIG_X86_HARDLOCKUP_DETECTOR_HPET */ + #endif /* _ASM_X86_HPET_H */ diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index f42ce3fc4528..97570426f324 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -20,6 +20,7 @@ enum hpet_mode { HPET_MODE_LEGACY, HPET_MODE_CLOCKEVT, HPET_MODE_DEVICE, + HPET_MODE_NMI_WATCHDOG, }; struct hpet_channel { @@ -216,6 +217,7 @@ static void __init hpet_reserve_platform_timers(void) break; case HPET_MODE_CLOCKEVT: case HPET_MODE_LEGACY: + case HPET_MODE_NMI_WATCHDOG: hpet_reserve_timer(&hd, hc->num); break; } @@ -1498,3 +1500,101 @@ irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) } EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); #endif + +#ifdef CONFIG_X86_HARDLOCKUP_DETECTOR_HPET + +/* + * We program the channel in 32-bit mode to reduce the number of register + * accesses. The maximum value of watch_thresh is 60 seconds. The HPET counter + * should not wrap around more frequently than that: its frequency must be less + * than 71.582788 MHz. For safety, limit the frequency to 85% of the maximum + * permitted frequency. + * + * The frequency of the HPET in most systems in the field is less than 24MHz. + */ +#define HPET_HLD_MAX_FREQ 60845000ULL + +/** + * hpet_hld_free_timer - Free the reserved channel for the hardlockup detector + * @hdata: Data structure representing the reserved channel. + * + * Returns: none + */ +void hpet_hld_free_timer(struct hpet_hld_data *hld_data) +{ + hld_data->channel_priv->mode = HPET_MODE_UNUSED; + hld_data->channel_priv->in_use = 0; + kfree(hld_data); +} + +/** + * hpet_hld_get_timer - Get an HPET channel for the hardlockup detector + * + * Reserve an HPET channel if available, supports FSB mode, and has sufficiently + * low frequency. This function is called by the hardlockup detector if enabled + * in the kernel command line. + * + * Returns: a pointer with the properties of the reserved HPET channel. + */ +struct hpet_hld_data *hpet_hld_get_timer(void) +{ + struct hpet_channel *hc = hpet_base.channels; + struct hpet_hld_data *hld_data; + int i, irq; + + if (hpet_freq > HPET_HLD_MAX_FREQ) + return NULL; + + for (i = 0; i < hpet_base.nr_channels; i++) { + hc = hpet_base.channels + i; + + /* + * Associate the first unused channel to the hardlockup + * detector. Bailout if we cannot find one. This may happen if + * the HPET clocksource has taken all the timers. The HPET + * driver (/dev/hpet) has not taken any channels at this point. + */ + if (hc->mode == HPET_MODE_UNUSED) + break; + } + + if (i == hpet_base.nr_channels) + return NULL; + + if (!(hc->boot_cfg & HPET_TN_FSB_CAP)) + return NULL; + + hld_data = kzalloc(sizeof(*hld_data), GFP_KERNEL); + if (!hld_data) + return NULL; + + hc->mode = HPET_MODE_NMI_WATCHDOG; + hc->in_use = 1; + hld_data->channel_priv = hc; + + if (hc->boot_cfg & HPET_TN_PERIODIC_CAP) + hld_data->has_periodic = true; + + if (!hpet_domain) + hpet_domain = hpet_create_irq_domain(hpet_blockid); + + if (!hpet_domain) + goto err; + + /* Assign an IRQ with NMI delivery mode. */ + irq = hpet_assign_irq(hpet_domain, hc, hc->num, true); + if (irq <= 0) + goto err; + + hc->irq = irq; + hld_data->irq = irq; + hld_data->channel = i; + hld_data->ticks_per_second = hpet_freq; + + return hld_data; + +err: + hpet_hld_free_timer(hld_data); + return NULL; +} +#endif /* CONFIG_X86_HARDLOCKUP_DETECTOR_HPET */ From patchwork Wed Mar 1 23:47:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63131 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3930521wrd; Wed, 1 Mar 2023 15:39:33 -0800 (PST) X-Google-Smtp-Source: AK7set/4c0oE53e7H/U2kVE7j3YF29msiVGFoDfo/kmLVG2K/n4KaO2Ie9gCGLjEayDnA/DCICwh X-Received: by 2002:a17:903:1250:b0:19a:9406:b234 with SMTP id u16-20020a170903125000b0019a9406b234mr9705044plh.45.1677713973325; Wed, 01 Mar 2023 15:39:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677713973; cv=none; d=google.com; s=arc-20160816; b=WMK9nJSYiYbQLggTPGE0/ChWigyp776lDY/x/iGz9jv6ZwYR1o0kmpWCeqLbEQuC0R FMTMrSbASsieRPifyTV5/MVFeEoEimhmE7iogG/coU0xWT21WaVDCa4qzrEJC9K5LVcx xwOLJw9ITOBIFfRh6ViqB2ca29RfgVW/VRWO6OwowzHkGuT1hVAOawQG/cON6rR1FltI YVfF20EKjD80OlEaPvOFTZoMR1EB4kRrO7S7+odkwY38aCPZDxdbISLjqjp7sDSUs39F FScRCs+6DPjW6BCPbuYMJrh4K67IkXZG3cCCKTT8EqJYGNLsyMewGtiGJCKowy1aqTVM HUhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=dpr0+8Zx7vhvT2TXC4AX4krbBQphQCXhKIP4IgWJPTg=; b=MB1ijGaaCRyzz273XwTBMSq349RK/HsWHUqeATBXzlT7F4rxVV1xTwn7sWUpSIw+Cu U0YmIemPYfl/EES6l6cs2fB5RAk79md9uM2TY5URUZuyCPYP6dXGC1oLkOO3cEwvfcoq wGVXxqeST68rIOkZO8Q5PE3ihQJC/bLn8ylDQdnwFUGjSjLrV/E5gpNFeYYD6dvLk7Cf S7EbgXt/XNSgOKbS93Z7BOsZN1BXMzCeJl1ZPJ5jYDzukLzmhpCNvsrk6KQKMepHMB+B WVcghil/vtSNVayEGBZ/bQSQEZAW4Mj1BqRdjCTflrMQAvD4YMx049PVrXOXL2twPVKQ Dx9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kLMismFm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri , Nicholas Piggin , Andrew Morton Subject: [PATCH v7 16/24] watchdog/hardlockup: Define a generic function to detect hardlockups Date: Wed, 1 Mar 2023 15:47:45 -0800 Message-Id: <20230301234753.28582-17-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210607577702587?= X-GMAIL-MSGID: =?utf-8?q?1759210607577702587?= The procedure to detect hardlockups is independent of the source of the the non-maskable interrupt that drives it. Place it in a separate, generic function to be invoked by various implementations of the NMI watchdog. Move the bulk of watchdog_overflow_callback() to the new function inspect_for_hardlockups(). This function can then be called from the applicable NMI handlers. No functional changes. Cc: Andi Kleen Cc: Nicholas Piggin Cc: Andrew Morton Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * None Changes since v4: * None Changes since v3: * None Changes since v2: * None Changes since v1: * None --- include/linux/nmi.h | 1 + kernel/watchdog_hld.c | 18 +++++++++++------- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index 048c0b9aa623..75038cb2710e 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -209,6 +209,7 @@ int proc_nmi_watchdog(struct ctl_table *, int , void *, size_t *, loff_t *); int proc_soft_watchdog(struct ctl_table *, int , void *, size_t *, loff_t *); int proc_watchdog_thresh(struct ctl_table *, int , void *, size_t *, loff_t *); int proc_watchdog_cpumask(struct ctl_table *, int, void *, size_t *, loff_t *); +void inspect_for_hardlockups(struct pt_regs *regs); #ifdef CONFIG_HAVE_ACPI_APEI_NMI #include diff --git a/kernel/watchdog_hld.c b/kernel/watchdog_hld.c index 247bf0b1582c..b352e507b17f 100644 --- a/kernel/watchdog_hld.c +++ b/kernel/watchdog_hld.c @@ -106,14 +106,8 @@ static struct perf_event_attr wd_hw_attr = { .disabled = 1, }; -/* Callback function for perf event subsystem */ -static void watchdog_overflow_callback(struct perf_event *event, - struct perf_sample_data *data, - struct pt_regs *regs) +void inspect_for_hardlockups(struct pt_regs *regs) { - /* Ensure the watchdog never gets throttled */ - event->hw.interrupts = 0; - if (__this_cpu_read(watchdog_nmi_touch) == true) { __this_cpu_write(watchdog_nmi_touch, false); return; @@ -163,6 +157,16 @@ static void watchdog_overflow_callback(struct perf_event *event, return; } +/* Callback function for perf event subsystem */ +static void watchdog_overflow_callback(struct perf_event *event, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + /* Ensure the watchdog never gets throttled */ + event->hw.interrupts = 0; + inspect_for_hardlockups(regs); +} + static int hardlockup_detector_event_create(void) { unsigned int cpu = smp_processor_id(); From patchwork Wed Mar 1 23:47:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63132 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3931085wrd; Wed, 1 Mar 2023 15:41:25 -0800 (PST) X-Google-Smtp-Source: AK7set90+zrB+fVVKtTCtkWwUYrELIOTnX7MqeXIGfwGE+15H0tq1VbovP5nchTYU5enzsj1w9U4 X-Received: by 2002:a05:6a20:69a3:b0:cc:1996:9853 with SMTP id t35-20020a056a2069a300b000cc19969853mr13032247pzk.47.1677714084927; Wed, 01 Mar 2023 15:41:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677714084; cv=none; d=google.com; s=arc-20160816; b=Rt+A4/laAfLVyBNgaNs2+tyiOQpyA+HxzivUTxqnhr/KYpYgeE49o/S1LlKBO8U/KE 6iqh/u4k9YEL5Rcg11mPg3p9wt33jH/OcqdbQHPpjOF91fc5fDIL8PBT8eS7nwEh0riw NV6nMK4EvzAA9Umk2xU/GO9hi/Qaco3lWD0+fokiLD+0YcivPFOkMk6pUcKIyfJhRK6M InW96KZWf50uRL3xVDasJaQ6fxi46UbqK2KNMskdXBS9CIYbtdr/zmECz6pif/uf+vGI AFLUb6ct2ohA8cWbQW2LZaFe16TfTgXADwpCjQFUwgvZvKDhqD44UOjAxPOse1aqBUKD HcCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=GaL8zYceIBoMfycu+f2XDHTCe8moBlwJaAli2Lz/Y/8=; b=N5vZDOAGs8kwTYAFd8iStQ5Xup1DDSIz/cfu3QCer4xN153j8cJOfiQM8De4mGsTVu UAPMNx+wz3sm0GAsvBrH1Au3u7rxBRu2tZR8ZWY3NCt3TmTJ7rRS65+XUSFF1WOI4sXM n22XvFw0gBdAaUeRT0FyODX4wdRLoX3TAW2pZtS4/aXYTiC0Nus0fe/hse7v0aXcSfsa xFPWL3LJtCfzwXSGok/7E9Pw2gXrmfjeF/WIVn7Y5oQ1Fu+uA3f0dchHf3M5DTIEKGNe l/bVfSwUcEqcy8xw7R9wRk7WRlmnbhLyIVsXxda4S/IjbNGUTp/5YhmgA5QXgfLDeNWF JlJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YLrIEN3m; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u64-20020a638543000000b004ff6fe5b263si12938617pgd.749.2023.03.01.15.41.10; Wed, 01 Mar 2023 15:41:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=YLrIEN3m; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229993AbjCAXiz (ORCPT + 99 others); Wed, 1 Mar 2023 18:38:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229792AbjCAXiN (ORCPT ); Wed, 1 Mar 2023 18:38:13 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7731F21282 for ; Wed, 1 Mar 2023 15:38:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677713887; x=1709249887; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=y8eExCkaoLH5zqN5BzT0UUYALRj8RDWacqQHg/gnrqc=; b=YLrIEN3mlc5R7eG/lpqLU5XgZZg3B9jbKDT//k66ay4ixcAUGxtzYnup bo1K8JKin45AXhpeYh7IdaRWxOUqjScmNXu9ip1+nZ0NhVdjDKWCVeWYz xkOqdEtvUQuf5D1vHDEDGeyi4O7nNVqHNEjgMdHhdqk7Twf9mrhnJ9bYb 9dGA7cUAVn6rYnD8SzhqHUhptS+Frc1PV8yhKRpcFGzzvo6aoWFNiDoM1 nk79az5t3f/ExXnjmohx+Bm3wl+VBaJTGyIDJHxmitzEgRHDDPE8HkzW5 nVEa8gVBWQJ8PJJ6uTCCjYbfCc1rJInktqIdHBiD0kb9RtyVYjl6imQxl A==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="420818767" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="420818767" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 15:37:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="738826853" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="738826853" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmsmga008.fm.intel.com with ESMTP; 01 Mar 2023 15:37:59 -0800 From: Ricardo Neri To: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri , Nicholas Piggin , Andrew Morton Subject: [PATCH v7 17/24] watchdog/hardlockup: Decouple the hardlockup detector from perf Date: Wed, 1 Mar 2023 15:47:46 -0800 Message-Id: <20230301234753.28582-18-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210724315739401?= X-GMAIL-MSGID: =?utf-8?q?1759210724315739401?= The current default implementation of the hardlockup detector assumes that it is implemented using perf events. However, the hardlockup detector can be driven by other sources of non-maskable interrupts (e.g., a properly configured timer). Group and wrap in #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF all the code specific to perf: create and manage perf events, stop and start the perf- based detector. The generic portion of the detector (monitor the timers' thresholds, check timestamps and detect hardlockups as well as the implementation of arch_touch_nmi_watchdog()) is now selected with the new intermediate config symbol CONFIG_HARDLOCKUP_DETECTOR_CORE. The perf-based implementation of the detector selects the new intermediate symbol. Other implementations should do the same. Cc: Andi Kleen Cc: Nicholas Piggin Cc: Andrew Morton Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * None Changes since v4: * None Changes since v3: * Squashed into this patch a previous patch to make arch_touch_nmi_watchdog() part of the core detector code. Changes since v2: * Undid split of the generic hardlockup detector into a separate file. (Thomas Gleixner) * Added a new intermediate symbol CONFIG_HARDLOCKUP_DETECTOR_CORE to select generic parts of the detector (Paul E. McKenney, Thomas Gleixner). Changes since v1: * Make the generic detector code with CONFIG_HARDLOCKUP_DETECTOR. --- include/linux/nmi.h | 5 ++++- kernel/Makefile | 2 +- kernel/watchdog_hld.c | 32 ++++++++++++++++++++------------ lib/Kconfig.debug | 4 ++++ 4 files changed, 29 insertions(+), 14 deletions(-) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index 75038cb2710e..a38c4509f9eb 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -94,8 +94,11 @@ static inline void hardlockup_detector_disable(void) {} # define NMI_WATCHDOG_SYSCTL_PERM 0444 #endif -#if defined(CONFIG_HARDLOCKUP_DETECTOR_PERF) +#if defined(CONFIG_HARDLOCKUP_DETECTOR_CORE) extern void arch_touch_nmi_watchdog(void); +#endif + +#if defined(CONFIG_HARDLOCKUP_DETECTOR_PERF) extern void hardlockup_detector_perf_stop(void); extern void hardlockup_detector_perf_restart(void); extern void hardlockup_detector_perf_disable(void); diff --git a/kernel/Makefile b/kernel/Makefile index 10ef068f598d..f35fad36cf81 100644 --- a/kernel/Makefile +++ b/kernel/Makefile @@ -91,7 +91,7 @@ obj-$(CONFIG_FAIL_FUNCTION) += fail_function.o obj-$(CONFIG_KGDB) += debug/ obj-$(CONFIG_DETECT_HUNG_TASK) += hung_task.o obj-$(CONFIG_LOCKUP_DETECTOR) += watchdog.o -obj-$(CONFIG_HARDLOCKUP_DETECTOR_PERF) += watchdog_hld.o +obj-$(CONFIG_HARDLOCKUP_DETECTOR_CORE) += watchdog_hld.o obj-$(CONFIG_SECCOMP) += seccomp.o obj-$(CONFIG_RELAY) += relay.o obj-$(CONFIG_SYSCTL) += utsname_sysctl.o diff --git a/kernel/watchdog_hld.c b/kernel/watchdog_hld.c index b352e507b17f..bb6435978c46 100644 --- a/kernel/watchdog_hld.c +++ b/kernel/watchdog_hld.c @@ -22,12 +22,8 @@ static DEFINE_PER_CPU(bool, hard_watchdog_warn); static DEFINE_PER_CPU(bool, watchdog_nmi_touch); -static DEFINE_PER_CPU(struct perf_event *, watchdog_ev); -static DEFINE_PER_CPU(struct perf_event *, dead_event); -static struct cpumask dead_events_mask; static unsigned long hardlockup_allcpu_dumped; -static atomic_t watchdog_cpus = ATOMIC_INIT(0); notrace void arch_touch_nmi_watchdog(void) { @@ -98,14 +94,6 @@ static inline bool watchdog_check_timestamp(void) } #endif -static struct perf_event_attr wd_hw_attr = { - .type = PERF_TYPE_HARDWARE, - .config = PERF_COUNT_HW_CPU_CYCLES, - .size = sizeof(struct perf_event_attr), - .pinned = 1, - .disabled = 1, -}; - void inspect_for_hardlockups(struct pt_regs *regs) { if (__this_cpu_read(watchdog_nmi_touch) == true) { @@ -157,6 +145,24 @@ void inspect_for_hardlockups(struct pt_regs *regs) return; } +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF +#undef pr_fmt +#define pr_fmt(fmt) "NMI perf watchdog: " fmt + +static DEFINE_PER_CPU(struct perf_event *, watchdog_ev); +static DEFINE_PER_CPU(struct perf_event *, dead_event); +static struct cpumask dead_events_mask; + +static atomic_t watchdog_cpus = ATOMIC_INIT(0); + +static struct perf_event_attr wd_hw_attr = { + .type = PERF_TYPE_HARDWARE, + .config = PERF_COUNT_HW_CPU_CYCLES, + .size = sizeof(struct perf_event_attr), + .pinned = 1, + .disabled = 1, +}; + /* Callback function for perf event subsystem */ static void watchdog_overflow_callback(struct perf_event *event, struct perf_sample_data *data, @@ -298,3 +304,5 @@ int __init hardlockup_detector_perf_init(void) } return ret; } + +#endif /* CONFIG_HARDLOCKUP_DETECTOR_PERF */ diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index c8b379e2e9ad..1ff53c5995b1 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -1025,9 +1025,13 @@ config BOOTPARAM_SOFTLOCKUP_PANIC Say N if unsure. +config HARDLOCKUP_DETECTOR_CORE + bool + config HARDLOCKUP_DETECTOR_PERF bool select SOFTLOCKUP_DETECTOR + select HARDLOCKUP_DETECTOR_CORE # # Enables a timestamp based low pass filter to compensate for perf based From patchwork Wed Mar 1 23:47:47 2023 Content-Type: text/plain; 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri , Nicholas Piggin , Andrew Morton Subject: [PATCH v7 18/24] init/main: Delay initialization of the lockup detector after smp_init() Date: Wed, 1 Mar 2023 15:47:47 -0800 Message-Id: <20230301234753.28582-19-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210605164003112?= X-GMAIL-MSGID: =?utf-8?q?1759210605164003112?= Certain implementations of the hardlockup detector require support for Inter-Processor Interrupt shorthands. On x86, support for these can only be determined after all the possible CPUs have booted once (in smp_init()). Other architectures may not need such check. lockup_detector_init() only performs the initializations of data structures of the lockup detector. Hence, there are no dependencies on smp_init(). Cc: Andi Kleen Cc: Nicholas Piggin Cc: Andrew Morton Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Acked-by: Nicholas Piggin Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Introduced this patch Changes since v4: * N/A Changes since v3: * N/A Changes since v2: * N/A Changes since v1: * N/A --- init/main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/init/main.c b/init/main.c index 4425d1783d5c..d0642a49e2e8 100644 --- a/init/main.c +++ b/init/main.c @@ -1620,9 +1620,11 @@ static noinline void __init kernel_init_freeable(void) rcu_init_tasks_generic(); do_pre_smp_initcalls(); - lockup_detector_init(); smp_init(); + + lockup_detector_init(); + sched_init_smp(); padata_init(); From patchwork Wed Mar 1 23:47:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63133 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3931700wrd; Wed, 1 Mar 2023 15:43:28 -0800 (PST) X-Google-Smtp-Source: AK7set9LLApSsvfCLJirg33ygTI3HSReryIEHmg/zqZQ7su1OKOLrPbivkteEtXeKsHoJiQRczWa X-Received: by 2002:a17:902:d2c5:b0:19a:a9d8:e48a with SMTP id n5-20020a170902d2c500b0019aa9d8e48amr10178731plc.22.1677714208291; Wed, 01 Mar 2023 15:43:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677714208; cv=none; d=google.com; s=arc-20160816; b=MlZXzGxjuXOdrOiR8L9ugcOVB90IMmMW2CeopqXWVt+wNujP/N8qQKEynlj5MnaOIb wnPLTO+c/b8PbuXHYgNfRf+JphWbAnZujscYNS1QhGkwMEct4L2aQSbwhovvvPG8MwG4 ak+K9NzsMV+L3bE+8xaVefzv7L65vyPE1uLHR6r2Na7/2HT69BLsnmYiVD/rDhidHCmM m51rifk1l5/Jjr4WhKN8GBFJG1LFY8324ZdOcHxJktMBbo4JUPXTWNutjFVRvo5TYqsH ajzH85L6LffWB9QkL+/7PUk+VbV2FRFQDEYL/yUUIFEpxytmTDPngtliiUtSSuzzeNWe ge+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Qa6uEdjZW4DoYsu9Kjy2sEwA7/HqKazCWOje+E7Wv/8=; b=ESof+tlrUIB5udyhUQYxSd612/lYE3O12pLk/dV4QPCtWRlt+YSClw/dKue8nEIEnY uU0tfwq2Ni2j3RIUpi73jCdQFL22Pmcj/OKPiYFu1Nmx7G549AkQF87kGPQDd7shj/LA Vfy4TjlJAbIM/nq2oqm4N4+VSe5DuqtWORhF1u7Qfz/J70RSS/345MqNlg32xxn/CQw1 iXYDtDZGB5b3m0AQtI7xIBrrwy1pizs5dgb/p7AZawOFBJaPRdwKoBMlq5RzqzhpAfUl aFiFh+2GJzCU5x2+2P8pA7I6EAieMJllywlhsjFOUhG+/GQLt7vqUB24aF64lgLWoMTK 9GQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XJ1FaX1p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 19/24] x86/watchdog/hardlockup: Add an HPET-based hardlockup detector Date: Wed, 1 Mar 2023 15:47:48 -0800 Message-Id: <20230301234753.28582-20-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759210853982429172?= X-GMAIL-MSGID: =?utf-8?q?1759210853982429172?= Implement a hardlockup detector that uses an HPET channel as the source of the non-maskable interrupt. Implement the basic functionality to start, stop, and configure the timer. Designate as the handling CPU one of the CPUs that the detector monitors. Use it to service the NMI from the HPET channel. When servicing the HPET NMI, issue an inter-processor interrupt to the rest of the monitored CPUs to look for hardlockups. Only enable the detector if IPI shorthands are enabled in the system. During operation, the HPET registers are only accessed to kick the timer. This operation can be avoided if the detector gets a periodic HPET channel. Since we use IPI shorthands, all CPUs get the IPI NMI. This would disturb the isolated CPUs specified in the nohz_full command-line parameter. In such case, do not enable this hardlockup detector implementation. The detector is not functional at this stage. A subsequent changeset will invoke the interfaces implemented in this changeset to operate the detector. Another subsequent changeset implements logic to determine if the HPET timer caused the NMI. For now, implement a stub function. Cc: Andi Kleen Cc: Stephane Eranian Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Added missing header asm/nmi.h. linux/nmi.h #includes it only if CONFIG_HAVE_NMI_WATCHDOG selected. Such option is not selected for ARCH=x86. * Removed IRQF_NOBALANCING from request_irq(). The NMI vector already is configured to prevent balancing. * Added check to not use the detector when the nohz_full= command-line parameter is present. * Since I dropped the patch that added a new NMI_WATCHDOG list of handlers, now I added my handler to the NMI_LOCAL list. This makes sense since now the watchdog NMIs are now delivered via IPIs. The only exception is the HPET NMI, but that interrupt can only be handled by the monitoring CPU. Changes since v5: * Squashed a previously separate patch to support interrupt remapping into this patch. There is no need to handle interrupt remapping separately. All the necessary plumbing is done in the interrupt subsystem. Now it uses request_irq(). * Use IPI shorthands to send an NMI to the CPUs being monitored. (Thomas) * Added extra check to only use the HPET hardlockup detector if the IPI shorthands are enabled. (Thomas) * Relocated flushing of outstanding interrupts from enable_timer() to disable_timer(). On some systems, making any change in the configuration of the HPET channel causes it to issue an interrupt. * Added a new cpumask to function as a per-cpu test bit to determine if a CPU should check for hardlockups. * Dropped pointless X86_64 || X86_32 check in Kconfig. (Tony) * Dropped pointless dependency on CONFIG_HPET. * Added dependency on CONFIG_GENERIC_MSI_IRQ, needed to build the [|IR]- HPET-MSI irq_chip. * Added hardlockup_detector_hpet_start() to be used when tsc_khz is recalibrated. * Reworked the periodic setting the HPET channel. Rather than changing it every time the channel is disabled or enabled, do it only once. While at here, wrap the code in an initial setup function. * Implemented hardlockup_detector_hpet_start() to be called when tsc_khz is refined. * Enhanced inline comments for clarity. * Added missing #include files. * Relocated function declarations to not depend on CONFIG_HPET_TIMER. Changes since v4: * Dropped hpet_hld_data.enabled_cpus and instead use cpumask_weight(). * Renamed hpet_hld_data.cpu_monitored_mask to hld_data_data.cpu_monitored_mask and converted it to cpumask_var_t. * Flushed out any outstanding interrupt before enabling the HPET channel. * Removed unnecessary MSI_DATA_LEVEL_ASSERT from the MSI message. * Added comments in hardlockup_detector_nmi_handler() to explain how CPUs are targeted for an IPI. * Updated code to only issue an IPI when needed (i.e., there are monitored CPUs to be inspected via an IPI). * Reworked hardlockup_detector_hpet_init() for readability. * Now reserve the cpumasks in the hardlockup detector code and not in the generic HPET code. * Handled the case of watchdog_thresh = 0 when disabling the detector. * Made this detector available to i386. * Reworked logic to kick the timer to remove a local variable. (Andi) * Added a comment on what type of timer channel will be assigned to the detector. (Andi) * Reworded prompt comment in Kconfig. (Andi) * Removed unneeded switch to level interrupt mode when disabling the timer. (Andi) * Disabled the HPET timer to avoid a race between an incoming interrupt and an update of the MSI destination ID. (Ashok) * Corrected a typo in an inline comment. (Tony) * Made the HPET hardlockup detector depend on HARDLOCKUP_DETECTOR instead of selecting it. Changes since v3: * Fixed typo in Kconfig.debug. (Randy Dunlap) * Added missing slab.h to include the definition of kfree to fix a build break. Changes since v2: * Removed use of struct cpumask in favor of a variable length array in conjunction with kzalloc. (Peter Zijlstra) * Removed redundant documentation of functions. (Thomas Gleixner) * Added CPU as argument hardlockup_detector_hpet_enable()/disable(). (Thomas Gleixner). Changes since v1: * Do not target CPUs in a round-robin manner. Instead, the HPET timer always targets the same CPU; other CPUs are monitored via an interprocessor interrupt. * Dropped support for IO APIC interrupts and instead use only MSI interrupts. * Removed use of generic irq code to set interrupt affinity and NMI delivery. Instead, configure the interrupt directly in HPET registers. (Thomas Gleixner) * Fixed unconditional return NMI_HANDLED when the HPET timer is programmed for FSB/MSI delivery. (Peter Zijlstra) --- arch/x86/Kconfig.debug | 8 + arch/x86/include/asm/hpet.h | 21 ++ arch/x86/kernel/Makefile | 1 + arch/x86/kernel/watchdog_hld_hpet.c | 380 ++++++++++++++++++++++++++++ 4 files changed, 410 insertions(+) create mode 100644 arch/x86/kernel/watchdog_hld_hpet.c diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index bdfe08f1a930..b4dced142116 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -110,6 +110,14 @@ config IOMMU_LEAK config HAVE_MMIOTRACE_SUPPORT def_bool y +config X86_HARDLOCKUP_DETECTOR_HPET + bool "HPET-based hardlockup detector" + select HARDLOCKUP_DETECTOR_CORE + depends on HARDLOCKUP_DETECTOR && HPET_TIMER && GENERIC_MSI_IRQ + help + Say y to drive the hardlockup detector using the High-Precision Event + Timer instead of performance counters. + config X86_DECODER_SELFTEST bool "x86 instruction decoder selftest" depends on DEBUG_KERNEL && INSTRUCTION_DECODER diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index 5762bd0169a1..c88901744848 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -105,6 +105,8 @@ static inline int is_hpet_enabled(void) { return 0; } #endif #ifdef CONFIG_X86_HARDLOCKUP_DETECTOR_HPET +#include + /** * struct hpet_hld_data - Data needed to operate the detector * @has_periodic: The HPET channel supports periodic mode @@ -112,6 +114,10 @@ static inline int is_hpet_enabled(void) { return 0; } * @channe_priv: Private data of the assigned channel * @ticks_per_second: Frequency of the HPET timer * @irq: IRQ number assigned to the HPET channel + * @handling_cpu: CPU handling the HPET interrupt + * @monitored_cpumask: CPUs monitored by the hardlockup detector + * @inspect_cpumask: CPUs that will be inspected at a given time. + * Each CPU clears itself upon inspection. */ struct hpet_hld_data { bool has_periodic; @@ -119,10 +125,25 @@ struct hpet_hld_data { struct hpet_channel *channel_priv; u64 ticks_per_second; int irq; + u32 handling_cpu; + cpumask_var_t monitored_cpumask; + cpumask_var_t inspect_cpumask; }; extern struct hpet_hld_data *hpet_hld_get_timer(void); extern void hpet_hld_free_timer(struct hpet_hld_data *hdata); +int hardlockup_detector_hpet_init(void); +void hardlockup_detector_hpet_start(void); +void hardlockup_detector_hpet_stop(void); +void hardlockup_detector_hpet_enable(unsigned int cpu); +void hardlockup_detector_hpet_disable(unsigned int cpu); +#else +static inline int hardlockup_detector_hpet_init(void) +{ return -ENODEV; } +static inline void hardlockup_detector_hpet_start(void) {} +static inline void hardlockup_detector_hpet_stop(void) {} +static inline void hardlockup_detector_hpet_enable(unsigned int cpu) {} +static inline void hardlockup_detector_hpet_disable(unsigned int cpu) {} #endif /* CONFIG_X86_HARDLOCKUP_DETECTOR_HPET */ #endif /* _ASM_X86_HPET_H */ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index dd61752f4c96..58eb858f33ff 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -109,6 +109,7 @@ obj-$(CONFIG_VM86) += vm86_32.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_HPET_TIMER) += hpet.o +obj-$(CONFIG_X86_HARDLOCKUP_DETECTOR_HPET) += watchdog_hld_hpet.o obj-$(CONFIG_AMD_NB) += amd_nb.o obj-$(CONFIG_DEBUG_NMI_SELFTEST) += nmi_selftest.o diff --git a/arch/x86/kernel/watchdog_hld_hpet.c b/arch/x86/kernel/watchdog_hld_hpet.c new file mode 100644 index 000000000000..b583d3180ae0 --- /dev/null +++ b/arch/x86/kernel/watchdog_hld_hpet.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * A hardlockup detector driven by an HPET channel. + * + * Copyright (C) Intel Corporation 2023 + * + * An HPET channel is reserved for the detector. The channel issues an NMI to + * one of the CPUs in @watchdog_allowed_mask. This CPU monitors itself for + * hardlockups and sends an NMI IPI to the rest of the CPUs in the system. + * + * The detector uses IPI shorthands. Thus, all CPUs in the system get the NMI + * (offline CPUs also get the NMI but they "ignore" it). A cpumask is used to + * specify whether a CPU must check for hardlockups. + * + * The NMI also disturbs isolated CPUs. The detector fails to initialize if + * tick_nohz_full is enabled. + */ + +#define pr_fmt(fmt) "NMI hpet watchdog: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "apic/local.h" + +static struct hpet_hld_data *hld_data; + +static void __init setup_hpet_channel(struct hpet_hld_data *hdata) +{ + u32 v; + + v = hpet_readl(HPET_Tn_CFG(hdata->channel)); + if (hdata->has_periodic) + v |= HPET_TN_PERIODIC; + else + v &= ~HPET_TN_PERIODIC; + + /* + * Use 32-bit mode to limit the number of register accesses. If we are + * here the HPET frequency is sufficiently low to accommodate this mode. + */ + v |= HPET_TN_32BIT; + + /* If we are here, FSB mode is supported. */ + v |= HPET_TN_FSB; + + hpet_writel(v, HPET_Tn_CFG(hdata->channel)); +} + +/** + * kick_timer() - Reprogram timer to expire in the future + * @hdata: A data structure describing the HPET channel + * @force: Force reprogramming + * + * Reprogram the timer to expire in watchdog_thresh seconds in the future. + * If the timer supports periodic mode, it is not kicked unless @force is + * true. + */ +static void kick_timer(struct hpet_hld_data *hdata, bool force) +{ + u64 new_compare, count, period = 0; + + /* Kick the timer only when needed. */ + if (!force && hdata->has_periodic) + return; + + /* + * Update the comparator in increments of watch_thresh seconds relative + * to the current count. Since watch_thresh is given in seconds, we can + * safely update the comparator before the counter reaches such new + * value. + * + * Let it wrap around if needed. + */ + + count = hpet_readl(HPET_COUNTER); + new_compare = count + watchdog_thresh * hdata->ticks_per_second; + + if (!hdata->has_periodic) { + hpet_writel(new_compare, HPET_Tn_CMP(hdata->channel)); + return; + } + + period = watchdog_thresh * hdata->ticks_per_second; + hpet_set_comparator_periodic(hdata->channel, (u32)new_compare, + (u32)period); +} + +static void disable_timer(struct hpet_hld_data *hdata) +{ + u32 v; + + v = hpet_readl(HPET_Tn_CFG(hdata->channel)); + v &= ~HPET_TN_ENABLE; + + /* + * Prepare to flush out any outstanding interrupt. This can only be + * done in level-triggered mode. + */ + v |= HPET_TN_LEVEL; + hpet_writel(v, HPET_Tn_CFG(hdata->channel)); + + /* + * Even though we use the HPET channel in edge-triggered mode, hardware + * seems to keep an outstanding interrupt and posts an MSI message when + * making any change to it (e.g., enabling or setting to FSB mode). + * Flush out the interrupt status bit of our channel. + */ + hpet_writel(1 << hdata->channel, HPET_STATUS); +} + +static void enable_timer(struct hpet_hld_data *hdata) +{ + u32 v; + + v = hpet_readl(HPET_Tn_CFG(hdata->channel)); + v &= ~HPET_TN_LEVEL; + v |= HPET_TN_ENABLE; + hpet_writel(v, HPET_Tn_CFG(hdata->channel)); +} + +/** + * is_hpet_hld_interrupt() - Check if the HPET channel caused the interrupt + * @hdata: A data structure describing the HPET channel + * + * Returns: + * True if the HPET watchdog timer caused the interrupt. False otherwise. + */ +static bool is_hpet_hld_interrupt(struct hpet_hld_data *hdata) +{ + return false; +} + +/** + * hardlockup_detector_nmi_handler() - NMI Interrupt handler + * @type: Type of NMI handler; not used. + * @regs: Register values as seen when the NMI was asserted + * + * Check if our HPET channel caused the NMI. If yes, inspect for lockups by + * issuing an IPI to the rest of the CPUs. Also, kick the timer if it is + * non-periodic. + * + * Returns: + * NMI_DONE if the HPET timer did not cause the interrupt. NMI_HANDLED + * otherwise. + */ +static int hardlockup_detector_nmi_handler(unsigned int type, + struct pt_regs *regs) +{ + struct hpet_hld_data *hdata = hld_data; + int cpu; + + /* + * The CPU handling the HPET NMI will land here and trigger the + * inspection of hardlockups in the rest of the monitored + * CPUs. + */ + if (is_hpet_hld_interrupt(hdata)) { + /* + * Kick the timer first. If the HPET channel is periodic, it + * helps to reduce the delta between the expected TSC value and + * its actual value the next time the HPET channel fires. + */ + kick_timer(hdata, !(hdata->has_periodic)); + + if (cpumask_weight(hld_data->monitored_cpumask) > 1) { + /* + * Since we cannot know the source of an NMI, the best + * we can do is to use a flag to indicate to all online + * CPUs that they will get an NMI and that the source of + * that NMI is the hardlockup detector. Offline CPUs + * also receive the NMI but they ignore it. + */ + cpumask_copy(hld_data->inspect_cpumask, + cpu_online_mask); + + /* If we are here, IPI shorthands are enabled. */ + apic->send_IPI_allbutself(NMI_VECTOR); + } + + inspect_for_hardlockups(regs); + return NMI_HANDLED; + } + + /* The rest of the CPUs will land here after receiving the IPI. */ + cpu = smp_processor_id(); + if (cpumask_test_and_clear_cpu(cpu, hld_data->inspect_cpumask)) { + if (cpumask_test_cpu(cpu, hld_data->monitored_cpumask)) + inspect_for_hardlockups(regs); + + return NMI_HANDLED; + } + + return NMI_DONE; +} + +/** + * setup_hpet_irq() - Install the interrupt handler of the detector + * @data: Data associated with the instance of the HPET channel + * + * Returns: + * 0 success. An error code if setup was unsuccessful. + */ +static int setup_hpet_irq(struct hpet_hld_data *hdata) +{ + int ret; + + /* + * hld_data::irq was configured to deliver the interrupt as + * NMI. Thus, there is no need for a regular interrupt handler. + */ + ret = request_irq(hld_data->irq, no_action, IRQF_TIMER, + "hpet_hld", hld_data); + if (ret) + return ret; + + ret = register_nmi_handler(NMI_LOCAL, + hardlockup_detector_nmi_handler, 0, + "hpet_hld"); + if (ret) + free_irq(hld_data->irq, hld_data); + + return ret; +} + +/** + * hardlockup_detector_hpet_enable() - Enable the hardlockup detector + * @cpu: CPU Index in which the watchdog will be enabled. + * + * Enable the hardlockup detector in @cpu. Also, start the detector if not done + * before. + */ +void hardlockup_detector_hpet_enable(unsigned int cpu) +{ + cpumask_set_cpu(cpu, hld_data->monitored_cpumask); + + /* + * If this is the first CPU on which the detector is enabled, designate + * @cpu as the handling CPU and start everything. The HPET channel is + * disabled at this point. + */ + if (cpumask_weight(hld_data->monitored_cpumask) == 1) { + hld_data->handling_cpu = cpu; + + if (irq_set_affinity(hld_data->irq, + cpumask_of(hld_data->handling_cpu))) { + pr_warn_once("Failed to set affinity. Hardlockdup detector not started"); + return; + } + + kick_timer(hld_data, true); + enable_timer(hld_data); + } +} + +/** + * hardlockup_detector_hpet_disable() - Disable the hardlockup detector + * @cpu: CPU index in which the watchdog will be disabled + * + * Disable the hardlockup detector in @cpu. If @cpu is also handling the NMI + * from the HPET channel, update the affinity of the interrupt. + */ +void hardlockup_detector_hpet_disable(unsigned int cpu) +{ + cpumask_clear_cpu(cpu, hld_data->monitored_cpumask); + + if (hld_data->handling_cpu != cpu) + return; + + disable_timer(hld_data); + if (!cpumask_weight(hld_data->monitored_cpumask)) + return; + + /* + * If watchdog_thresh is zero, then the hardlockup detector is being + * disabled. + */ + if (!watchdog_thresh) + return; + + hld_data->handling_cpu = cpumask_any_but(hld_data->monitored_cpumask, + cpu); + /* + * Only update the affinity of the HPET channel interrupt when + * disabled. + */ + if (irq_set_affinity(hld_data->irq, + cpumask_of(hld_data->handling_cpu))) { + pr_warn_once("Failed to set affinity. Hardlockdup detector stopped"); + return; + } + + enable_timer(hld_data); +} + +void hardlockup_detector_hpet_stop(void) +{ + disable_timer(hld_data); +} + +void hardlockup_detector_hpet_start(void) +{ + kick_timer(hld_data, true); + enable_timer(hld_data); +} + +static const char hpet_hld_init_failed[] = "Initialization failed:"; + +/** + * hardlockup_detector_hpet_init() - Initialize the hardlockup detector + * + * Only initialize and configure the detector if an HPET is available on the + * system, the TSC is stable, IPI shorthands are enabled, and there are no + * isolated CPUs. + * + * Returns: + * 0 success. An error code if initialization was unsuccessful. + */ +int __init hardlockup_detector_hpet_init(void) +{ + int ret; + + if (!is_hpet_enabled()) { + pr_info("%s HPET unavailable\n", hpet_hld_init_failed); + return -ENODEV; + } + + if (tick_nohz_full_enabled()) { + pr_info("%s nohz_full in use\n", hpet_hld_init_failed); + return -EPERM; + } + + if (!static_branch_likely(&apic_use_ipi_shorthand)) { + pr_info("%s APIC IPI shorthands disabled\n", hpet_hld_init_failed); + return -ENODEV; + } + + if (check_tsc_unstable()) + return -ENODEV; + + hld_data = hpet_hld_get_timer(); + if (!hld_data) + return -ENODEV; + + disable_timer(hld_data); + + setup_hpet_channel(hld_data); + + ret = setup_hpet_irq(hld_data); + if (ret) + goto err_no_irq; + + if (!zalloc_cpumask_var(&hld_data->monitored_cpumask, GFP_KERNEL)) + goto err_no_monitored_cpumask; + + if (!zalloc_cpumask_var(&hld_data->inspect_cpumask, GFP_KERNEL)) + goto err_no_inspect_cpumask; + + return 0; + +err_no_inspect_cpumask: + free_cpumask_var(hld_data->monitored_cpumask); +err_no_monitored_cpumask: + ret = -ENOMEM; +err_no_irq: + hpet_hld_free_timer(hld_data); + hld_data = NULL; + + return ret; +} From patchwork Wed Mar 1 23:47:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63135 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3935744wrd; Wed, 1 Mar 2023 15:54:40 -0800 (PST) X-Google-Smtp-Source: AK7set9FA1Y4TtE+J4naTTc4VDgOmg4XPSUI8LuUU2QHhoP4u1I+tlieOcdTNvYl+RDcQECAoVJI X-Received: by 2002:a17:903:244e:b0:19c:e484:b4e with SMTP id l14-20020a170903244e00b0019ce4840b4emr7555262pls.59.1677714880349; Wed, 01 Mar 2023 15:54:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677714880; cv=none; d=google.com; s=arc-20160816; b=I62DUtYO1vwxtVlQG4SvencTVxPm+tOaE7fnbsJokQIqUCbvI05cHgxVjQWZrbjn/A IORBm++QvyyHKRGl6rLSPR+/AsIBOELC5ofDl0cSPr38cUdqJkZb2Y03hObX4d8ckvC1 2EQtlryHlH5AlGNScfpfh5ito1qxkei2v59Sm/BFlKxCMthBFrPQ2RdL4z2Ff4dU/Zjz dQLv9B0IVVnuypnKiqKn9IYyAF1tkEdlB3EW/ny22gADRoZnDQMFD+cSmBLvx7Xc6CKs rlYdiI6qRzMg8UywiJrsNpjzryWsyIzK7VzL4bvhrCC4CyEeA0TaQFz+FsuPsRLBUHii 3oZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=+Z1EwmKqe+DihJSNALRqklCNht3Hq1VhSfjWlzSmmxA=; b=ZGcn59YnYs7quhjwFD748nwbBQ9Mk7LhjBK3mT8VsFSef5GoR4ldN5wc1/f8wqr8qv LTT8WXBAN3x4E938h4tShc4YTv1CFXiKy/snD2p3pQijTSXOClLrh9X2hx7UB2fBZOi/ yqcpNIzinKAdI2W3kxQWZi1dGwUrzXdlCgyk2AxBixvs3zZ8mSBfX5VQ+3bkQF3Ub+WX GZB/IjAHKyR3lDi3BDtdo/ol4WzTtcAWUHnHAawetP9cDdsuMQ7Yrcuaoovff2LbsXR+ Wqt4rwqYSiaPDS4KplOsCMf3fZy5oRo7yoYytAVBHDstcQ1PlbVZrtZmEotiCXmzdGcH 0N+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=WAwqbSy3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 20/24] x86/watchdog/hardlockup/hpet: Determine if HPET timer caused NMI Date: Wed, 1 Mar 2023 15:47:49 -0800 Message-Id: <20230301234753.28582-21-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759211558240124388?= X-GMAIL-MSGID: =?utf-8?q?1759211558240124388?= It is not possible to determine the source of a non-maskable interrupt (NMI) in x86. When dealing with an HPET channel, the only direct method to determine whether it caused an NMI would be to read the Interrupt Status register. Reading HPET registers is slow and, therefore, not to be done while in NMI context. Also, the interrupt status bit is not available if the HPET channel is programmed to deliver an MSI interrupt. An indirect manner to infer if the HPET channel is the source of an NMI is is to use the time-stamp counter (TSC). Compute the value that the TSC is expected to have at the next interrupt of the HPET channel and compare it with the value it has when the interrupt does happen. Let this error be tsc_next_error. If tsc_next_error is less than a certain value, assume that the HPET channel of the detector is the source of the NMI. Below is a table that characterizes tsc_next_error in a collection of systems. The error is expressed in microseconds as well as a percentage of tsc_delta: the computed number of TSC counts between two consecutive interrupts of the HPET channel. The table summarizes the error of 4096 interrupts of the HPET channel in two experiments: a) since the system booted and b) ignoring the first 5 minutes after boot. The maximum observed error in a) is 0.198%. For b) the maximum error is 0.045%. Allow a maximum tsc_next_error that is twice as big the maximum error observed in these experiments: 0.4% of tsc_delta. watchdog_thresh 1s 10s 60s tsc_next_error % us % us % us AMD EPYC 7742 64-Core Processor max(abs(a)) 0.04517 451.74 0.00171 171.04 0.00034 201.89 max(abs(b)) 0.04517 451.74 0.00171 171.04 0.00034 201.89 Intel(R) Xeon(R) CPU E7-8890 - INTEL_FAM6_HASWELL_X max(abs(a)) 0.00811 81.15 0.00462 462.40 0.00014 81.65 max(abs(b)) 0.00811 81.15 0.00084 84.31 0.00014 81.65 Intel(R) Xeon(R) Platinum 8170M - INTEL_FAM6_SKYLAKE_X max(abs(a)) 0.10530 1053.04 0.01324 1324.27 0.00407 2443.25 max(abs(b)) 0.01166 116.59 0.00114 114.11 0.00024 143.47 Intel(R) Xeon(R) CPU E5-2699A v4 - INTEL_FAM6_BROADSWELL_X max(abs(a)) 0.00010 99.34 0.00099 98.83 0.00016 97.50 max(abs(b)) 0.00010 99.34 0.00099 98.83 0.00016 97.50 Intel(R) Xeon(R) Gold 5318H - INTEL_FAM6_COOPERLAKE_X max(abs(a)) 0.11262 1126.17 0.01109 1109.17 0.00409 2455.73 max(abs(b)) 0.01073 107.31 0.00109 109.02 0.00019 115.34 Intel(R) Xeon(R) Platinum 8360Y - INTEL_FAM6_ICELAKE_X max(abs(a)) 0.19853 1985.30 0.00784 783.53 -0.00017 -104.77 max(abs(b)) 0.01550 155.02 0.00158 157.56 0.00020 117.74 Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Andi Kleen Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- NOTE: The error characterization data is repeated here from the cover letter. --- Changes since v6: * Fixed bug when checking the error window. Now check for an error which is +/-4% the actual TSC value, not +/-2%. Changes since v5: * Reworked is_hpet_hld_interrupt() to reduce indentation. * Use time_in_range64() to compare the actual TSC value vs the expected value. This makes it more readable. (Tony) * Reduced the error window of the expected TSC value at the time of the HPET channel expiration. * Described better the heuristics used to determine if the HPET channel caused the NMI. (Tony) * Added a table to characterize the error in the expected TSC value when the HPET channel fires. * Removed references to groups of monitored CPUs. Instead, use tsc_khz directly. Changes since v4: * Compute the TSC expected value at the next HPET interrupt based on the number of monitored packages and not the number of monitored CPUs. Changes since v3: * None Changes since v2: * Reworked condition to check if the expected TSC value is within the error margin to avoid an unnecessary conditional. (Peter Zijlstra) * Removed TSC error margin from struct hld_data; use a global variable instead. (Peter Zijlstra) Changes since v1: * Introduced this patch. --- arch/x86/include/asm/hpet.h | 3 ++ arch/x86/kernel/watchdog_hld_hpet.c | 58 +++++++++++++++++++++++++++-- 2 files changed, 58 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h index c88901744848..af0a504b5cff 100644 --- a/arch/x86/include/asm/hpet.h +++ b/arch/x86/include/asm/hpet.h @@ -113,6 +113,8 @@ static inline int is_hpet_enabled(void) { return 0; } * @channel: HPET channel assigned to the detector * @channe_priv: Private data of the assigned channel * @ticks_per_second: Frequency of the HPET timer + * @tsc_next: Estimated value of the TSC at the next + * HPET timer interrupt * @irq: IRQ number assigned to the HPET channel * @handling_cpu: CPU handling the HPET interrupt * @monitored_cpumask: CPUs monitored by the hardlockup detector @@ -124,6 +126,7 @@ struct hpet_hld_data { u32 channel; struct hpet_channel *channel_priv; u64 ticks_per_second; + u64 tsc_next; int irq; u32 handling_cpu; cpumask_var_t monitored_cpumask; diff --git a/arch/x86/kernel/watchdog_hld_hpet.c b/arch/x86/kernel/watchdog_hld_hpet.c index b583d3180ae0..a03126e02eda 100644 --- a/arch/x86/kernel/watchdog_hld_hpet.c +++ b/arch/x86/kernel/watchdog_hld_hpet.c @@ -12,6 +12,11 @@ * (offline CPUs also get the NMI but they "ignore" it). A cpumask is used to * specify whether a CPU must check for hardlockups. * + * It is not possible to determine the source of an NMI. Instead, we calculate + * the value that the TSC counter should have when the next HPET NMI occurs. If + * it has the calculated value +/- 0.4%, we conclude that the HPET channel is the + * source of the NMI. + * * The NMI also disturbs isolated CPUs. The detector fails to initialize if * tick_nohz_full is enabled. */ @@ -34,6 +39,7 @@ #include "apic/local.h" static struct hpet_hld_data *hld_data; +static u64 tsc_next_error; static void __init setup_hpet_channel(struct hpet_hld_data *hdata) { @@ -65,12 +71,39 @@ static void __init setup_hpet_channel(struct hpet_hld_data *hdata) * Reprogram the timer to expire in watchdog_thresh seconds in the future. * If the timer supports periodic mode, it is not kicked unless @force is * true. + * + * Also, compute the expected value of the time-stamp counter at the time of + * expiration as well as a deviation from the expected value. */ static void kick_timer(struct hpet_hld_data *hdata, bool force) { - u64 new_compare, count, period = 0; + u64 tsc_curr, tsc_delta, new_compare, count, period = 0; + + tsc_curr = rdtsc(); + + /* + * Compute the delta between the value of the TSC now and the value + * it will have the next time the HPET channel fires. + */ + tsc_delta = watchdog_thresh * tsc_khz * 1000L; + hdata->tsc_next = tsc_curr + tsc_delta; + + /* + * Define an error window between the expected TSC value and the actual + * value it will have the next time the HPET channel fires. Define this + * error as percentage of tsc_delta. + * + * The systems that have been tested so far exhibit an error of 0.05% + * of the expected TSC value once the system is up and running. Systems + * that refine tsc_khz exhibit a larger initial error up to 0.2%. To be + * safe, allow a maximum error of ~0.4% (i.e., tsc_delta / 256). + */ + tsc_next_error = tsc_delta >> 8; - /* Kick the timer only when needed. */ + /* + * We must compute the exptected TSC value always. Kick the timer only + * when needed. + */ if (!force && hdata->has_periodic) return; @@ -133,12 +166,31 @@ static void enable_timer(struct hpet_hld_data *hdata) * is_hpet_hld_interrupt() - Check if the HPET channel caused the interrupt * @hdata: A data structure describing the HPET channel * + * Determining the sources of NMIs is not possible. Furthermore, we have + * programmed the HPET channel for MSI delivery, which does not have a + * status bit. Also, reading HPET registers is slow. + * + * Instead, we just assume that an NMI delivered within a time window + * of when the HPET was expected to fire probably came from the HPET. + * + * The window is estimated using the TSC counter. Check the comments in + * kick_timer() for details on the size of the time window. + * * Returns: * True if the HPET watchdog timer caused the interrupt. False otherwise. */ static bool is_hpet_hld_interrupt(struct hpet_hld_data *hdata) { - return false; + u64 tsc_curr, tsc_curr_min, tsc_curr_max; + + if (smp_processor_id() != hdata->handling_cpu) + return false; + + tsc_curr = rdtsc(); + tsc_curr_min = tsc_curr - tsc_next_error; + tsc_curr_max = tsc_curr + tsc_next_error; + + return time_in_range64(hdata->tsc_next, tsc_curr_min, tsc_curr_max); } /** From patchwork Wed Mar 1 23:47:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63136 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3936774wrd; Wed, 1 Mar 2023 15:58:13 -0800 (PST) X-Google-Smtp-Source: AK7set+blMvwK1YJ96tTPHq/P+mMZA+kUqvQAxgQ/1dHx85yCsruuXRdwFZrklhPXQn4L6TKkd2S X-Received: by 2002:a17:90a:1db:b0:237:39b1:7b7 with SMTP id 27-20020a17090a01db00b0023739b107b7mr9701795pjd.11.1677715093135; Wed, 01 Mar 2023 15:58:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677715093; cv=none; d=google.com; s=arc-20160816; b=NlmsKmV46l1h4wYfZP2YVl5ZSiEJNOSCKqX/m4FOTHPtDXpsNCoDTX4n3+ixURZOKY J7t5hjUuSQ4sSVnWAnYqTMfPbSmbuRC2yGwKT+8k9pl0QU60MsTHw/+0FaxU6GIh5fzd mlxpo5itR8ETGup8Kq1mD6NEp4mByem7pke88/j9CT0Etw7uF50SyLmYDZ93h7O37XYW yxpW/S2ImmzHUW5T6VZiVuN3Bif3gVYpEyc0u6GjpY/mljGclIKwyeK1m8LAltkSk6XS SfgJA5al2nmip1LuUIxKuEvne1x2S/SSkleg+4NsqqW2OeSgIJUFIwf2FSNAneTDt5iK l1Og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=+WUzKY81oBWiiiyEJcItLmxXo61z2pnmfyZHNar/TPo=; b=0/5pxC4jQjApc05rYyRdwOIe1Ufon07DJ4+vsxItU0qvoivmyI+VLS85zZuolWU6Es YIKJ5Mix/Tc7lldFQM8SDfWOv09feOiEUSc+lR7cbnAnDhYdP2d8aDmdIAW11NjzkY21 GwO7nPyyQlGIjjSl9FC5/YVVB8uZKqdQsu7kEv91TUk+dAeIoNuJLzRBVUncZC/XnfGs UXekWY37mlFf8aX0W0jigceGug8bG6OmkmCzuokBCDxzNS2PM/gCgNIZAwkKiY9+giZw eTKO6VFEURXMjBasL/vNV6oXEaUSe1WPMTD6aPbZUcjmUrM3F9SrEtfGgdRtFQFH6rAK vxbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=mGGKiJ86; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 21/24] watchdog/hardlockup/hpet: Only enable the HPET watchdog via a boot parameter Date: Wed, 1 Mar 2023 15:47:50 -0800 Message-Id: <20230301234753.28582-22-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759211781726752953?= X-GMAIL-MSGID: =?utf-8?q?1759211781726752953?= Keep the HPET-based hardlockup detector disabled unless explicitly enabled via a command-line argument. If such parameter is not given, the initialization of the HPET-based hardlockup detector fails and the NMI watchdog will fall back to use the perf-based implementation. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Do not reuse the nmi_watchdog command line option. Instead, use a separate command line option. (Nicholas Piggin) * Document conflict with conflict between `hpet_nmi_watchdog` and `nohz_full` and dependency on `no_ipi_broadcast`. Changes since v5: * None Changes since v4: * None Changes since v3: * None Changes since v2: * Do not imply that using nmi_watchdog=hpet means the detector is enabled. Instead, print a warning in such case. Changes since v1: * Added documentation to the function handing the nmi_watchdog kernel command-line argument. --- Documentation/admin-guide/kernel-parameters.txt | 8 ++++++++ arch/x86/kernel/watchdog_hld_hpet.c | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 46268d6baa43..2d1262bb99c7 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1708,6 +1708,14 @@ hpet_mmap= [X86, HPET_MMAP] Allow userspace to mmap HPET registers. Default set by CONFIG_HPET_MMAP_DEFAULT. + hpet_nmi_watchdog [X86, KNL] + Drive the NMI watchdog with an HPET channel. This option + has no effect if the NMI watchdog is not enabled. + The HPET NMI watchdog conflicts with the parameters + nohz_full, no_ipi_broadcast, and hpet=disable. If any + of these parameters is present the NMI watchdog will + fall back to the perf-driven implementation. + hugepages= [HW] Number of HugeTLB pages to allocate at boot. If this follows hugepagesz (below), it specifies the number of pages of hugepagesz to be allocated. diff --git a/arch/x86/kernel/watchdog_hld_hpet.c b/arch/x86/kernel/watchdog_hld_hpet.c index a03126e02eda..0fc728ad6f15 100644 --- a/arch/x86/kernel/watchdog_hld_hpet.c +++ b/arch/x86/kernel/watchdog_hld_hpet.c @@ -39,6 +39,7 @@ #include "apic/local.h" static struct hpet_hld_data *hld_data; +static bool hardlockup_use_hpet; static u64 tsc_next_error; static void __init setup_hpet_channel(struct hpet_hld_data *hdata) @@ -366,6 +367,19 @@ void hardlockup_detector_hpet_start(void) enable_timer(hld_data); } +/** + * hardlockup_detector_hpet_setup() - Parse command-line parameters + * @str: A string containing the kernel command line + * + * If selected by the user, enable this hardlockup detector. + */ +static int __init hardlockup_detector_hpet_setup(char *str) +{ + hardlockup_use_hpet = true; + return 1; +} +__setup("hpet_nmi_watchdog", hardlockup_detector_hpet_setup); + static const char hpet_hld_init_failed[] = "Initialization failed:"; /** @@ -382,6 +396,9 @@ int __init hardlockup_detector_hpet_init(void) { int ret; + if (!hardlockup_use_hpet) + return -ENODEV; + if (!is_hpet_enabled()) { pr_info("%s HPET unavailable\n", hpet_hld_init_failed); return -ENODEV; From patchwork Wed Mar 1 23:47:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63134 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3933736wrd; Wed, 1 Mar 2023 15:49:12 -0800 (PST) X-Google-Smtp-Source: AK7set9WoR1WX+c4wZzwLY8zBRCvIhkL26k1Wr4RPVA5Sc9Fx/jAtllnYbrv77vBvd9draRg5Z5P X-Received: by 2002:a17:90a:5c:b0:237:40b6:1011 with SMTP id 28-20020a17090a005c00b0023740b61011mr9516155pjb.47.1677714552390; Wed, 01 Mar 2023 15:49:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677714552; cv=none; d=google.com; s=arc-20160816; b=IqdwxgH63swIdI2OWt3DF+2vf4zxLe0AJucfdj5Uci5N7KScavEVmCQaQecjbFcKPw 4BsgT1PqVtbmYKlB5XuedwRIkT26rq34o7IsKmt1usuux50kIoqvi4I9QimGjnqRGhZi Hh9tQGeLNL1NZX9c8qXk0NxIImPwMzWM3ZeYPeH02ISoKSnpevYnBIMEpGBjVx0X0jUW YlcXrga7kt3uADwfeGF3plv6CH4fZ+ONHHS2ufSRYYcnkSUx8aB7BXBXZ6ra687wVE6g RaeCsrzc+GhAPtu+cUYHQuXBjNH0lOPZ9ydXOZNvoJQDVqCieezQ9uL4DncwFA0Nq5R1 n0Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=TfAVIKvawGXvtEKD3SRklhyaGVh6YDz5/m3h6tJXU4s=; b=uXooukujg4MLchOGb1RPCFhbKjRxruGV9XQgyrGYl7cYLEV79h4D+uzM7/Gy1UtFQN eQLMrKbeTl8zRGL4JpFwuXw5XgDpVGqeAYAPwm3wPjM6cPMwpDJp5wg9xnYzX7GGIqu+ l0HQmwxNKdMKYxj/hb0KFIeSCwTowh7K1ge0vxAGFd0XsPvRLwotQNQM+68dwP1WIxpn ejoqzAUQgJ/Pcbv/T0J4UV2awCgRgsgPvcdlUxperlr5EYDqgLT3scbfdZTiYhbrVpaE w43LI6F4+gxovvyCiQPDLGYNKvFXVAPolD78kf1uY/UBZ/XcI+Cd0YJGNixkNM4hMluF NhSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=NMPe86NR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 22/24] x86/watchdog: Add a shim hardlockup detector Date: Wed, 1 Mar 2023 15:47:51 -0800 Message-Id: <20230301234753.28582-23-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759211214569534080?= X-GMAIL-MSGID: =?utf-8?q?1759211214569534080?= Add a shim hardlockup detector that allows to select between the perf- and HPET-driven implementations available for x86. Override the interfaces of the default hardlockup detector. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Nicholas Piggin Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * None Changes since v5: * Added watchdog_nmi_start() to be used when the watchdog is reconfigured. * Always build the x86-specific hardlockup detector shim; not only when the HPET-based detector is selected. * Corrected a typo in comment in watchdog_nmi_probe() (Ani) * Removed useless local ret variable in watchdog_nmi_enable(). (Ani) Changes since v4: * Use a switch to enable and disable the various available detectors. (Andi) Changes since v3: * Fixed style in multi-line comment. (Randy Dunlap) Changes since v2: * Pass cpu number as argument to hardlockup_detector_[enable|disable]. (Thomas Gleixner) Changes since v1: * Introduced this patch: Added an x86-specific shim hardlockup detector. (Nicholas Piggin) --- arch/x86/Kconfig.debug | 3 ++ arch/x86/kernel/Makefile | 2 + arch/x86/kernel/watchdog_hld.c | 86 ++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 arch/x86/kernel/watchdog_hld.c diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index b4dced142116..41ae46314307 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -3,6 +3,9 @@ config EARLY_PRINTK_USB bool +config X86_HARDLOCKUP_DETECTOR + def_bool y if HARDLOCKUP_DETECTOR_CORE + config X86_VERBOSE_BOOTUP bool "Enable verbose x86 bootup info messages" default y diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 58eb858f33ff..706294fd5e46 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -108,6 +108,8 @@ obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_VM86) += vm86_32.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_X86_HARDLOCKUP_DETECTOR) += watchdog_hld.o + obj-$(CONFIG_HPET_TIMER) += hpet.o obj-$(CONFIG_X86_HARDLOCKUP_DETECTOR_HPET) += watchdog_hld_hpet.o diff --git a/arch/x86/kernel/watchdog_hld.c b/arch/x86/kernel/watchdog_hld.c new file mode 100644 index 000000000000..33c22f6456a3 --- /dev/null +++ b/arch/x86/kernel/watchdog_hld.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * A shim hardlockup detector for x86 to select between the perf- and HPET- + * driven implementations. + * + * Copyright (C) Intel Corporation 2023 + */ + +#include +#include + +enum x86_hardlockup_detector { + X86_HARDLOCKUP_DETECTOR_PERF, + X86_HARDLOCKUP_DETECTOR_HPET, +}; + +static enum x86_hardlockup_detector detector_type __ro_after_init; + +int watchdog_nmi_enable(unsigned int cpu) +{ + switch (detector_type) { + case X86_HARDLOCKUP_DETECTOR_PERF: + hardlockup_detector_perf_enable(); + break; + case X86_HARDLOCKUP_DETECTOR_HPET: + hardlockup_detector_hpet_enable(cpu); + break; + default: + return -ENODEV; + } + + return 0; +} + +void watchdog_nmi_disable(unsigned int cpu) +{ + switch (detector_type) { + case X86_HARDLOCKUP_DETECTOR_PERF: + hardlockup_detector_perf_disable(); + break; + case X86_HARDLOCKUP_DETECTOR_HPET: + hardlockup_detector_hpet_disable(cpu); + break; + } +} + +int __init watchdog_nmi_probe(void) +{ + int ret; + + /* + * Try first with the HPET hardlockup detector. It will only succeed if + * requested via the kernel command line. The perf-based detector is + * used by default. + */ + ret = hardlockup_detector_hpet_init(); + if (!ret) { + detector_type = X86_HARDLOCKUP_DETECTOR_HPET; + return ret; + } + + ret = hardlockup_detector_perf_init(); + if (!ret) { + detector_type = X86_HARDLOCKUP_DETECTOR_PERF; + return ret; + } + + return 0; +} + +void watchdog_nmi_stop(void) +{ + /* Only the HPET lockup detector defines a stop function. */ + if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) + hardlockup_detector_hpet_stop(); +} + +void watchdog_nmi_start(void) +{ + if (!(watchdog_enabled & NMI_WATCHDOG_ENABLED)) + return; + + /* Only the HPET lockup detector defines a start function. */ + if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) + hardlockup_detector_hpet_start(); +} From patchwork Wed Mar 1 23:47:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63138 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3937604wrd; Wed, 1 Mar 2023 16:00:21 -0800 (PST) X-Google-Smtp-Source: AK7set+N+NogPKpCdmVGlgLzz7slEgDeK2e6lWZZ14O5ecnhuSjeLtbD1JpYtYz0AFBSqX3pCcWB X-Received: by 2002:a05:6a20:8e0d:b0:cb:f76c:e1a8 with SMTP id y13-20020a056a208e0d00b000cbf76ce1a8mr261782pzj.15.1677715221572; Wed, 01 Mar 2023 16:00:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677715221; cv=none; d=google.com; s=arc-20160816; b=UGfB5W60zryyDDCwU0czhBnW3z50tmJqmcQAhQlj0/aeY1ZUBBX8sNcZXX912CG48l +avFMLYOZt/tYhq4P8Yontx1sJOdyrcMuOTCBIqQeQj9/8mNc82KwT7ExqfMqHe6w5hR qRdop0/4gyLCz/wSvxFfrhtz6lw0rWqc9yMlWdlxlekIs1mRpUJivKoOju8q3Fbuhkmi WtzDQKZcbkOpS/NYuw14JVS3LuBNTm/gBwEkFDQntKy9TZX8Yy5a2ii6ecgT6oogfNlI qr+EumPJhw/BQl3579zjcru/aA4rPT3uIY4MKmmq5CeKy6/As2fM1GAm8QcvjFXhZd8j oVnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=T5zqcLZ4YQwidRgne/1vY1TACH4DLlwTpXxcTV9nGZk=; b=CkanA/lEY32ah9PvQqGlWRpheb6WozHx0HAaiujrIEp2VgDgFj9c3KkFvRyTbCw149 JPqbRiui980iIyE3zQy9MuBsxkLpPOmkwHcz+pa8+zcXklSlJtQVz61aYEl6Q9z/t2zk pKVeRZgbLN5fHB9DOL9IrN3Iu4gxxvnddwqrkrvgx4myL37tDDaji/OmJdEHhzm28FEd X6m4iHYSOMAvHlJw5pZk/GAI2kxM+SIguH/so2GDgDExXufBzDJNsRookIGHgBzgyTFJ aPxOWMPe5iES4mrFy+04EyvsuwX1GF9SJmUnY9gwwcoOfAI8Wmg7jzyxpjg7hjNnTTGZ SeiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CN9ZqS2A; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 23/24] watchdog: Introduce hardlockup_detector_mark_unavailable() Date: Wed, 1 Mar 2023 15:47:52 -0800 Message-Id: <20230301234753.28582-24-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759211916551955662?= X-GMAIL-MSGID: =?utf-8?q?1759211916551955662?= The NMI watchdog may become unreliable during runtime. This is the case in x86 if, for instance, the HPET-based hardlockup detector is in use and the TSC counter becomes unstable. Introduce a new interface to mark the hardlockup detector as unavailable in such cases. When doing this, update the state of /proc/sys/kernel/ nmi_watchdog to keep it consistent. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ricardo Neri --- Changes since v6: * Introduced this patch Changes since v5: * N/A Changes since v4 * N/A Changes since v3 * N/A Changes since v2: * N/A Changes since v1: * N/A --- include/linux/nmi.h | 2 ++ kernel/watchdog.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index a38c4509f9eb..40a97139ec65 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -83,9 +83,11 @@ static inline void reset_hung_task_detector(void) { } #if defined(CONFIG_HARDLOCKUP_DETECTOR) extern void hardlockup_detector_disable(void); +extern void hardlockup_detector_mark_unavailable(void); extern unsigned int hardlockup_panic; #else static inline void hardlockup_detector_disable(void) {} +static inline void hardlockup_detector_mark_unavailable(void) {} #endif #if defined(CONFIG_HAVE_NMI_WATCHDOG) || defined(CONFIG_HARDLOCKUP_DETECTOR) diff --git a/kernel/watchdog.c b/kernel/watchdog.c index 8e61f21e7e33..0e4fed6d95b9 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -47,6 +47,8 @@ static int __read_mostly nmi_watchdog_available; struct cpumask watchdog_cpumask __read_mostly; unsigned long *watchdog_cpumask_bits = cpumask_bits(&watchdog_cpumask); +static void __lockup_detector_reconfigure(void); + #ifdef CONFIG_HARDLOCKUP_DETECTOR # ifdef CONFIG_SMP @@ -85,6 +87,24 @@ static int __init hardlockup_panic_setup(char *str) } __setup("nmi_watchdog=", hardlockup_panic_setup); +/** + * hardlockup_detector_mark_unavailable - Mark the NMI watchdog as unavailable + * + * Indicate that the hardlockup detector has become unavailable. This may + * happen if the hardware resources that the detector uses have become + * unreliable. + */ +void hardlockup_detector_mark_unavailable(void) +{ + mutex_lock(&watchdog_mutex); + + /* These variables can be updated without stopping the detector. */ + nmi_watchdog_user_enabled = 0; + nmi_watchdog_available = false; + + __lockup_detector_reconfigure(); + mutex_unlock(&watchdog_mutex); +} #endif /* CONFIG_HARDLOCKUP_DETECTOR */ /* From patchwork Wed Mar 1 23:47:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 63137 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp3937114wrd; Wed, 1 Mar 2023 15:59:09 -0800 (PST) X-Google-Smtp-Source: AK7set9AG6/9nGVpfQ3HMNW43en8ssyB8xXxff/9ygD696YRSpwuIE0gAuGICOROggAcgDTnRz9X X-Received: by 2002:a17:902:da88:b0:19e:31a3:1a87 with SMTP id j8-20020a170902da8800b0019e31a31a87mr9599035plx.39.1677715149299; Wed, 01 Mar 2023 15:59:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677715149; cv=none; d=google.com; s=arc-20160816; b=j9Fr31ySoCHOmR2QFNt7yqOYGkbNrLG1ILbq3pBdSXIIaQrpKYyclDIk1F2TT/mlqe jtsuQjpJWIFRzk2n00DHbAaFpH+qyeuiLn438A2U/NP3G4EQVY5Eydqo/Nd95n7EZDfQ YZSErdGOnAkAjzpPD0qB895U0J77RcxLuaC3UBS7cLo8oR0Vsedj/ROLhhHpqMKjFEVF bBr/SvYjpY+Am+ppfnZtB+h4488pQN4YrR/O/nvesW+rf6ANbxM84Cgp5WLFfOA9cajl N+hZDvgMI3lGK2YusLLn2fbp3NdxXlVTp4jCArNtsM9kGF41wVcrCqYlIK5yX5h/711i TGSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=wiKXL8l/UR5Y+ypSAW02Dym97Q3YRfdOIwzMjhCqpHg=; b=UmKWRvZupel2Zi1DOu9mvJ+ZA5m8EyPCrKzsc1ZyjxgySTYkZYIwVo5dJqbQ2s+nVD oloy/dy4FISXOYTZ22QZUAls4hH26TooCylzSWr72wSRZNEMXIxtzQ7rpyH4lsRJU8Rl OQ+Hli5HdEgaska9l10OB+pK/AvPTyTv/DHvNfC1XLcC67wBBeQcY8QDRLfhIo0fno8t 6ntszDZAS+8pGGoDI0Vp4EfOkcYYh41XEykgUVwoqINUx1o+4LOS1+ODU5brLAFSqiuM qC3qyBue/Jgyex9c0EKKOQRLIcllYIh9lDDQ1OVSuyCsbOgBJwCq+ccwhn+9XypNmxvX +xJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=SSgWhUvX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Reinette Chatre , Dan Williams , Len Brown Cc: Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v7 24/24] x86/tsc: Stop the HPET hardlockup detector if TSC become unstable Date: Wed, 1 Mar 2023 15:47:53 -0800 Message-Id: <20230301234753.28582-25-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759211840280359586?= X-GMAIL-MSGID: =?utf-8?q?1759211840280359586?= The HPET-based hardlockup detector relies on the TSC to determine if an observed NMI interrupt was originated by HPET timer. Hence, this detector can no longer be used with an unstable TSC. Once marked as unstable, the TSC cannot be stable again. In such case, permanently stop the HPET- based hardlockup detector. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v6: * Do not switch to the perf-based NMI watchdog. Instead, only stop the HPET-based NMI watchdog if the TSC counter becomes unstable. Changes since v5: * Relocated the declaration of hardlockup_detector_switch_to_perf() to x86/nmi.h It does not depend on HPET. * Removed function stub. The shim hardlockup detector is always for x86. Changes since v4: * Added a stub version of hardlockup_detector_switch_to_perf() for !CONFIG_HPET_TIMER. (lkp) * Reconfigure the whole lockup detector instead of unconditionally starting the perf-based hardlockup detector. Changes since v3: * None Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/nmi.h | 6 ++++++ arch/x86/kernel/tsc.c | 3 +++ arch/x86/kernel/watchdog_hld.c | 11 +++++++++++ 3 files changed, 20 insertions(+) diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index 5c5f1e56c404..4d0687a2b4ea 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -63,4 +63,10 @@ void stop_nmi(void); void restart_nmi(void); void local_touch_nmi(void); +#ifdef CONFIG_HARDLOCKUP_DETECTOR +extern void hardlockup_detector_mark_hpet_hld_unavailable(void); +#else +static inline void hardlockup_detector_mark_hpet_hld_unavailable(void) {} +#endif + #endif /* _ASM_X86_NMI_H */ diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 344698852146..24f77efea569 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1191,6 +1191,9 @@ void mark_tsc_unstable(char *reason) clocksource_mark_unstable(&clocksource_tsc_early); clocksource_mark_unstable(&clocksource_tsc); + + /* The HPET hardlockup detector depends on a stable TSC. */ + hardlockup_detector_mark_hpet_hld_unavailable(); } EXPORT_SYMBOL_GPL(mark_tsc_unstable); diff --git a/arch/x86/kernel/watchdog_hld.c b/arch/x86/kernel/watchdog_hld.c index 33c22f6456a3..f5d79ce0e7a2 100644 --- a/arch/x86/kernel/watchdog_hld.c +++ b/arch/x86/kernel/watchdog_hld.c @@ -6,6 +6,8 @@ * Copyright (C) Intel Corporation 2023 */ +#define pr_fmt(fmt) "watchdog: " fmt + #include #include @@ -84,3 +86,12 @@ void watchdog_nmi_start(void) if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) hardlockup_detector_hpet_start(); } + +void hardlockup_detector_mark_hpet_hld_unavailable(void) +{ + if (detector_type != X86_HARDLOCKUP_DETECTOR_HPET) + return; + + pr_warn("TSC is unstable. Stopping the HPET NMI watchdog."); + hardlockup_detector_mark_unavailable(); +}