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[194.187.74.233]) by smtp.gmail.com with ESMTPSA id l2-20020ac25542000000b004d85a7e8b17sm1229550lfk.269.2023.02.27.23.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 23:29:46 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski Cc: Matthias Brugger , Kunihiko Hayashi , Masami Hiramatsu , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Rob Herring Subject: [PATCH V4 1/2] dt-bindings: nvmem: mmio: new binding for MMIO accessible NVMEM devices Date: Tue, 28 Feb 2023 08:29:35 +0100 Message-Id: <20230228072936.1108-2-zajec5@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230228072936.1108-1-zajec5@gmail.com> References: <20230228072936.1108-1-zajec5@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759059343446811278?= X-GMAIL-MSGID: =?utf-8?q?1759059343446811278?= From: Rafał Miłecki Content of some NVMEM devices can be read using MMIO. Some of them (probably very few though) may be also programmable that way. Add generic binding to allow describing such hardware. This *doesn't* apply to any more complicated devices that need more complex interface e.g. for writing. While such devices could be supported for reading purposes by the same driver - they should get their own binding. This binding will gain even more usability once we fully support NVMEM layouts (describing content of NVMEM devices in an independent way). Signed-off-by: Rafał Miłecki Reviewed-by: Rob Herring --- V3: Make it clear this binding should NOT be used for more complex devices --- .../devicetree/bindings/nvmem/mmio.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/mmio.yaml diff --git a/Documentation/devicetree/bindings/nvmem/mmio.yaml b/Documentation/devicetree/bindings/nvmem/mmio.yaml new file mode 100644 index 000000000000..9ca96b7a4856 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/mmio.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/mmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MMIO access based NVMEM + +description: | + This binding describes simple NVMEM devices with content that can be accessed + using MMIO (memory-mapped I/O access). + + More complex devices that support any other access than a simple memory + mapping should use a custom binding. In such cases this binding's compatible + should NOT be used even as a fallback. + + This binding is designed to describe just an NVMEM content access method. The + way of handling actual content should be described independently (on top of + this binding). + +maintainers: + - Rafał Miłecki + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + const: mmio-nvmem + + reg: + maxItems: 1 + + reg-io-width: + description: | + The size (in bytes) of the IO accesses that should be performed + on the device. + enum: [1, 2, 4, 8] + +required: + - reg + +unevaluatedProperties: false + +examples: + - | + nvmem@10000 { + compatible = "mmio-nvmem"; + reg = <0x10000000 0x10000>; + }; From patchwork Tue Feb 28 07:29:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 62316 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2870520wrd; Mon, 27 Feb 2023 23:35:41 -0800 (PST) X-Google-Smtp-Source: AK7set/ni+Qj/kh8B+L6053ryyT9zxBupB27i901IBBM7zaUcNxGcenTV97FvW/Ms+wZ+FK8nucD X-Received: by 2002:a17:906:58c5:b0:8f6:ad32:cd51 with SMTP id e5-20020a17090658c500b008f6ad32cd51mr2382002ejs.62.1677569741109; Mon, 27 Feb 2023 23:35:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677569741; cv=none; d=google.com; s=arc-20160816; b=pspAB2DmwIClxdFU58wKBL6OAqsSXHMbFUeJvUdclYPkILOL0UvJn7s5BbocQwqQ2C hlZzF1p0uzZAhKairVN1c7lxlzGTsmltjoERBkNVrqwVErttDv4/HpWk2ytr52WTn2N1 dcHEpiz6gUfWHntiI00NPYsOka7JAnlsQx90h2Ei9rtEGGrbn3cqCawc+Y7v7+Nu5Rz2 y4ycO8tfz/Hnr9beHmq++VIwRsYe5V5G0A4hIN0vsL8xdhmNmwavA+/9AE53NaopvmUV uxP1uBpkEQh1H5azgq2Jt3kvG2b9A3QKuO358PYBqppfHnko20nCP0Ojw8iaH765kBBO PZRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IsqApEBQlKEPGyVsiuZgMJvp51SjT+jXo8h7J6aTlqU=; b=fpEXBDAZAgZ4EOfGA3w17VCznGPsHYrtaZ+QHsNZv8jnbeGJdVO+1+f8aDz0pAlWNK B4WfcmEPk7SGlM5I5qB4qTEvUl1gqBjLoyDbjvPkXpcwKMQHbBcyLyw9LKYI5wUiJR6t svWlqW+jX/ir/LFzrT8lZXxQ9VkftWpTqHHv7Ll02OpmOGAgG6gAABJNdAQpzy3ujFhX ljLjVP2dKmoaMSnJ8u3+qqR+U55oczZBrFOeplzRoIIfjVfBe/4W68o5UPhxfb00Ny/5 A/Cq6QdPbA2uY0H6B20AXdyfFKkU2BLgCEkEolkwBmVoVfIlprXPpfL6BeGkr3EXDIkb QKUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=DBHZA2u5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[194.187.74.233]) by smtp.gmail.com with ESMTPSA id l2-20020ac25542000000b004d85a7e8b17sm1229550lfk.269.2023.02.27.23.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 23:29:47 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski Cc: Matthias Brugger , Kunihiko Hayashi , Masami Hiramatsu , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH V4 2/2] nvmem: add generic driver for devices with MMIO access Date: Tue, 28 Feb 2023 08:29:36 +0100 Message-Id: <20230228072936.1108-3-zajec5@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230228072936.1108-1-zajec5@gmail.com> References: <20230228072936.1108-1-zajec5@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759059368816576662?= X-GMAIL-MSGID: =?utf-8?q?1759059368816576662?= From: Rafał Miłecki Some NVMEM devices can be accessed by simply mapping memory and reading from / writing to it. This driver adds support for a generic "mmio-nvmem" DT binding used by such devices. One of such devices is Broadcom's NVRAM. It's already supported (see NVMEM_BRCM_NVRAM) but existing driver covers both: 1. NVMEM device access 2. NVMEM content parsing Once we get support for NVMEM layouts then existing NVRAM driver will get converted into a layout and generic driver will take over responsibility for data access. Signed-off-by: Rafał Miłecki --- V3: Support "reg-io-width", basic writing & "brcm,nvram" string V3: Don't duplicate core checks, add 64 b support, complete writing support, don't add confusing conditional "brcm,nvram" support (it will be handled with layouts migration) --- drivers/nvmem/Kconfig | 10 +++ drivers/nvmem/Makefile | 2 + drivers/nvmem/mmio.c | 148 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 160 insertions(+) create mode 100644 drivers/nvmem/mmio.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 6dec38805041..189ea85bd67d 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -166,6 +166,16 @@ config NVMEM_MICROCHIP_OTPC This driver enable the OTP controller available on Microchip SAMA7G5 SoCs. It controls the access to the OTP memory connected to it. +config NVMEM_MMIO + tristate "MMIO access based NVMEM support" + depends on HAS_IOMEM + help + This driver provides support for NVMEM devices that can be accessed + using MMIO. + + This driver can also be built as a module. If so, the module + will be called nvmem-mmio. + config NVMEM_MTK_EFUSE tristate "Mediatek SoCs EFUSE support" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 6a1efffa88f0..767a9db2bfc1 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -35,6 +35,8 @@ obj-$(CONFIG_NVMEM_MESON_MX_EFUSE) += nvmem_meson_mx_efuse.o nvmem_meson_mx_efuse-y := meson-mx-efuse.o obj-$(CONFIG_NVMEM_MICROCHIP_OTPC) += nvmem-microchip-otpc.o nvmem-microchip-otpc-y := microchip-otpc.o +obj-$(CONFIG_NVMEM_MMIO) += nvmem-mmio.o +nvmem-mmio-y := mmio.o obj-$(CONFIG_NVMEM_MTK_EFUSE) += nvmem_mtk-efuse.o nvmem_mtk-efuse-y := mtk-efuse.o obj-$(CONFIG_NVMEM_MXS_OCOTP) += nvmem-mxs-ocotp.o diff --git a/drivers/nvmem/mmio.c b/drivers/nvmem/mmio.c new file mode 100644 index 000000000000..ce51648bb321 --- /dev/null +++ b/drivers/nvmem/mmio.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Rafał Miłecki + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct mmio_nvmem { + void __iomem *base; + u32 io_width; +}; + +static int mmio_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes) +{ + struct mmio_nvmem *priv = context; + u64 __maybe_unused *dst64; + u32 *dst32; + u16 *dst16; + u8 *dst8; + + switch (priv->io_width) { + case 0: + memcpy_fromio(val, priv->base + offset, bytes); + break; + case 1: + for (dst8 = val; bytes; bytes -= 1, offset += 1) + *dst8++ = readb(priv->base + offset); + break; + case 2: + for (dst16 = val; bytes; bytes -= 2, offset += 2) + *dst16++ = readw(priv->base + offset); + break; + case 4: + for (dst32 = val; bytes; bytes -= 4, offset += 4) + *dst32++ = readl(priv->base + offset); + break; +#ifdef CONFIG_64BIT + case 8: + for (dst64 = val; bytes; bytes -= 8, offset += 8) + *dst64++ = readq(priv->base + offset); + break; +#endif + default: + return -EINVAL; + } + + return 0; +} + +static int mmio_nvmem_write(void *context, unsigned int offset, void *val, size_t bytes) +{ + struct mmio_nvmem *priv = context; + u64 __maybe_unused *dst64; + u32 *dst32; + u16 *dst16; + u8 *dst8; + + switch (priv->io_width) { + case 0: + memcpy_toio(priv->base + offset, val, bytes); + break; + case 1: + for (dst8 = val; bytes; bytes -= 1, offset += 1) + writeb(*dst8++, priv->base + offset); + break; + case 2: + for (dst16 = val; bytes; bytes -= 2, offset += 2) + writew(*dst16++, priv->base + offset); + break; + case 4: + for (dst32 = val; bytes; bytes -= 4, offset += 4) + writel(*dst32++, priv->base + offset); + break; +#ifdef CONFIG_64BIT + case 8: + for (dst64 = val; bytes; bytes -= 8, offset += 8) + writeq(*dst64++, priv->base + offset); + break; +#endif + default: + return -EINVAL; + } + + return 0; +} + +static int mmio_nvmem_probe(struct platform_device *pdev) +{ + struct nvmem_config config = { + .name = "mmio-nvmem", + .id = NVMEM_DEVID_AUTO, + .read_only = true, + .reg_read = mmio_nvmem_read, + .reg_write = mmio_nvmem_write, + }; + struct device *dev = &pdev->dev; + struct mmio_nvmem *priv; + struct resource *res; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + of_property_read_u32(dev->of_node, "reg-io-width", &priv->io_width); + + config.dev = dev; + config.size = resource_size(res); + config.word_size = priv->io_width; + config.stride = priv->io_width; + config.priv = priv; + + return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config)); +} + +static const struct of_device_id mmio_nvmem_of_match_table[] = { + { .compatible = "mmio-nvmem", }, + {}, +}; + +static struct platform_driver mmio_nvmem_driver = { + .probe = mmio_nvmem_probe, + .driver = { + .name = "mmio_nvmem", + .of_match_table = mmio_nvmem_of_match_table, + }, +}; + +static int __init mmio_nvmem_init(void) +{ + return platform_driver_register(&mmio_nvmem_driver); +} + +subsys_initcall_sync(mmio_nvmem_init); + +MODULE_AUTHOR("Rafał Miłecki"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, mmio_nvmem_of_match_table);