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Client device can insert a wait state on MISO when address is trasmitted by controller on MOSI. It can work only on full duplex. Half duplex controllers need to implement flow control in HW. Add a flag for TPM to indicate flow control is expected in controller. Signed-off-by: Krishna Yarlagadda --- include/linux/spi/spi.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 988aabc31871..b88494e31239 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -184,8 +184,9 @@ struct spi_device { u8 chip_select; u8 bits_per_word; bool rt; -#define SPI_NO_TX BIT(31) /* No transmit wire */ -#define SPI_NO_RX BIT(30) /* No receive wire */ +#define SPI_NO_TX BIT(31) /* No transmit wire */ +#define SPI_NO_RX BIT(30) /* No receive wire */ +#define SPI_TPM_HW_FLOW BIT(29) /* TPM flow control */ /* * All bits defined above should be covered by SPI_MODE_KERNEL_MASK. * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart, @@ -195,7 +196,7 @@ struct spi_device { * These bits must not overlap. A static assert check should make sure of that. * If adding extra bits, make sure to decrease the bit index below as well. */ -#define SPI_MODE_KERNEL_MASK (~(BIT(30) - 1)) +#define SPI_MODE_KERNEL_MASK (~(BIT(29) - 1)) u32 mode; int irq; void *controller_state; From patchwork Fri Feb 24 15:49:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 61387 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp990068wrd; Fri, 24 Feb 2023 08:00:37 -0800 (PST) X-Google-Smtp-Source: AK7set8tWjDBRQ0owu045TtKNwFIzzifb9c0zp4gNjT4H6VxTSqzKFhM591Mwgm2UvoI1CfYB6Mb X-Received: by 2002:a17:903:70c:b0:19c:d0c9:8ff6 with SMTP id kk12-20020a170903070c00b0019cd0c98ff6mr2825308plb.60.1677254437218; Fri, 24 Feb 2023 08:00:37 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1677254437; cv=pass; d=google.com; s=arc-20160816; b=SjItygCR3kYkXoJyA/0R+cRcJNYgjS8zHaTz5kMYI2EBDJOpY7J6aZs1rjx2vJb287 XgtPwP0lxHEG/HbIvp/O34HVFUkjsUfCBDp/ACr1dSJQQ5S7hPmAuO+wpnyzy8OXvwYu HCZw9/fvoi9AZsjtGxomJwokOTUWF12Tcctldc4+Kdket5JiQ7ndBdFuDfQg427Dr00q SpZd3oak3NTRyVnTCCTGQl7veP+zkgNV/sNTnQcNPpXTtvunbJb5RUutgy1W3U2koh47 ZwVfAtiPpUbu9k2Rsl9DuyeuJC+wi5vZKfZEJXRqViiw8LqH+p3pejCclldIuQ6c/UV1 QLZg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=YzD8z7HwK+9VBLftUFJPu9vmJRdUl869K7Fizq2RcOc=; b=Sepfc+Vbgy/J9RQASRWx6dCW3X6fG7XS9bGsYNi/x02NrpqRaVwgQhbyU1iPa4QC6s X3hc5jWxyG4wegXrl+Kj1CnVmlX+UcwB7Kkjf4vNJEhLdj9pJgXsG8lmTIlMSLuTZbQv G+18cqLjkvy+svFqdeZxkQr8qTsAwBlINjqKTzbiua3RH5TvDaHIf3+g1H6Fw4y6PpXl wfE6uDozGm7VeNgx8O1Imz/DoflZOaMamIhQZxP4RTk73RwzN2aLZADijPSSXcOtioZl 8bn/stKOIZCC30DpkGoDRn31kVRm/VAdeujmq2DNVEvumn1CDAqtU3PDwo7qlShYVzn/ JrWQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Ymm7gUDp; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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This can be detected by software driver by reading MISO line on same clock which requires full duplex support. In case of half duplex controllers wait detection has to be implemented in HW. Support hardware wait state detection by sending entire message and let controller handle flow control. QSPI controller in Tegra236 & Tegra241 implement TPM wait polling. Signed-off-by: Krishna Yarlagadda --- drivers/char/tpm/tpm_tis_spi_main.c | 96 ++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/char/tpm/tpm_tis_spi_main.c b/drivers/char/tpm/tpm_tis_spi_main.c index a0963a3e92bd..b193c950f133 100644 --- a/drivers/char/tpm/tpm_tis_spi_main.c +++ b/drivers/char/tpm/tpm_tis_spi_main.c @@ -71,8 +71,78 @@ static int tpm_tis_spi_flow_control(struct tpm_tis_spi_phy *phy, return 0; } -int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len, - u8 *in, const u8 *out) +/* + * Half duplex controller with support for TPM wait state detection like + * Tegra241 need cmd, addr & data sent in single message to manage HW flow + * control. Each phase sent in different transfer for controller to idenity + * phase. + */ +int tpm_tis_spi_hw_flow_transfer(struct tpm_tis_data *data, u32 addr, u16 len, + u8 *in, const u8 *out) +{ + struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); + struct spi_transfer spi_xfer[3]; + struct spi_message m; + u8 transfer_len; + int ret; + + spi_bus_lock(phy->spi_device->master); + + while (len) { + transfer_len = min_t(u16, len, MAX_SPI_FRAMESIZE); + + spi_message_init(&m); + phy->iobuf[0] = (in ? 0x80 : 0) | (transfer_len - 1); + phy->iobuf[1] = 0xd4; + phy->iobuf[2] = addr >> 8; + phy->iobuf[3] = addr; + + memset(&spi_xfer, 0, sizeof(spi_xfer)); + + spi_xfer[0].tx_buf = phy->iobuf; + spi_xfer[0].len = 1; + spi_message_add_tail(&spi_xfer[0], &m); + + spi_xfer[1].tx_buf = phy->iobuf + 1; + spi_xfer[1].len = 3; + spi_message_add_tail(&spi_xfer[1], &m); + + if (out) { + spi_xfer[2].tx_buf = &phy->iobuf[4]; + spi_xfer[2].rx_buf = NULL; + memcpy(&phy->iobuf[4], out, transfer_len); + out += transfer_len; + } + + if (in) { + spi_xfer[2].tx_buf = NULL; + spi_xfer[2].rx_buf = &phy->iobuf[4]; + } + + spi_xfer[2].len = transfer_len; + spi_message_add_tail(&spi_xfer[2], &m); + + reinit_completion(&phy->ready); + + ret = spi_sync_locked(phy->spi_device, &m); + if (ret < 0) + goto exit; + + if (in) { + memcpy(in, &phy->iobuf[4], transfer_len); + in += transfer_len; + } + + len -= transfer_len; + } + +exit: + spi_bus_unlock(phy->spi_device->master); + return ret; +} + +int tpm_tis_spi_sw_flow_transfer(struct tpm_tis_data *data, u32 addr, u16 len, + u8 *in, const u8 *out) { struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); int ret = 0; @@ -140,6 +210,28 @@ int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len, return ret; } +int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len, + u8 *in, const u8 *out) +{ + struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); + struct spi_controller *ctlr = phy->spi_device->controller; + + /* + * TPM flow control over SPI requires full duplex support. + * Send entire message to a half duplex controller to handle + * wait polling in controller. + * Set TPM HW flow control flag.. + */ + if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX) { + phy->spi_device->mode |= SPI_TPM_HW_FLOW; + return tpm_tis_spi_hw_flow_transfer(data, addr, len, in, + out); + } else { + return tpm_tis_spi_sw_flow_transfer(data, addr, len, in, + out); + } +} + static int tpm_tis_spi_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len, u8 *result, enum tpm_tis_io_mode io_mode) { From patchwork Fri Feb 24 15:49:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 61388 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp990443wrd; Fri, 24 Feb 2023 08:01:08 -0800 (PST) X-Google-Smtp-Source: AK7set9+tatLqUFXto3mvklBYlHC6BRNKC19coDTsiVSuWzeIpIpa4Smjr32Ux2Va73e47k4ix8W X-Received: by 2002:a17:90b:4d8e:b0:237:b121:670b with SMTP id oj14-20020a17090b4d8e00b00237b121670bmr612252pjb.7.1677254468114; Fri, 24 Feb 2023 08:01:08 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1677254468; cv=pass; d=google.com; s=arc-20160816; b=JPZG1NZyHqHyH1Q9oxdlHNGmr5bi+u7JTcIrWWgIZM7dQIF3NR3Mbhg/M7ynkEggFi NGUeo56qn4r3Tm3pN4R6ctWrc4W9bebaABgOlogS2J70opHwjwMfow7FTS5TbHzdHeIH +gpQqivE+AZcw0hTU5mwrgmxSMlzdgc+wYQGl3zgCE7TKskQMKi8lFpymt65zpAd8Bnw E9O485CnnTpgfebD3DGNk+m12Ezp2iX6ZKA8F9Sf1db2k86vtOzsaUNpKIGYE+hdc8V4 r3JvSnJdeZ3s0MPDSf/nVMBblJDADHn791GuCEUl5Sxw81ff/vsbXyF+7rJTlSkV5X/a rCUg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=16STglZTI/DGYdzA7sqcyZCgku+uxhdaj2buTCIKCMo=; b=PzrnfjDfk29py3LgaGroFb8Xzkkvu8hzeEmyc/2Ry7fDC+ISQH7YK7sOxmVsT0OpMS Mw860T6OL9lF0NZ0dcSUR99kEPqkj6xwTXFsIiidE3yBGAR60cTml7anjoeM4drtyQ/p lMFliXszwfK23qIGs4zpEFpJS2x28fwN2NMht0VOFfx/qe1oFRJIOj+gCn/rXNHSYlW3 upCvDK/1wZNMG50Fp2opHCw79i83380AGsUxKJlhXeemZCeXI2SESFaWlG64oKYyL4G0 Mgf7kO6f/ZerxgPwsPEfjf8K64vBUumLuQngs4dP4TANa7LaXPsQn9VrgBZnoqkts2Ad E2ng== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=QWgAUzAj; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Set half duplex constrain flag. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 39dec2dc161b..fe15fa6eecd1 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1553,6 +1553,7 @@ static int tegra_qspi_probe(struct platform_device *pdev) master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH | SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8); + master->flags = SPI_CONTROLLER_HALF_DUPLEX; master->setup = tegra_qspi_setup; master->transfer_one_message = tegra_qspi_transfer_one_message; master->num_chipselect = 1;