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[2620:137:e000::1:20]) by mx.google.com with ESMTP id fh6-20020a1709073a8600b008d8279dfbe0si12727910ejc.651.2023.02.24.03.01.39; Fri, 24 Feb 2023 03:02:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xMS93kYt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229504AbjBXLAY (ORCPT + 99 others); Fri, 24 Feb 2023 06:00:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230192AbjBXK7u (ORCPT ); Fri, 24 Feb 2023 05:59:50 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD8A864E16 for ; Fri, 24 Feb 2023 02:59:20 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id m8-20020a17090a4d8800b002377bced051so2550165pjh.0 for ; Fri, 24 Feb 2023 02:59:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7g1uqAd+GBvLWxylp13ChAu3aZ2qmP9sP5D+Fm30PJ4=; b=xMS93kYtTEWQdbX6qfOwCbcRYIGnoaDf2QJDnzsBG1pI8dHP/gX61gX4fLgH/twQzJ /XYaG0UG2ZbcmamgvygW+VMhACiR0ijaXbGnqHdojoFsXmF1pUX+yOkQGUqG2hKUdOE1 Yluzn+n+d81WXnsnHRCJmIuo2lvf+6VzZzYvcRHDXhF9I7+gv7ARITZ57947CHWinHn7 fi2BhJDcGjuwrKoVxcrJ4r8zbaBTpKm83kP5a28aqeRygtjRVQzRssVxqNtrTnS7FjtS 5pclT3FRd82lh5EuexCw1XznkKdhrrd2yv1XHxfaeZ7RqTU/l7gDAaWGEnGhCmu64iOA us+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7g1uqAd+GBvLWxylp13ChAu3aZ2qmP9sP5D+Fm30PJ4=; b=ffuOqC+QPMMaHpC0BmT61/fXl/64QWDD0xnbv7a2LdnK6XiPZVX4GVbEwF6hy23BZR tTatq+ncUKRWQN0YaqegDEyB1YGFWFLNE+dFrAw4RUVat0RoYJL9HvrxMNw3Msl0gCbD zKsYyXFsTnpEgyQAcYxPi6P7rBPiXbnEIdEhsIy47HL2Zj4vW0AUb+QQDaOjuBXOc89q eRjNk22eVS8vgKjq7vgNg/8Df3gNLAiQlBf6FpDH/tUB3dId0GF/VIAXo4TwquMWl2hp h5rcep7t4LFD12mATNh26TZuC7Nh6V0cXVANrw9UVvg/OktzDlmMOkh0V+ZUhArktQ4M p1xg== X-Gm-Message-State: AO0yUKUeBOvi6FSB5QhNVOaNtyRzprVtGiVBR9ufIkvW/JNkvsvsDe1I gMyupJsUdblfZple7foSr54S X-Received: by 2002:a17:90a:188:b0:237:3dfb:9095 with SMTP id 8-20020a17090a018800b002373dfb9095mr9674382pjc.6.1677236360228; Fri, 24 Feb 2023 02:59:20 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.02.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 02:59:19 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v2 01/13] dt-bindings: PCI: qcom: Update maintainers entry Date: Fri, 24 Feb 2023 16:28:54 +0530 Message-Id: <20230224105906.16540-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758709963452190434?= X-GMAIL-MSGID: =?utf-8?q?1758709963452190434?= Stan is no longer working with MMSOL and expressed his interest to not continue maintaining Qcom PCIe driver. Since I took over the driver maintainership, I'm stepping in to maintain the binding also. Acked-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a5859bb3dc28..a3639920fcbb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex maintainers: - Bjorn Andersson - - Stanimir Varbanov + - Manivannan Sadhasivam description: | Qualcomm PCIe root complex controller is based on the Synopsys DesignWare From patchwork Fri Feb 24 10:58:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61267 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp837989wrd; Fri, 24 Feb 2023 03:03:23 -0800 (PST) X-Google-Smtp-Source: AK7set8IYLKTvPqWxicpPiqgZZwUU/sR+9Y/Epod5i0eZUcPzJI6LYAZGMJeGUeHsHXdH3eFmlJa X-Received: by 2002:a05:6402:48b:b0:4af:70a5:43ff with SMTP id k11-20020a056402048b00b004af70a543ffmr4443748edv.26.1677236603623; Fri, 24 Feb 2023 03:03:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677236603; cv=none; d=google.com; s=arc-20160816; b=ThHSL4yQIgQrzsOzKl2s0CGUafEq9CFJekxAQGEY6UofoDWHKH48cU1Nv624e2vjuP DrgJ5p1yTSCcUtdnOY9wXBLdLMnj+R5l9XHNBxnGzZPj4zbLADuMxMx0X43vbTwxDH2C gVd3YjShR79xmlRSyDY11WQrGa8RJAzQ0ZOAMcTLerCo9f7Z/5Ka4T85DXCMHkegw28e wTz4BB0jZids/gaFORFLj+5NKPrDEm37+DGvPYe5SC/bYM3tSkKnVdxjF1j+uwnuQUXk Vh1FejbPu/mBL+VPKlFza8o0McIXZPhalWrPGqo9Ms+bkIRmdk4zoTZ/2qVnUU6R/kce aQnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uGDet0K+1/m01Mue6GMZv5iNZBwdpYi4DRLEmHhKT40=; b=aoFS7O2dhbBxPgInGMqs4c/BXLSKvs/4jtdiTQLIF185rtcMGgsZ38jHgF1+i4XwCP sqxEw7IbnndXnouLvcC+KZ4QgMohW5p24gOhYxobHExC/uED+EPJgE0H7Zn8FEwZYCj+ DRbLvK0dC9DuNkgzZIiQyaDNyaiQBocNAFPNZUdP6lBOVBFC17b9kaPvUXosrNhkkfwG BRNkgqN22xmOZ8zlxIzptTqTfl5/CC7+T54OfXHMRcRCP6hf9O+YGqZ6QqAAnQAF2qnS 0F56ukksm1mAaaPWB7q2UbYmzt4ZhvCQvxb/1q6JBxIcc8KtyBY/gZWRcs+/IwQO4z0W 8hxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wzykzWTL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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So let's add them to the binding. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a3639920fcbb..f48d0792aa57 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -64,6 +64,11 @@ properties: dma-coherent: true + iommus: + maxItems: 1 + + iommu-map: true + interconnects: maxItems: 2 From patchwork Fri Feb 24 10:58:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61268 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp838086wrd; Fri, 24 Feb 2023 03:03:34 -0800 (PST) X-Google-Smtp-Source: AK7set/wKlg9PZiruAYaSh2VCfYDWjyxyyQkK3yJOuvAdnoOuBYNtZSDGVr+ir1vNAdIYfhmGuPz X-Received: by 2002:a17:907:8c89:b0:8b1:779c:a8b1 with SMTP id td9-20020a1709078c8900b008b1779ca8b1mr29627239ejc.5.1677236614118; Fri, 24 Feb 2023 03:03:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677236614; cv=none; d=google.com; s=arc-20160816; b=jjc4vj8KOFWsj0/T7ufxE2t33fybw2bV9hxqRjadIn/KAiuEyHLqHJjgVKPWKoS5n8 WIGIc68XtVSyum4DFujlSWo+Xx0FOroO6sH7xTFch0uaJA0f3nDi6sYmrPwIALC4N2wl Vmm9hPMjWzoiBCUdj8QixDNGYlMNsSmb5HsE7GMGjvbIxBq/jnv2wWxhtZDWern//AWk 7mLgTc8PkM67g2p3jBtXVoAQv8VcSgNXkys4z2lhNu72PBuxr0qaYWkuwlLAb7ZNrH4g 34ouXIt2+WmT9RdWsTPT+EmtNL7E1azITCCfEOdsOLJEbIKFWPs+KQZA2rEl9LxBccpC u7tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wzdP0f8Dd/LfcCPdQr780PzK2RvZAJKB5vPc2XD3ufA=; b=a2GGLWP4sXQOVTtR97i/MkO3MST5aCg3qyNPu20vyPoGqaqpoELies9zKifUUyNX6p OiyLewjrHgSiIpAL/3pErpOuCzwrEq/gRWEJbJ8r6h2cox48Njy2cO+pxL3yXPU4bYeA +tq78ibNHZNVefVOt9fGfNHnpnGaNYaTmeRJl4Ir4j1ZJJm2xysRxCaMGhOrvcN1xv2P MHo/dG6zsTRlLhX53XK1TlAQp6gUArlcmlse1QgEOW6671lKKJl98wdevbLo0JMiGcE2 5+zxMohARysy2dEkonP2lmFPfMLhZi2Ff+Ez0MUtdVeU9yAmZgtsnN0VbUM7Pz8k/INs fr7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mByJV+Ja; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pci/qcom,pcie.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index f48d0792aa57..3bba1ef3cff5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -30,6 +30,7 @@ properties: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdm845 + - qcom,pcie-sdx55 - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 @@ -199,6 +200,7 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sc8280xp + - qcom,pcie-sdx55 - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 @@ -646,6 +648,32 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sdx55 + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: sleep # PCIe Sleep clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: properties: compatible: From patchwork Fri Feb 24 10:58:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61262 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp837422wrd; Fri, 24 Feb 2023 03:02:28 -0800 (PST) X-Google-Smtp-Source: AK7set+hYjLw4QDiYG4H/l7KNUCYDHS0Jd5mbW8C2uXDuQRSbsH0P34V7JRU33dNmg0uP/mq9vwV X-Received: by 2002:aa7:d281:0:b0:4ab:16a8:bc61 with SMTP id w1-20020aa7d281000000b004ab16a8bc61mr14949550edq.23.1677236548193; Fri, 24 Feb 2023 03:02:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677236548; cv=none; d=google.com; s=arc-20160816; b=iMqq+nEclFUUSaiVlGtvotifVoqhynW1+uPA9mf2jjMZpm6RVard1444L+F+TD0bu3 SLIQuQIjXcoogYa9Aa8FHJlx7AK0u5EHexQXP1zaR/reiVQwhjCAkrF5Fr5ROUyUiHtn /6qek4m52HL7XPRYA9Sn60W/7Dqxiou8KG4D+hV3FEd3Ps05XifN6Iyi8nPvsxFcumYR fahdhN8K1kGvS+PBlMm80lvLy22x7baB4H/l9p4xoa+eRUm7CriuPjHFAcdBPVKW3L6Q WwUdgQFp85k36ZAmTLdu3nhK4wKEuf7yJwKVPOl5f0CDLbOckaE+CXgHJexqXE1GgSBG BQog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VslRr6K7dtSVjJZa6fQapZMGTntHaQJdO/Shpvvg0kE=; b=R+2au8xsS400PIBTtola4Xbz+nyOIhh5uyllHtKc53z2y6BcfnRh+0qOnS8bWyP1Th B1P+GII66GUrBnV7BB0FHQcYU+jpflVB8gAhHTav3z0xEbjCMkwXWIvb3HoGzu38CF+Q Nh2uc7vmlBGtr7MCsmwab0evEU/6u04sxEv1hycgwR6ngU2wARD6Yij3H/9tJNMP4JBD eQ2OANNH7TEf84/eraHQTYUuwggz919Q3PWZ17P/ftE/hFjIDreKIAAjWGPtllC8HUhX JfsefSrxkiNhoxWMxqK8KcH1WYyyDYe76B77LgJI3iByL3ton0XGgAAJ1kw8fMHOckt1 U0rA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MGOUmbwJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Fixes: 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 8d7eb51edcb4..c1800e44f3da 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -164,7 +164,7 @@ examples: #include #include #include - pcie_ep: pcie-ep@40000000 { + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, <0x40000000 0xf1d>, From patchwork Fri Feb 24 10:58:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61263 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp837449wrd; Fri, 24 Feb 2023 03:02:32 -0800 (PST) X-Google-Smtp-Source: AK7set/4JAZpOWiyIbdQtVW3JiYIwu+6ODLSfcQCYejXwPXuYcmT+Dc+iFvnqS2CeokBOVXOX5WO X-Received: by 2002:a17:906:fb07:b0:8b1:7857:2331 with SMTP id lz7-20020a170906fb0700b008b178572331mr29554596ejb.65.1677236552082; Fri, 24 Feb 2023 03:02:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677236552; cv=none; d=google.com; s=arc-20160816; b=jFNqa4+vNBXQD5bEoYk+MPgQiUsTWPqH21P5bkaDaLZn5ddTnkPqt9dKL8Eun4H+HB sMVAg8xnOxs/2+iZzRyMro8ZJCsTSzTZddxswpmR5afgBWjwINIbzNkjHo8FCqJuGTQh v4y4lt0sTSPV7A4VIi5O72i99neizleWZ/fo2iZd1HfAZcrqzyx1ev9Gho/VkwQza0y/ iZ9VMRgHwevohwqT9+4aISiCWjNB6W0syImhBc76Ac/0OUZ4Yp/zkYob0VpAXCFZDVBl e8nLxxMD9lSbGgy/Ek2j65/26Q1wsQ1luixGKMyo/4idI8MdyDVp5snvDq9YHFB9OIyK UjqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HWzirrIvAlApajl/8IV1ns6ZR5N3zHdUYEWFW4EUTxg=; b=M70o15EY1fFAFpJXx1r83yiYskbaaQOw9pgFbhiJWwRDNnc8+k7fY8QjINAfFlyKvr UzHkdvlKRSweAIwdzt+uvUmt9V+CQ0IiAZ4BN7lchOmz3r4tcw5efZySwGXMABImtYTy SzeUjBvV/Qli3CjEcYz9VBclN4Dus6+fCL/TaGW5VbfEVbQgfSzhZvquudiaJ1AgtS9E ytSeE+TSCILx5FcGzKiCR/5hJZJBu4pHyyqUGA4KjpBODA+mY3B/1yexLTUthZnEmPzZ KLVXFKLKHG7y0naU6xxv+7+p0Bg+OIGXTI7OCFo+6KHL16YREFZpd+hQn0PI+g7SjIH6 Ubbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WgOeZtrM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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This also requires sorting the node in the ascending order. Fixes: e6b69813283f ("ARM: dts: qcom: sdx55: Add support for PCIe EP") Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 78 +++++++++++++++---------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 93d71aff3fab..e84ca795cae6 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -303,6 +303,45 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; @@ -400,45 +439,6 @@ sdhc_1: mmc@8804000 { status = "disabled"; }; - pcie_ep: pcie-ep@40000000 { - compatible = "qcom,sdx55-pcie-ep"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, - <0x40200000 0x100000>, - <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio"; - - qcom,perst-regs = <&tcsr 0xb258 0xb270>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; - - interrupts = , - ; - interrupt-names = "global", "doorbell"; - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; - phy-names = "pciephy"; - max-link-speed = <3>; - num-lanes = <2>; - - status = "disabled"; - }; - remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; From patchwork Fri Feb 24 10:58:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61264 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp837603wrd; Fri, 24 Feb 2023 03:02:47 -0800 (PST) X-Google-Smtp-Source: AK7set+s89rXLZiUy8RpP5KIkBDICsdaZNTBIw9J6+0RsER/eMcJDenJkn1s7o4eKNy4Oup+eNyD X-Received: by 2002:a05:6402:6d1:b0:4af:593c:c06f with SMTP id n17-20020a05640206d100b004af593cc06fmr12611431edy.11.1677236567298; Fri, 24 Feb 2023 03:02:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677236567; cv=none; d=google.com; s=arc-20160816; b=ufK0x2KbUpVTt2G1CvD+UL9iK6J9z+TKBeGlr4KKZw9ssWKhsRojPlocIsgIkQTItF qI5nLqrIj+e/mf5pmrGA+Jwu0I9Lh4ZKWru3RkkES5y6nAy+9PmJvCyFdyouW+5B0IE6 bwVAf1M0Fl5g3dFjtEX5zIoWBF7n898Nx65JMVOJn0j0oi2GnFCSAPU6cglPsZioQuQd 6bqr5Ud1Yfh0S9YkhIv00d8kd2aCINl80cq+QvHmQ8eCh8C9NbS7syjZ+A+NVe8H/xDw w0nBvP8K92Im1j0dbbG1cYNDy98pdxXrkQeJCFxnNjrSKISaan3qN2ZsmoT1OVxpV7kd BSMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0M8kYEAz7MzsWNWHJToSlMHPi/nWVr288+AKYIv+MWQ=; b=rvV61G4NkTK3YjYFUrmdncUdgz8iA4o5Lgms4scAdOm5CtfcE9rfiUdSXzY7pv24ha ZZI9zzXxFDXCFN4hdswWaP5Tc4YTL5AK/P8dlgIgwHcAnZiw/TJATITkR7A+SvTYRQFr aolhEtSnUfCnmIWHrg76YBqpnXABzXeuaLlPneGfBWmNmzMU85xczXW4mJ5XJRxjKnfg zo/Fn1R/lzfU8TC+cfeTgWim7H0FFkhGUssF4761aLQg9fEHxP30zTGqRLLG6UFQZ+Lp wuRsJTt7mmyyhsGMbWh+0kdTb61p+bERuv1zVlLXA3PgMUmt2mdY/gkBTteMsX1aiDHh Hcvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SL27Mr2E; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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This also matches the naming convention of the PCIe controller. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 2 +- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index ac8b4626ae9a..b7ee0237608f 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -242,7 +242,7 @@ &ipa { memory-region = <&ipa_fw_mem>; }; -&pcie0_phy { +&pcie_phy { status = "okay"; vdda-phy-supply = <&vreg_l1e_bb_1p2>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index e84ca795cae6..a1f4a7b0904a 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -334,7 +334,7 @@ pcie_ep: pcie-ep@1c00000 { resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie_lane>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; @@ -342,7 +342,7 @@ pcie_ep: pcie-ep@1c00000 { status = "disabled"; }; - pcie0_phy: phy@1c07000 { + pcie_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; #address-cells = <1>; @@ -362,7 +362,7 @@ pcie0_phy: phy@1c07000 { status = "disabled"; - pcie0_lane: lanes@1c06000 { + pcie_lane: lanes@1c06000 { reg = <0x01c06000 0x104>, /* tx0 */ <0x01c06200 0x328>, /* rx0 */ <0x01c07200 0x1e8>, /* pcs */ From patchwork Fri Feb 24 10:59:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61265 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp837634wrd; Fri, 24 Feb 2023 03:02:49 -0800 (PST) X-Google-Smtp-Source: AK7set9vpEGZw9Azgmq1EEo0+O9OVw5VLUMktjYpUsiCELQE53cZoAAbcgmCZ8hbM18esNS1UWkF X-Received: by 2002:a17:906:9508:b0:878:6477:d7 with SMTP id u8-20020a170906950800b00878647700d7mr19701003ejx.72.1677236569360; Fri, 24 Feb 2023 03:02:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677236569; cv=none; d=google.com; s=arc-20160816; b=CG0+LNzUjkviQ720UOPc/fmb/Qvch5oLglcC9jguc6NKePyRoepZuJAZUKkUZt43e8 36P4ip/lzKtLHG9KDE0TICrutCU4eQGsDbN2VP4n9p7ENYRoxxFHba/JicOyAD5R7Pao 9QTBWS/cvkDlBeBdEMlS3u58T2xGRlBjCHWOqm2/MM2yYNF36UpyPvcY2eogCmY9QVU+ 8LYdKIET+0fxyDjbd3VNFQ63EUI2nH/gVCAGAWg6w9fT2ewXSUtvYWzp7b61hxw0H3JA 5msMCq73azlgB4//WPrjmeq7FU1k+m9TSqW2/GqEWN/fGK+4d19qmrEhnV2X5oFSiTTS NTJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=P6vfCv6t5vjN1sjFyDIdqOCzfNDFUx2i/y3YhWTxhes=; b=FcpvgrJLbJfPDD6+ShDb4pE1oX4AiF3UGN5VVAaim08haCmnHfOMjAarCsRrSp/2nt c4YJKJArptmpKbH1Ms428JF/ggyXqz7l6nP/YVhDEex3gvGGWqnYsQyb3fThUZIiAW0w qoBeLLBm2Y4+mn2p2gA/1xaqEHF1H0wtEzZSBub+8vlcZBhKoNQZavOFTj+Op4czvV/r 8ZFe4dm4YxzXWJWfUE5h2dSpO0sqGp+fouaz/em9DixUu2QBBnGY+Odlrsdn+TeLeRow jKEbAAG4E3th/ymvcuvt2BrzMX1KHxU3WWKYwnFrZu5vv2A5BbwDGJ1jPGCMgKKtf5nt ErXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E3vLvIh2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Let's add support for it. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx55.dtsi | 82 +++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index a1f4a7b0904a..b411c4ae34c3 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -303,6 +303,88 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_rc: pcie@1c00000 { + compatible = "qcom,pcie-sdx55"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "msi8"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep"; + + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x0200 0x0f>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, From patchwork Fri Feb 24 10:59:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61266 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp837862wrd; Fri, 24 Feb 2023 03:03:11 -0800 (PST) X-Google-Smtp-Source: AK7set8Z4DA7oIs+RnG0PQLTI7iaI1nSe8rP7G8W4Lb434+GZ+xs5QsZQFtnJUffImRRZYtzxmLx X-Received: by 2002:aa7:d491:0:b0:4ad:7cfe:f0a with SMTP id b17-20020aa7d491000000b004ad7cfe0f0amr14593188edr.34.1677236591148; Fri, 24 Feb 2023 03:03:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677236591; cv=none; d=google.com; s=arc-20160816; b=W+j1EF+yU1vvAG9MQuyUoRAijL65pf81+N3MIX/zgT/gU3vX9cFww36SJO8O2Kr+is 4e2XRU2qc/YtqmsKMBj9+8rSMb/W8SkUnuD/ZU8YnfNSpP+X1NvOA29fW+1pC8lhCTTO L/85v1WqpLhnUDou56Ksf/+kBfD3QwhFmkiqJlZwAoR3wkDM4zFqOYXTZ7ZozLYaTYIq O7hxCJi/mqEcsMoBAkYVvdL5cuO1mo8RTJGMcc4BxLXF4p2pUQ2tcwnNCiVR3xCjIYOn E0vbNAi08LAzadFjBRVV1fmCG4vna/ZJfvOi+CSSlabS9AvjrWZ2vI8iFn5kKOk5ccFu ng8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xofzeZkvhksqMPAnkuhobq6bJN+LwPdywmpacr5C34Y=; b=i5ohT81m3SIVpDFxWKCJeUe4ufoAFh3za/1PmocdRTvjfnp2c8z1O47+yPjazwqQKo etgevqDWpzC5TqHbyuqWHcqm/233Ynotu7geBVJ1c7kWcFo8f5IXb9ix/OpL9eZIqIFo O/eEkZrxGowI8+PFbI/AuH1xE+r57M0SOlU2/vSOUETAR9lSS+LdOJ7wvS5UsZyPdep+ vbXrTERnI5RJg60BnvFr4J9EbGW+PyAY4RNlrmI2ekt5v8cyvPdzD+TCAH3VXQdCQDnx j61mv8Wdx5bBfBQYd1+aRjuGBPjtzO8XK9hCxTYGa5/QyP848i0yMjRGOPwrygTTVR/M T5xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bgyrhfTA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Suggested-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx55.dtsi | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index b411c4ae34c3..61fdd601fc26 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -393,7 +393,11 @@ pcie_ep: pcie-ep@1c00000 { <0x40001000 0x1000>, <0x40200000 0x100000>, <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", "mmio"; qcom,perst-regs = <&tcsr 0xb258 0xb270>; @@ -405,12 +409,18 @@ pcie_ep: pcie-ep@1c00000 { <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_SLEEP_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; interrupts = , ; - interrupt-names = "global", "doorbell"; + interrupt-names = "global", + "doorbell"; reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_PCIE_BCR>; @@ -434,7 +444,10 @@ pcie_phy: phy@1c07000 { <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen"; resets = <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy"; From patchwork Fri Feb 24 10:59:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61269 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp838149wrd; Fri, 24 Feb 2023 03:03:40 -0800 (PST) X-Google-Smtp-Source: AK7set+vui8FHyyHAWfzB4aW1ly4zvqLN7oFhICFVHSyEU9iM9JyxlfURe/kIGd6EGC0nVS9iLVN X-Received: by 2002:a17:907:33cc:b0:86f:d0c9:4bdd with SMTP id zk12-20020a17090733cc00b0086fd0c94bddmr20285440ejb.27.1677236620351; Fri, 24 Feb 2023 03:03:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677236620; cv=none; d=google.com; s=arc-20160816; b=HNYZaaeibhZZ6VSLlPmnawYXZt7ZIojEntIAQqf6GmIT5okAK6OiasK5Ow+gE9euDV /zslQNvhh3jvugKk+HfRrqyx42ur180vSERNc/wgOxHPoQHI8PbNGosOv/ogAQqTNd+m O0gQ2wJ6tjbTmg+TZWPSeXEhzghCPjwNO9azUYWssv8BO+R0fU0PyBrkNJPCyT/3RtOI OEDtcEzWelvECvXmoC5dvOJOj68Hp+oVvCLOxxwqG74Ow4+oYRCFHhR/7RTFoU2s4yPr AH0py13VB5ZgWp5JYoGK/NrYQy/qetxxtAmeWGVvCZvHEeM9Jo/Mm7pIha/Ey2GDZSsj vDMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iP9zGqgMaCSpCYlPZyiAEXYd/RguuzuuCZizAwTQ5gg=; b=BB2O0MWLJMWBX8O818jeiwXItOH8A49Iu+x4u/24ptbvZOokIlgUI+O0bXfiWBA/ms 8obO43wRjXGhyEB2Ay3JzhI5NkGWG1SikbkfweqF553IRaDvD64HNERAwqmDF2Yan41Z ylO2CtlPKvm1nzTwEOyNhI6I7j2t5kq8QQieTiQNS6418UKEHbw2bfB1zHmxzHzrmacN BaD9ZYhC0dJmAlFBG9ZYiUEphS4Hj8fxC+gc92tt84P17KlxXBF+1FE0Kj/MFxIbT9OZ MWR2C8zIpKJ/sJeLYmlMFTzqHkuWvMoDK94Vvj3YGt4MWgKUU4xBYnt0vdkYqeTyYLjJ sjdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J290LwTp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 7ed8feb99afb..6339af791b0b 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -242,6 +242,23 @@ &ipa { memory-region = <&ipa_fw_mem>; }; +&pcie_phy { + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + + status = "okay"; +}; + +&pcie_rc { + perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &qpic_bam { status = "ok"; }; @@ -265,6 +282,31 @@ &remoteproc_mpss { memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_default: pcie-default-state { + clkreq-pins { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; From patchwork Fri Feb 24 10:59:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61270 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp838196wrd; Fri, 24 Feb 2023 03:03:45 -0800 (PST) X-Google-Smtp-Source: AK7set/lk+QoYUIWuCARQTNR/dn9vaPSJz/V7TrDcVkgnRaPt4psN/OFCI+vkY70Bt1Q2queQC5A X-Received: by 2002:a17:906:3958:b0:8b1:7fa:51da with SMTP id g24-20020a170906395800b008b107fa51damr19739784eje.52.1677236625035; Fri, 24 Feb 2023 03:03:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677236625; cv=none; d=google.com; s=arc-20160816; b=MD7ctBmlJA7ouotBuk4qbWdiVhePzaLwMoeJ9UtxBW8cuaA+tFuZ3AgRUWfo/66vzY /xF/XtcemxTtGszOYSXVqHtS5dGmL+3Az7mHiKMjpVbuSvPpY5Po3fwx7Lt9igUckSJJ t4HlUSqfhJKr/iR3pF7eO5maw9u15Ax2v8rBQpVuJKnmZvJRnrtJRy9fg+1kyb+0VZKq /0XeGV/+aDpfOvLTe4LCT/8lKE3wE9dLVW8aHuA1qUS7lvsvb1DiG7hcMtnxYyJPQkGA ONS3eXh3clfAv3MtqC/whtkvGrZhZHAB9rY4cTP7VRr0w83LCk3yjKTnjE5c2CaZFrmW +zLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Iy/081Gnr6V+cD2T3z4UyrGlDr2ZO96fWTmGEselzPk=; b=j7Ucj5nE9ZvTlupqY14oIrhw8zkUst7kJpCWCXDG05w331AeZr8ZKCo4gPku/8YA1K rS1q6ryyR7MxkEUFv+aKeSAKILie8rI6gnlJT7CX9gIPZDyIkmMCrdWEjDO2NfkpjtqZ VAtslJXVpOUknW5uYTPqDNXX9j1LtfoBdghNlKOhmQ+2Clw6Cf7DPJKdaM+c2l/qylPx f/HxBDjbrjBTvqO1Aq8YTOVSXMZ2S9RCwDmxjmrUvXlLHEQC/KWCYAiUCx2/IjfW37A2 3WnEGcLtE4DJtiP37mywqztoBAy0pFYlmkWHe1Gwc5upFb3sX2zIN8MzRE7KlZnMq0u1 4Fyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=omzwojmB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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&ipa { - status = "okay"; - memory-region = <&ipa_fw_mem>; + + status = "okay"; }; &pcie_phy { @@ -278,8 +278,9 @@ nand@0 { }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + + status = "okay"; }; &tlmm { @@ -308,16 +309,18 @@ wake-pins { }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; vdda33-supply = <&vreg_l10e_3p1>; vdda18-supply = <&vreg_l5e_bb_1p7>; + + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4e_bb_0p875>; vdda-pll-supply = <&vreg_l1e_bb_1p2>; + + status = "okay"; }; &usb { From patchwork Fri Feb 24 10:59:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61272 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp838887wrd; Fri, 24 Feb 2023 03:05:07 -0800 (PST) X-Google-Smtp-Source: AK7set8lcLtkvT45QcnIx/Q/g25D3U+chT45VRWITeLIra5UU8xVqXmIF4R5osLGqJqEKRNPFRir X-Received: by 2002:a17:906:7f8c:b0:8b0:fc14:bbcb with SMTP id f12-20020a1709067f8c00b008b0fc14bbcbmr18417265ejr.42.1677236706858; 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Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 42 ++++++++++++++++-------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 1b136a87053f..f526f73f76ef 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1122,10 +1122,25 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { }; static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), @@ -1133,8 +1148,6 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), @@ -1146,21 +1159,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), }; static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { @@ -1212,6 +1215,9 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), }; @@ -2003,6 +2009,14 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), }, + + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { + .serdes = sdx55_qmp_pcie_ep_serdes_tbl, + .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), + .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), + }, + .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, From patchwork Fri Feb 24 10:59:05 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e5-20020a056402088500b004ada70cf9e2si13109095edy.58.2023.02.24.03.04.44; Fri, 24 Feb 2023 03:05:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G17M3oBH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230330AbjBXLBt (ORCPT + 99 others); Fri, 24 Feb 2023 06:01:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229801AbjBXLAd (ORCPT ); Fri, 24 Feb 2023 06:00:33 -0500 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55E29671C6 for ; Fri, 24 Feb 2023 03:00:12 -0800 (PST) Received: by mail-pl1-x630.google.com with SMTP id ko13so16991567plb.13 for ; Fri, 24 Feb 2023 03:00:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RqG9xtTBiKFFqs7nudeShHVEmZgSa7/qeDhwUVoJ0gI=; b=G17M3oBHmV1rKnXNh1qHs8TV9ZpAIJko2IX49Vd+g7LzLTJ7J29aWSKgIGFLJNfkXa z2J7OxDTIAOohyEkMB5yoq1pCXjGEkvok/8Nyov5BaZ8YPSdoEecZwNJ72edVHIXcCD8 NwtowiHV6RL/DILAYI/vRlDaWPAn5mQvxosGSHcaaxmNpiwjFrfcIoJRrtPRColtdjZo yJRziDEWYWd1E99c9gqQoYDEV2s8EgL1dUYgfyOdQd6OiXx843L3SJBVCCHKECPHG+5r I/xBedgx7KJUfBxt7S751k773L1TzebuwGza831nxZK80Tx6tgOr0C+wqYhhK82mZJ62 jobg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RqG9xtTBiKFFqs7nudeShHVEmZgSa7/qeDhwUVoJ0gI=; b=VZx8yko6j/CNDqMVsyVtKqQTJjf6FcBx9MexFrKGRvWp21FyL1PIlxV4Muns9ddTvI YT64HF5wgUxV1Iuwan1PktXMljSrvPjQtS/9nlspcWoDLFj1PUSzPY9vM46ieSYuxVrS pKUYAAwwJGJKDjuIAneCMlEoevW5+fO6zX5OZ5czJYXMU2uf4B4g3B/BN8u4ifHfnny2 ykOXTwhVSNlwnPHcJd2chptEMN/6h1AK0tDPYYKnMGeq841AlVqybYXD2qeTvLUkwMNQ eytTmEBHWVz5rSePbE8eHgT9fZlqB8hmrjejzNI7mNDen1F2QsVU53drf5Y+aY5JT1iq gQgg== X-Gm-Message-State: AO0yUKWF+2dCSBdM4Cn34TzyqfVFeK5ULk8IYJBf1eFnLXGFyAfguDvK UwDjX4XtMtZvSSgkcDVCPu+i X-Received: by 2002:a17:90b:38ce:b0:236:704d:ab8c with SMTP id nn14-20020a17090b38ce00b00236704dab8cmr16684270pjb.26.1677236411808; Fri, 24 Feb 2023 03:00:11 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.03.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 03:00:11 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 12/13] phy: qcom-qmp-pcie: Add RC init sequence for SDX55 Date: Fri, 24 Feb 2023 16:29:05 +0530 Message-Id: <20230224105906.16540-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758710156976466962?= X-GMAIL-MSGID: =?utf-8?q?1758710156976466962?= Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 49 ++++++++++++++++++- .../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 2 + 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index f526f73f76ef..9d92facd47a6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1138,6 +1138,41 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), }; +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), +}; + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), @@ -1217,6 +1252,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), }; +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +}; + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), @@ -2010,6 +2050,13 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), }, + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { + .serdes = sdx55_qmp_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), + .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), + }, + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { .serdes = sdx55_qmp_pcie_ep_serdes_tbl, .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), @@ -2025,7 +2072,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = sm8250_pcie_regs_layout, - .pwrdn_ctrl = SW_PWRDN, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, }; diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h index af273602998e..ac872a9eff9a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h @@ -6,6 +6,8 @@ #ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ #define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ +#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 From patchwork Fri Feb 24 10:59:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 61273 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp839906wrd; Fri, 24 Feb 2023 03:07:05 -0800 (PST) X-Google-Smtp-Source: AK7set+kor0uUkWs7AcoaX0yfV37zgCIR2gEB6JplHVWm0VGz2fhdPn/EBYyoYkUgMpHqo7YdgLm X-Received: by 2002:a17:906:4784:b0:8f1:da18:c6ca with SMTP id cw4-20020a170906478400b008f1da18c6camr4945168ejc.3.1677236825482; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n15-20020a056402514f00b004acb81aae7dsi4595190edd.186.2023.02.24.03.06.24; Fri, 24 Feb 2023 03:07:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fAJqvN5f; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230338AbjBXLCE (ORCPT + 99 others); Fri, 24 Feb 2023 06:02:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229874AbjBXLAt (ORCPT ); Fri, 24 Feb 2023 06:00:49 -0500 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFC2B6357A for ; Fri, 24 Feb 2023 03:00:16 -0800 (PST) Received: by mail-pl1-x630.google.com with SMTP id ko13so16991795plb.13 for ; Fri, 24 Feb 2023 03:00:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GDe2OfCLNRaJ6CRURKr3KlmzCsataxU7y19XTJRsk+A=; b=fAJqvN5f5O1suKMbMKyZTKUOuQWDy9CpZJalOaBD5HtdbClkBc2Y3mQktVEXsKIkyM jqwulwTPo0TCvEOim7vshccXaA0Rf0Y9DXxoEyVsK6j4qZBAOBZHZiAZh0/FPdl8b/6t 99/G0hP6iYZ4siN6USBnUOzHhXy1eq6v4rBhHz+L1jWHVYaknjNut3fHZGmnF4uuf8bR wpflaqZ3v5/cyV78xkdj4tw+GViopd/zJBAxU8ZdPbKO62vSoEb1Mc10BxaZZnmVKbUe 7pNqc3ZJQdBJVjmXt29Ew9KoAUfYslHbLyuSOn82oi52m3xc0zy0oxh6RKvsx+uXM0Us l8lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GDe2OfCLNRaJ6CRURKr3KlmzCsataxU7y19XTJRsk+A=; b=PLLaoWL+7FvzSoV1CnYJx+haolMGyyBQzjdIfwJz2+4mH0S9BLW6g9n26M/A6RtFzA Fu48fcMti2w0etEOe+pB5RKth8I1oCxYxR9rhOkvfnwaZDe6+wxLD/1wG7BoV/qBmmEH S15oLb6wVXHyMORI5xx0TWCkLUhEypByK9hG+hM+5fT1l4nEDQPIMNd0MgMt7K2j12cx zSvHox8wvK8tFjrMDRivnfcUbMEZp/SzaH5OyAHm/DyjmprWLnIb5xNuIe2+P0eErnyx HU0pmMz31L8y3uxOdcOQk5pO1HRjCCT6NrGYLRAqHDrR5hfLZDj4ShddKS4F1frUrhil ZbaQ== X-Gm-Message-State: AO0yUKVbDq3+3iFrJEl7leSyN7wok9N09NPrXJlymssJLEJ61KL+Zn67 CRX5qE6VsHp9s0TrdffLtnVJ X-Received: by 2002:a17:90b:4a4d:b0:231:284:ea4d with SMTP id lb13-20020a17090b4a4d00b002310284ea4dmr17736121pjb.22.1677236416420; Fri, 24 Feb 2023 03:00:16 -0800 (PST) Received: from localhost.localdomain ([117.217.187.3]) by smtp.gmail.com with ESMTPSA id gd5-20020a17090b0fc500b00233cde36909sm1263853pjb.21.2023.02.24.03.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 03:00:16 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 13/13] PCI: qcom: Add support for SDX55 SoC Date: Fri, 24 Feb 2023 16:29:06 +0530 Message-Id: <20230224105906.16540-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758710281230750068?= X-GMAIL-MSGID: =?utf-8?q?1758710281230750068?= Add support for SDX55 SoC reusing the 1.9.0 config. The PCIe controller is of version 1.10.0 but it is compatible with the 1.9.0 config. This SoC also requires "sleep" clock which is added as an optional clock in the driver, since it is not required on other SoCs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 77e5dc7b88ad..659df73114dd 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[13]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "sleep"; num_opt_clks = idx - num_clks; res->num_clks = idx; @@ -1824,6 +1825,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, + { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },