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[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21480/ Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a2xx.xml.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h index afa6023346c4..b85fdc082bc1 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h @@ -1060,6 +1060,12 @@ enum a2xx_mh_perfcnt_select { AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, }; +enum perf_mode_cnt { + PERF_STATE_RESET = 0, + PERF_STATE_ENABLE = 1, + PERF_STATE_FREEZE = 2, +}; + enum adreno_mmu_clnt_beh { BEH_NEVR = 0, BEH_TRAN_RNG = 1, From patchwork Thu Feb 23 10:51:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60898 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp247195wrd; Thu, 23 Feb 2023 02:56:12 -0800 (PST) X-Google-Smtp-Source: AK7set9HL9LpyyHgcyuyQgYyjwa7kPkfUu/drTnjmwHY2UVWeFBwCNatJJhsU4rqy2gOzK+NHYxA X-Received: by 2002:a05:6402:1e91:b0:4af:593c:c09b with SMTP id f17-20020a0564021e9100b004af593cc09bmr5704604edf.0.1677149772668; Thu, 23 Feb 2023 02:56:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677149772; cv=none; d=google.com; s=arc-20160816; b=HYbe93NW1QW0a0U1vupn2YxbbbIuhUpPIZxN8rHnQkA+TYDg39IaPmjz8vr3rkMLvW 4VGBNhuIJTjR7mzUzWVh5j3p5+7i79I0IL6UFw2RHYW9ZFkmtCq7eci10SaKPH+68DXl JnzYDkjZFGEhV5OL2TJm1o183zgnQL0JuMvp7+D/0YNVhxbdc0TJ6sAia86uC2ycUrWS uuayIawfCc+iHUS8GPjLwLA9KQGBQwwWNGuXoI4u9oXgJgxc+EqsM/3po8Yoa4iVBNlt ndDV0mtZ1m3m/Tn5ljyjMaEG0601GMWwgTXKOFQMDCwCrfV5bVW2f9FTFAykf9oGkNwg 9HJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=Za3E13sEZpZGy0TRJfvtiuOwvhVoLyHtf80EvRj/pZk=; b=x9du+h4V0wR9nuEDq+K4dGxiv8xAkx4IjkqqF25LRAARbS//o0Q7UaFBYtAGSCmzM9 ES4JfC9ZUdf/wWObJTQQidIb3BX14QQyh9iNgUf1C6XT03ZnCwIPWeS6gwl7R9K1fKHv nltas/Y13S+1+o+NnxC4HMNK9ExXl5/HIKjjwZpXTdULpn9hH8Zr1c7ySBJncbJvBdQg PHSc3m29Jy0w6YQzBm4K5spMr9Z0o3r+2/T8mwnXtXn/ZkWnCZ0GSzUDvnNFTUDYoHqn 6MxT8p5jJv4sWupkvjFBihMg7PK7ukpjlhsbG7TYQTqY59yKuumic4LxsmrUYoRHohQj 3e/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MDFq7rd0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id m25-20020ac24ad9000000b004cf07a0051csm262304lfp.228.2023.02.23.02.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 02:52:06 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 11:51:58 +0100 Subject: [PATCH v3 2/7] drm/msm/a2xx: Add REG_A2XX_RBBM_PM_OVERRIDE2 to XML MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v3-2-5f22163cd1df@linaro.org> References: <20230223-topic-opp-v3-0-5f22163cd1df@linaro.org> In-Reply-To: <20230223-topic-opp-v3-0-5f22163cd1df@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677149522; l=1718; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=rz6HoVcDmCXeKasABEEZkTNc5/V8jfFkA4B1KcOgBnk=; b=SV+lLJPnQxMiG/KFu5RTsHoCbIyFDh3U+cxdnLtWr+2iKgpzxvA+vL+isiIzxDQu0WWLaAFkiOco 5fsAxgM/ChvKgPuWKpvD2Uc6+EI07YVG76reRZTaxRAM7YZWZsqV X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758618999731697387?= X-GMAIL-MSGID: =?utf-8?q?1758618999731697387?= This is a partial merge of [1], subject to be dropped if a header update is executed. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21484 Suggested-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a2xx.xml.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h index b85fdc082bc1..fbac25f66c67 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h @@ -1313,6 +1313,18 @@ static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d +#define A2XX_RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE 0x00000001 +#define A2XX_RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE 0x00000002 +#define A2XX_RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE 0x00000004 +#define A2XX_RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE 0x00000008 +#define A2XX_RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010 +#define A2XX_RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE 0x00000020 +#define A2XX_RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040 +#define A2XX_RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE 0x00000080 +#define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE 0x00000100 +#define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE 0x00000200 +#define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE 0x00000400 +#define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE 0x00000800 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 From patchwork Thu Feb 23 10:51:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60899 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp247271wrd; Thu, 23 Feb 2023 02:56:30 -0800 (PST) X-Google-Smtp-Source: AK7set9Vhb/M/6nTaECjCNlK4IWcFR5bOH4uohQ77dfKe4/14dAVwUErMYyAYNFraEaCmyRCg9ph X-Received: by 2002:a17:906:74dd:b0:887:dbe1:25ac with SMTP id z29-20020a17090674dd00b00887dbe125acmr20113265ejl.0.1677149789929; Thu, 23 Feb 2023 02:56:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677149789; cv=none; d=google.com; s=arc-20160816; b=yzpuDxWOjXw+Rp/aoE4rB0/FbO83/g3YcKrUK4P5y9bjiU6IHWyAnoB7R+u4T5NEZZ 9bR5tO7jRkC5JGBkKGKroKKkzG8RNRDojNI3MZonuTbtqWqd80INsZqAHnY/3jORCne/ d6s+CSd/zdK+mNwfzdXzWMZ0Rm3D2B31VraMZfgNHFkpVi6z1gXueBzkGPCS5LnHwmjb 3Ew6AxFsr4DLY92GbYXpT6C0qVgKSVi6iiVafv3a9PEBZIL+UDcod8U1mlEUq37Cn/C4 u7aXEz2AXXDNMwQeuCM63AVVTIsNB3punvyP50mQrtSmvnEkRp06G5mIPJvOa3R/tPTe J1og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=kOnarmskAJLopy40U3oKLXvwONPiZjzBhb9uGjfbEpM=; b=dU03dwtzw7COC9Fk9DB4cKHQi+0B39iHQwNZtm0TPRNoiavOlI1lboCIN4zPs/lnid 1xWZnhBDZvCCpFaszKkSKYu8tuHekIuaMUysHnsr9ZDhmZaNs2WkmlwvA7Qu+PkRx8BI KgDv1/6KXVXQE8Oujh0/oGbZG7uwSc9VpnqCcUWyHcNhWCvjXjMhr+ZOBV86PrGDjvAa 9VnQnrARyOVEDb7NPLs2/Yjf+fq4/h3YhkUcXO+WYONFJj6y8zAHOUuq0uLZSHWUKdTM AqRhkMSLRmR0AXGWmcvwPCUsLw4EY0c+bxQwA6wr1cCNjXL8K/ducE8RslTDnuhVN3gB lY2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v6mJXgjM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id m25-20020ac24ad9000000b004cf07a0051csm262304lfp.228.2023.02.23.02.52.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 02:52:07 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 11:51:59 +0100 Subject: [PATCH v3 3/7] drm/msm/adreno: Use OPP for every GPU generation MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v3-3-5f22163cd1df@linaro.org> References: <20230223-topic-opp-v3-0-5f22163cd1df@linaro.org> In-Reply-To: <20230223-topic-opp-v3-0-5f22163cd1df@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677149522; l=6284; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=glYRGSAYYXQFh91qm5j1elUuZYdypRgrsNPyka/F8vE=; b=aNk/6sMX10joDOfNNA+zMQRVgVNP1GQlVvN6+WTjJArXs6Mfezf/axeXVsw/hubjtzdfeQUk1CiW 5U+fuMvaA3Ke1TyL+vpAeDKopiEgfvO0Rk1oXpIN8/6EVjfjMp2L X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758619018058672437?= X-GMAIL-MSGID: =?utf-8?q?1758619018058672437?= Some older GPUs (namely a2xx with no opp tables at all and a320 with downstream-remnants gpu pwrlevels) used not to have OPP tables. They both however had just one frequency defined, making it extremely easy to construct such an OPP table from within the driver if need be. Do so and switch all clk_set_rate calls on core_clk to their OPP counterparts. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 99 +++++++++++++++------------------ drivers/gpu/drm/msm/msm_gpu.c | 4 +- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- 3 files changed, 47 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index ce6b76c45b6f..d12f2f314022 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -922,73 +922,46 @@ void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) ring->id); } -/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ -static int adreno_get_legacy_pwrlevels(struct device *dev) -{ - struct device_node *child, *node; - int ret; - - node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); - if (!node) { - DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n"); - return -ENXIO; - } - - for_each_child_of_node(node, child) { - unsigned int val; - - ret = of_property_read_u32(child, "qcom,gpu-freq", &val); - if (ret) - continue; - - /* - * Skip the intentionally bogus clock value found at the bottom - * of most legacy frequency tables - */ - if (val != 27000000) - dev_pm_opp_add(dev, val, 0); - } - - of_node_put(node); - - return 0; -} - -static void adreno_get_pwrlevels(struct device *dev, +static int adreno_get_pwrlevels(struct device *dev, struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); unsigned long freq = ULONG_MAX; struct dev_pm_opp *opp; int ret; gpu->fast_rate = 0; - /* You down with OPP? */ - if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) - ret = adreno_get_legacy_pwrlevels(dev); - else { - ret = devm_pm_opp_of_add_table(dev); - if (ret) - DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); - } - - if (!ret) { - /* Find the fastest defined rate */ - opp = dev_pm_opp_find_freq_floor(dev, &freq); - if (!IS_ERR(opp)) { - gpu->fast_rate = freq; - dev_pm_opp_put(opp); + /* devm_pm_opp_of_add_table may error out but will still create an OPP table */ + ret = devm_pm_opp_of_add_table(dev); + if (ret == -ENODEV) { + /* Special cases for ancient hw with ancient DT bindings */ + if (adreno_is_a2xx(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 200 MHz.\n"); + dev_pm_opp_add(dev, 200000000, 0); + } else if (adreno_is_a320(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 450 MHz.\n"); + dev_pm_opp_add(dev, 450000000, 0); + } else { + DRM_DEV_ERROR(dev, "Unable to find the OPP table\n"); + return -ENODEV; } + } else if (ret) { + DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); + return ret; } - if (!gpu->fast_rate) { - dev_warn(dev, - "Could not find a clock rate. Using a reasonable default\n"); - /* Pick a suitably safe clock speed for any target */ - gpu->fast_rate = 200000000; - } + /* Find the fastest defined rate */ + opp = dev_pm_opp_find_freq_floor(dev, &freq); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + gpu->fast_rate = freq; + dev_pm_opp_put(opp); DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); + + return 0; } int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, @@ -1046,6 +1019,20 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_rev *rev = &config->rev; const char *gpu_name; u32 speedbin; + int ret; + + /* + * This can only be done before devm_pm_opp_of_add_table(), or + * dev_pm_opp_set_config() will WARN_ON() + */ + if (IS_ERR(devm_clk_get(dev, "core"))) { + /* + * If "core" is absent, go for the legacy clock name. + * If we got this far in probing, it's a given one of them exists. + */ + devm_pm_opp_set_clkname(dev, "core_clk"); + } else + devm_pm_opp_set_clkname(dev, "core"); adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); @@ -1070,7 +1057,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.nr_rings = nr_rings; - adreno_get_pwrlevels(dev, gpu); + ret = adreno_get_pwrlevels(dev, gpu); + if (ret) + return ret; pm_runtime_set_autosuspend_delay(dev, adreno_gpu->info->inactive_period); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 380249500325..cdcb00df3f25 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -59,7 +59,7 @@ static int disable_pwrrail(struct msm_gpu *gpu) static int enable_clk(struct msm_gpu *gpu) { if (gpu->core_clk && gpu->fast_rate) - clk_set_rate(gpu->core_clk, gpu->fast_rate); + dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); /* Set the RBBM timer rate to 19.2Mhz */ if (gpu->rbbmtimer_clk) @@ -78,7 +78,7 @@ static int disable_clk(struct msm_gpu *gpu) * will be rounded down to zero anyway so it all works out. */ if (gpu->core_clk) - clk_set_rate(gpu->core_clk, 27000000); + dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); if (gpu->rbbmtimer_clk) clk_set_rate(gpu->rbbmtimer_clk, 0); diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index e27dbf12b5e8..ea70c1c32d94 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -48,7 +48,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); mutex_unlock(&df->lock); } else { - clk_set_rate(gpu->core_clk, *freq); + dev_pm_opp_set_rate(dev, *freq); } dev_pm_opp_put(opp); From patchwork Thu Feb 23 10:52:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60903 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp247676wrd; Thu, 23 Feb 2023 02:57:52 -0800 (PST) X-Google-Smtp-Source: AK7set/6r77IGL5VmUAZgM9tjswCBzhgWeUL+SCzfa8i/ndGnyO/47gErsXYOzcnuQ8vsTEJNzQx X-Received: by 2002:a17:906:739d:b0:8aa:f573:4ff8 with SMTP id f29-20020a170906739d00b008aaf5734ff8mr16626541ejl.4.1677149872153; Thu, 23 Feb 2023 02:57:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677149872; cv=none; d=google.com; s=arc-20160816; b=K0YocP9rn3qNIZ4Fea2UiTJYctlq5rJQ10skH+CjkMPb5Cm1qXo5JJ7CqWMP4/8Z/O mnUVL0wuWONOKx0VrNjO08HCroTIOrSdwOIJ27ShVin3x/RLouuufh3+23DZ8YpKlr9c iU0tGfoyYY3G3yuooBps6B7bdN8h9A+OjAdtQTT2qaCEgbDhCiTRFPu3af3TFA323OOv hSSP9VZa4MbFsoQx5MQs5NLAUaE7FgbypkesPWJBZ3lESmBhcQjs7wMvEHQOkOBjl8sv wTbPzgH9ATcxL4fn0E8BJa6jCnZ13HfgL/fh6SEBSksbXtykd5Wh5VR+ZcN8FDSBRyKx 3rmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=c856FNZ6Lhd5u8jT462zPqnplUQDu/X42aKd4/VDH9g=; b=uGJFEtjI3QD/SILfuWQVk3sDu1rttH0dTEuWFw3rlS3K2GrqYlWQFf+KPrHJ5jsHxk lHXBLlD851GMNBbVgvPPyK8S5fCBKdIqCMqIXOy8C+qoGDsa57iUSH14p17dOJzfWZ8M eZ4i6auhZVzwPdybKU6FzgCT/scH0O4i6c0sMEsbVC/LRN7nAIyleiqs/fjyrdGH3Kfm gExoJ5B+qFUTztXOy39zE/HkVc1GNSqv5ohaUocWG4r60pZHg8/ObdvUXDFwMDMt/zlJ 2+hjIUfDuhf3wR5yLNtm3WBBLMARF5yFUButuWVkplVIH/KtoeGFHn/uSOrfguKdLrSe 2h+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i+SHoYDu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id m25-20020ac24ad9000000b004cf07a0051csm262304lfp.228.2023.02.23.02.52.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 02:52:08 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 11:52:00 +0100 Subject: [PATCH v3 4/7] drm/msm/a2xx: Implement .gpu_busy MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v3-4-5f22163cd1df@linaro.org> References: <20230223-topic-opp-v3-0-5f22163cd1df@linaro.org> In-Reply-To: <20230223-topic-opp-v3-0-5f22163cd1df@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677149522; l=2182; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=M4GtniFH7Z74oP+C1wfVcdO+1YLmUE+S93nPkBb/ZUE=; b=A2D3TmwvTtxWv0uaGt4JkpWCn10VLe5vtr+8DwgiZJRVaOxktLKqoQFk0HZPITd+ExjXUz1QU95S 18RI7cwQD1ckEytf8zZPcel2UNNBKTsg0CC4mdBmGnGNEy0o5Nak X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758619104146646663?= X-GMAIL-MSGID: =?utf-8?q?1758619104146646663?= Implement gpu_busy based on the downstream msm-3.4 code [1]. This allows us to use devfreq on this old old old hardware! [1] https://github.com/LineageOS/android_kernel_sony_apq8064/blob/lineage-16.0/drivers/gpu/msm/adreno_a2xx.c#L1975 Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c index c67089a7ebc1..104bdf28cdaf 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -481,6 +481,31 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) return aspace; } +/* While the precise size of this field is unknown, it holds at least these three values.. */ +static u64 a2xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + /* Freeze the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_FREEZE); + + busy_cycles = gpu_read64(gpu, REG_A2XX_RBBM_PERFCOUNTER1_LO); + + /* Reset the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_RESET); + + /* Re-enable the performance monitors */ + gpu_rmw(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, + A2XX_RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE, + A2XX_RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE); + gpu_write(gpu, REG_A2XX_RBBM_PERFCOUNTER1_SELECT, 1); + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_ENABLE); + + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -502,6 +527,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a2xx_gpu_busy, .gpu_state_get = a2xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = a2xx_create_address_space, From patchwork Thu Feb 23 10:52:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60900 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp247434wrd; Thu, 23 Feb 2023 02:57:05 -0800 (PST) X-Google-Smtp-Source: AK7set/8nse3eLOn8279w+JukhrRP2RYxpWAlLkWRx1TkT++X8pMsTMvqLedxM2/t5dguv4ZMCul X-Received: by 2002:a17:906:10da:b0:8b1:94cc:10b1 with SMTP id v26-20020a17090610da00b008b194cc10b1mr18822135ejv.7.1677149825490; Thu, 23 Feb 2023 02:57:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677149825; cv=none; d=google.com; s=arc-20160816; b=rZffxjuHITzQZ6mN/qsc1x+OWF1n6lrrGMY5ygcX0gtTycIbQj2rOF2f2xFZzc31+N ZGlHr+PxAcGGjCN5z+3nn2O5jkqrr65/gmUaITyHFyOu0wIieDzIczBqR3Miy55QhtT3 I+HzGN/cISDtKBxN0QS7P4gSoLSI0YkZDtIVAIewKDey79B65Mwdt1MhM6eliRR8eS6S dviwYctLL1w21TBv4qTO9vn/I+ICmYNYlPunuuz3oc8TmkQk9iITCEw/AW3D/JpBmyzh WkEbZxIxb+sEBNzcReGyNWBggzEzSZzdRCTEVq81oiE86PSmPhzaaUR975IxhT6WHrdf YHeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=4RozdFg8UcjNGaMEUfY94uV2Q1ptXwQxOYUwNdKHWzQ=; b=a3EpRR/fbQCVAGZDxjJvPnDSXtRhUpQh52pqNz6Tfh8MKzyTnNMI45kEL5YAxH0c1Z FUwBTb4H7W6uCzIp4tlAymdgBpbGBj5dH+iErEPtrU0BWogebQcMXPHjDQqKykIg4x6M e5Yu41xxweEBDHIOaCPRbzuLirKmo0MRYSinzGKPXKHW0jis5+un3vNphw0BJ84SecQc 87sLfkotHqzYzQkBOCWYn8GksRnfi6F2NJuRXACPG0E/WTpo8tuWrX1mSKdpNppcoBjf QXh4LXW3IiU0odf2SkiP4yKU+ewI3/mvgrt6bT14lZ+zEtGkgG3JZ6xTa55yEvH7mDWG hM3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GGxvm6bl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Tested-by: Dmitry Baryshkov #ifc6410 Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 948785ed07bb..c86b377f6f0d 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -477,6 +477,16 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu) return state; } +static u64 a3xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + busy_cycles = gpu_read64(gpu, REG_A3XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -498,6 +508,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a3xx_gpu_busy, .gpu_state_get = a3xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = adreno_create_address_space, From patchwork Thu Feb 23 10:52:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60902 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp247675wrd; Thu, 23 Feb 2023 02:57:52 -0800 (PST) X-Google-Smtp-Source: AK7set/mR7vG28JHm4u9b/xNvwzj05U1f/qdHG1kvaLT4I6K9iLjVcDBkaGIouRCZejhlSOPQHoL X-Received: by 2002:a17:906:51ca:b0:8eb:fb1a:6970 with SMTP id v10-20020a17090651ca00b008ebfb1a6970mr3035734ejk.1.1677149872096; Thu, 23 Feb 2023 02:57:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677149872; cv=none; d=google.com; s=arc-20160816; b=v4DV2Ox+LtscWUcnRdo+orMsphD0SRqR6PDQypGBVldXjf7798786ScOXG+wbgIc8d 74NRYAfMw7ZaPVSlzs7J+2E0TUQ/rwiWHbDP3RKYZKJvApgokrF57jsdtCTc4aOP7eio NJHuwbDVD0xMl7wi8WtDPMTpscMbJzzMT+U691jJOGHKO9FQdTgO3b8zdbNGlTrKM/uN pCRf/NsZRaPXrhDxTeDIFrBqJ57ieajWjx3VdWWX5qJRiw+1dSl7zTmlu6QbeM+E4xTq 81fILKmCE/wBBTB9oT8HoACBR3+n2vLW0Mk8g4DKx79fU2reOqDkd0JTxRjy1H56PCqJ qelw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=GGhJ8k8BvYcG4UvdUcw3fi971zbE82bjXqWQD3F+nXY=; b=qVFHtgLrl5MmQ+aeBvaCpMzowYj3yVJvWcUNuEgZ1U/UVObHuSe/pH5vL531vlhw4j tKrjdNVAHs6wlOugjh3eAA9UE5dE7DwkeoEN01QCtokRN1EPAyIk1vE/vv7+LRWGkG0J oXfy1q5XeQnSr8wacENeli80eoTMLdbaUjUZevBs5ZmW8bjYt4kqELHx1QQZMKYFDmUz yIHM45Ksn9sUmFFdK7tkM5cPiySwDPTPKaP6EFHhp+S9s1Jg8wnpo1kgf2r8pBwCKVxk b/wiHE3ym6EhZAWcCgO3ESood99O2Ms+2C0VzNTBVBpvRDOBoKOxQhVj08gDLr0wHQP8 JJdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nwnpdMI6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 3e09d3a7a0ac..715436cb3996 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -611,6 +611,16 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) return 0; } +static u64 a4xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + busy_cycles = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a4xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR); @@ -632,6 +642,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a4xx_gpu_busy, .gpu_state_get = a4xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = adreno_create_address_space, From patchwork Thu Feb 23 10:52:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60904 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp247824wrd; Thu, 23 Feb 2023 02:58:17 -0800 (PST) X-Google-Smtp-Source: AK7set8I6EQr2eNxb+3mfvdOjj7j/nSELkwyhJaEA0YYFkpjiEEwDlGdgeB+ddHolFBzE61HGGgI X-Received: by 2002:a17:906:109c:b0:8b7:1cb4:a5ba with SMTP id u28-20020a170906109c00b008b71cb4a5bamr17935580eju.5.1677149897196; Thu, 23 Feb 2023 02:58:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677149897; cv=none; d=google.com; s=arc-20160816; b=Icp0mT3pEBuAr82EOTz1VCBxkWFFyb79mJ6eP+Yk5jB79bFM93k2b0lGgKhRyO6X04 QukFqt40nH8oiMacRmiVj31afoy6HM3Pcybi1GEfyhG3eFhXg+cPavDRJmTAXfLDGBLl zraghj+wQMSLlhuaJTADf6sLFC5an9/lVLrf984fsDeC/sz0ZOrA0fhE7Kk+ZOz9OPNG U+2qXze8hAmo/P87/KOCN5TgBw5tPUoMmNfXqzkye14J7IZrg9u+9EWvvzUK9Ftk2Pfo xCNDFf8c+425zCZCPf83aH8sOpGZotGw/+SNNCdXYcXA72LHQsaMqT4tXqoON0AdJrHp 8Pxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=312OV1ExLaf1docfwSJg/DyYHuD2OoIvYCwHKB24HQI=; b=ZL4QUVay42hNnDk3WiEJATnP5G0GI0vWOCp2uNopua/Xg52lwreZGCORDDanb1UJ82 7JBkncPgd+N/K1EtyDXrYSJohs6FjTC/IiLtvLpz8KJtVnPMQ4SOhCGwL5gKjtgZc1np 3t32z9lgA5KRdo2ZeyvkmEx9Hoitv2Dr33sWZngkiKde2SMSR+MWDOvVQddS08ljOm1n 9JWuKumfg7W/Valw13DCFAvFmSO/nWpUp0QU6WpFJ2E5QBFakTzg5rKkGxFD15Bq6LGW f4N2raKQEQsB2PDXaKj3oQY/pbpLmSkZmdlJfQn+ino82Cn0xzkDki0AiDVuZLFMuQjW Zliw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Ce/cN8SJ"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id m25-20020ac24ad9000000b004cf07a0051csm262304lfp.228.2023.02.23.02.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 02:52:12 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 11:52:03 +0100 Subject: [PATCH v3 7/7] drm/msm/adreno: Enable optional icc voting from OPP tables MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v3-7-5f22163cd1df@linaro.org> References: <20230223-topic-opp-v3-0-5f22163cd1df@linaro.org> In-Reply-To: <20230223-topic-opp-v3-0-5f22163cd1df@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677149522; l=828; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Yh6pwT6P3XDwmr1GaQu8MRHxTbI8EpTO/tdF6ItczWk=; b=2rrRDrTtljtkMy2NiIvypriRAjz8Zl6PZhh4lLLHUrTd/4LPzZWyfiOavFuEJQnJLGhxCc/L8cSg DQgfDp28B0bz+/nmo/25V3K4pnLZVeMgAtqBwOy48QqoAzn8bDYx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758619130568126884?= X-GMAIL-MSGID: =?utf-8?q?1758619130568126884?= Add the dev_pm_opp_of_find_icc_paths() call to let the OPP framework handle bus voting as part of power level setting. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 36f062c7582f..5142a4c72cfc 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -548,6 +548,10 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(gpu); } + ret = dev_pm_opp_of_find_icc_paths(dev, NULL); + if (ret) + return ret; + return 0; }