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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:40 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:37 +0100 Subject: [PATCH v2 1/6] drm/msm/a2xx: Include perf counter reg values in XML MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v2-1-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=830; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mzjSUO+qHIiKaLiyXFVom/GoyNVpw37b+tvLzQHI5RY=; b=sOt90zAVghwEBEdFaBDhwOmr+WDEq6xWWtPbhadU8HLedLihLtGPgw3G+utNjj5nKzLKe9UXi7Sp /8dBYiuOABV7JJpxXdNZpynZqYX62ZFL3PLs9g7th7h4bt1MOJga X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758584835255855924?= X-GMAIL-MSGID: =?utf-8?q?1758584835255855924?= This is a partial merge of [1], subject to be dropped if a header update is executed. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21480/ Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a2xx.xml.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h index afa6023346c4..b85fdc082bc1 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h @@ -1060,6 +1060,12 @@ enum a2xx_mh_perfcnt_select { AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, }; +enum perf_mode_cnt { + PERF_STATE_RESET = 0, + PERF_STATE_ENABLE = 1, + PERF_STATE_FREEZE = 2, +}; + enum adreno_mmu_clnt_beh { BEH_NEVR = 0, BEH_TRAN_RNG = 1, From patchwork Thu Feb 23 01:47:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60748 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp57532wrd; Wed, 22 Feb 2023 17:52:29 -0800 (PST) X-Google-Smtp-Source: AK7set+FSF2EbSqz3reJdEdCHP1374NdjVSMXuVoD68N0cUMeTxFOnBR5ovCgqm6Efi0txUvElJk X-Received: by 2002:a05:6402:1482:b0:4af:573c:c160 with SMTP id e2-20020a056402148200b004af573cc160mr6908168edv.24.1677117149514; Wed, 22 Feb 2023 17:52:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677117149; cv=none; d=google.com; s=arc-20160816; b=xP5WGeTMWgLgAw92MQT7w0hBxfigS73Mr7rlWracfvbsOzIbg8YIDITilyqgLgUZjN LSRrga4a7m8Iw+/5VNPFyVNano65aAoySmVWO2edrCJW4d3/WoOMlBMkHZckx6qpLcik 2sMMnFa3goTqEnIpypdQcOexv4zSwH+ykmZ1u8GllpzWFmh92gzv928Wz6XQGVjPmhZI ypowF+HMPKAwD/9ihJgrgMtTNGqWKIofHZUOctKScV1BJsk91Pa/dQPvFPHTNX5LZyMn 5/hVJfDCm12Zmy0u5UeRZsfvgm9bH5X921KmCY0LU3hTccQKpCicscdSDmOnr1ec+VXZ SPAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=0I63GzqZ4/pdwcdXOU5rzNuBienj4oVxRvi/wF6aWHM=; b=qPVzP2LC9t9ifLp0tNnBuArHzuOe5Uu96PGmXoVt8KLR66lidqzEpc9sfkHfL1znrU K+ir/tOx8UZvZZoabWlruHacY8ly9Bur7y9VMPRO9Fnw8xkZQJ1EzlL2yHzzeSGsebkg 9UXwICIYYOtGP0uHd7FO0oSGG47C8SeUsSMM9a7WbzMiKNPTgLWWp1KBMxgTWe5M+uG6 jM1MBLdPf1geGcZBAjQhcaTz64FlS8/PadzqXsm6BAYVgJvEGJeuHDfzBLdlSR8OPtRz vHfM3fTTtf2lD2yQUl/mWiLj+uM/Ecyi9IL6NGkjs3elgT9Xwl84/8y+w/BK7FJrsIOr +bRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lqbt+WCs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:41 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:38 +0100 Subject: [PATCH v2 2/6] drm/msm/adreno: Use OPP for every GPU generation MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v2-2-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=6235; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZLdJVtXa5OKKmfHA12Ep31JDGaPgYsonm/CsCSOeZZM=; b=j3U8ryJ7Pa3zdIXcfPRy23GXdpn9yPokiQ7mfYAzTieE3Gpo7ryz1533HQvPz+0QDeSF/Y9E8cMj Td95oUplAlRZddmwjbCPMx2UoOKLYhWDSbzDtFjUplLEpw4u/C5Q X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758584791921018758?= X-GMAIL-MSGID: =?utf-8?q?1758584791921018758?= Some older GPUs (namely a2xx with no opp tables at all and a320 with downstream-remnants gpu pwrlevels) used not to have OPP tables. They both however had just one frequency defined, making it extremely easy to construct such an OPP table from within the driver if need be. Do so and switch all clk_set_rate calls on core_clk to their OPP counterparts. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 99 +++++++++++++++------------------ drivers/gpu/drm/msm/msm_gpu.c | 4 +- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- 3 files changed, 48 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index ce6b76c45b6f..8721e3d6231a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -922,73 +922,48 @@ void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) ring->id); } -/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ -static int adreno_get_legacy_pwrlevels(struct device *dev) -{ - struct device_node *child, *node; - int ret; - - node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); - if (!node) { - DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n"); - return -ENXIO; - } - - for_each_child_of_node(node, child) { - unsigned int val; - - ret = of_property_read_u32(child, "qcom,gpu-freq", &val); - if (ret) - continue; - - /* - * Skip the intentionally bogus clock value found at the bottom - * of most legacy frequency tables - */ - if (val != 27000000) - dev_pm_opp_add(dev, val, 0); - } - - of_node_put(node); - - return 0; -} - -static void adreno_get_pwrlevels(struct device *dev, +static int adreno_get_pwrlevels(struct device *dev, struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); unsigned long freq = ULONG_MAX; struct dev_pm_opp *opp; int ret; gpu->fast_rate = 0; - /* You down with OPP? */ - if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) - ret = adreno_get_legacy_pwrlevels(dev); - else { - ret = devm_pm_opp_of_add_table(dev); - if (ret) - DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); - } - - if (!ret) { - /* Find the fastest defined rate */ - opp = dev_pm_opp_find_freq_floor(dev, &freq); - if (!IS_ERR(opp)) { - gpu->fast_rate = freq; - dev_pm_opp_put(opp); + /* devm_pm_opp_of_add_table may error out but will still create an OPP table */ + ret = devm_pm_opp_of_add_table(dev); + if (ret == -ENODEV) { + /* Special cases for ancient hw with ancient DT bindings */ + if (adreno_is_a2xx(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 200 MHz.\n"); + dev_pm_opp_add(dev, 200000000, 0); + } else if (adreno_is_a320(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 450 MHz.\n"); + dev_pm_opp_add(dev, 450000000, 0); + } else { + DRM_DEV_ERROR(dev, "Unable to find the OPP table\n"); + return -ENODEV; } + } else if (ret) { + DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); + return ret; } - if (!gpu->fast_rate) { - dev_warn(dev, - "Could not find a clock rate. Using a reasonable default\n"); - /* Pick a suitably safe clock speed for any target */ - gpu->fast_rate = 200000000; + /* Find the fastest defined rate */ + opp = dev_pm_opp_find_freq_floor(dev, &freq); + + if (IS_ERR(opp)) + return PTR_ERR(opp); + else { + gpu->fast_rate = freq; + dev_pm_opp_put(opp); } DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); + + return 0; } int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, @@ -1046,6 +1021,20 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_rev *rev = &config->rev; const char *gpu_name; u32 speedbin; + int ret; + + /* + * This can only be done before devm_pm_opp_of_add_table(), or + * dev_pm_opp_set_config() will WARN_ON() + */ + if (IS_ERR(devm_clk_get(dev, "core"))) { + /* + * If "core" is absent, go for the legacy clock name. + * If we got this far in probing, it's a given one of them exists. + */ + devm_pm_opp_set_clkname(dev, "core_clk"); + } else + devm_pm_opp_set_clkname(dev, "core"); adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); @@ -1070,7 +1059,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.nr_rings = nr_rings; - adreno_get_pwrlevels(dev, gpu); + ret = adreno_get_pwrlevels(dev, gpu); + if (ret) + return ret; pm_runtime_set_autosuspend_delay(dev, adreno_gpu->info->inactive_period); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 380249500325..cdcb00df3f25 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -59,7 +59,7 @@ static int disable_pwrrail(struct msm_gpu *gpu) static int enable_clk(struct msm_gpu *gpu) { if (gpu->core_clk && gpu->fast_rate) - clk_set_rate(gpu->core_clk, gpu->fast_rate); + dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); /* Set the RBBM timer rate to 19.2Mhz */ if (gpu->rbbmtimer_clk) @@ -78,7 +78,7 @@ static int disable_clk(struct msm_gpu *gpu) * will be rounded down to zero anyway so it all works out. */ if (gpu->core_clk) - clk_set_rate(gpu->core_clk, 27000000); + dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); if (gpu->rbbmtimer_clk) clk_set_rate(gpu->rbbmtimer_clk, 0); diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index e27dbf12b5e8..ea70c1c32d94 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -48,7 +48,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); mutex_unlock(&df->lock); } else { - clk_set_rate(gpu->core_clk, *freq); + dev_pm_opp_set_rate(dev, *freq); } dev_pm_opp_put(opp); From patchwork Thu Feb 23 01:47:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60747 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp57336wrd; Wed, 22 Feb 2023 17:51:53 -0800 (PST) X-Google-Smtp-Source: AK7set/xOzEUtu2O2i6GPLMxIRxpk52gnZOLd/uEx8EyqyuLLsToJ/hnwTACGqStd9DKBeBvTqkF X-Received: by 2002:a17:907:3e15:b0:8b2:fb3d:95e6 with SMTP id hp21-20020a1709073e1500b008b2fb3d95e6mr27341153ejc.74.1677117112969; Wed, 22 Feb 2023 17:51:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677117112; cv=none; d=google.com; s=arc-20160816; b=d0vYGv3xgW7T+Z8bVV0JjDNxWmwKoWO7eNwsMMO8+choiUWIRJRCv+EYVDXufa0rvZ AVPx7GEK+KqbROUpZvYn7TaRQb6sRS0UmSHEEIPp2/7D6JDgXFbAqEBzT75DrtfbfXRg 4EBNtuJYGcC2I/USDeS1TZmCnLwj7Wb3vahjDqYJH6pqnb+epJqjTtvAXINe/0x4KzMI cjiDqkQttGtJeIdkO2eF9d2qHz3PM3YDOT2+SdLFAmAVII1RwqbXtSVyOut1mWpb1NaF 4zwyoZq4h2HoxWl49fXiTan/W2m6iK3qNfWoD4XQdKRvP7SPjHtbmIupm3NAmRh/NfqN VE6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=E5+yg0/0krNLTPpeG4iJfNpIusLghNH594MfKs2+GeE=; b=Ufpn2Z4WGLsFCwXJyZzrRluaeW3LkL09B5LD7NKrliNvJPys/fD2gVA6X7wSy/0D6v K//vBFpVgW0RtlH9rqLgVTHRvtSEV7Dyi8px4gSO2Do/hwjKtyUyYJhC3iYms2jLLTnQ dGuKXU5eu0Wd+EoAl2StPDFEc8Lhgm/URnMGNo4l52f8cBJDWqhhT/GTABJ6XMI/4aqO ojQDf2WW8JIEle0oJ/vCtBWqpqnIKh5gud4foEKCza8otBcZvQNCqY/ajoPhuSN8xV2f +ypl1lLH638NqsZeHDctciBlJOJ2/P592qzrSDKF2VzMEyYCNiBksAbQ7R25FR4tx4gZ wxUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VusN6O7f; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:43 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:39 +0100 Subject: [PATCH v2 3/6] drm/msm/a2xx: Implement .gpu_busy MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v2-3-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=2023; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=o2IJoNBHAOSR6oYp4+Uz08OuccC4IUsqkONjhNT3F0Q=; b=s5/hbhoiSbqwQp+Bkv9gVx0WwGsnEjR+kvSlH359RLCiLjLo6w9Ek4Y4RWaXdFQy9iukWvt19fpG zU+0c93AADckr0oItDowSnXRKpk58/ORvjCDnY3rxbK1odDVmjDT X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758584753778130774?= X-GMAIL-MSGID: =?utf-8?q?1758584753778130774?= Implement gpu_busy based on the downstream msm-3.4 code [1]. This allows us to use devfreq on this old old old hardware! [1] https://github.com/LineageOS/android_kernel_sony_apq8064/blob/lineage-16.0/drivers/gpu/msm/adreno_a2xx.c#L1975 Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c index c67089a7ebc1..6f9876b37db5 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -481,6 +481,29 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) return aspace; } +/* While the precise size of this field is unknown, it holds at least these three values.. */ +static u64 a2xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + /* Freeze the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_FREEZE); + + busy_cycles = gpu_read64(gpu, REG_A2XX_RBBM_PERFCOUNTER1_LO); + + /* Reset the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_RESET); + + /* Re-enable the performance monitors */ + gpu_rmw(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, BIT(6), BIT(6)); + gpu_write(gpu, REG_A2XX_RBBM_PERFCOUNTER1_SELECT, 1); + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_ENABLE); + + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -502,6 +525,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a2xx_gpu_busy, .gpu_state_get = a2xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = a2xx_create_address_space, From patchwork Thu Feb 23 01:47:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60749 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp57596wrd; Wed, 22 Feb 2023 17:52:40 -0800 (PST) X-Google-Smtp-Source: AK7set+s+Mf1b0nzFHNNm6TdVozcPfDCxQ+uu/wzh2LJD+FdE6Ed4sEf1/NygqQtVghbLm1AJbcd X-Received: by 2002:a05:6402:783:b0:4ab:1625:908d with SMTP id d3-20020a056402078300b004ab1625908dmr10343299edy.16.1677117160760; Wed, 22 Feb 2023 17:52:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677117160; cv=none; d=google.com; s=arc-20160816; b=F0VjGB3mL8S0AJRijDxpps2OCXaL2ZELw0FsVIrBIGM44Q9YK6qRItVd9f/mRtHF7O N3uSEbyL9e31hG+xt4rUJ1HNU0+pf06MvBtVkg4CUHYVQxxF0BlAGPwJmkaIUE9s5aQt Tnwp2W/PtOPea+ClBoLfQn2JQtmuAXibHz4d3aXgK+xQGakIn8t7o0sV8PRbqunqAMZf nPMLZKKicol0frvwShuJPs1Z73iH69l15EIz9P/1CNWxfXjZ7vxWjUhBez9+4gxTM6ON FRvo6YJzDPbtUwP2s+9eHd4DecjvuNpbRC0HDfYuF/Ytiq03AiRDGJeW+fm/q8h7cBeo ggKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=4RozdFg8UcjNGaMEUfY94uV2Q1ptXwQxOYUwNdKHWzQ=; b=EdVj0NmcMUbp27TFh76rJWfj30WoxdkWSOBuxpu+ahSCqolX6PLq61cxBTe+6haGaj 0O/qUr54eOTZfBwxwyMQZD6Ik49aFakOicqfn4P3vVYAPtE4RzWVIAJWOoVzv1QtwX6q eY2ubcgGrA/WWjWSKkip8+w1azBMK4dsE60Le5qBc9SPivuHKOHrc8prXlrCmSxS8vn2 naShMFRURtdoTnBlsK5ZzPybnvgCyB32YmQHlnPlE2DuwWR/y9/3OxlZHTI2+OZE0ASE 0Goy52gWmNedftfTuz06v9XHH7GTOGm96oHoXJnYNS3kRsIO6f0iOcmpynlMob8iF+k+ Nqig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=esohPNul; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:44 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:40 +0100 Subject: [PATCH v2 4/6] drm/msm/a3xx: Implement .gpu_busy MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v2-4-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=1452; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=sAA92dCqoQlGesDQKUB68UAlcg2YIqQbh8UmjiEN524=; b=GVnaZnlQ6N+BD1eAG7ueoV0GF0HZZ3QeXEdiAAHLSxSj/otEEt/esgibqfS+fVabGvCIunPtJz75 w8iUO2JPBBZO7i/A1THaoFJbtoSTtLJ5z0wq/ODIxwXqLY6lcU75 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758584803915638362?= X-GMAIL-MSGID: =?utf-8?q?1758584803915638362?= Add support for gpu_busy on a3xx, which is required for devfreq support. Tested-by: Dmitry Baryshkov #ifc6410 Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 948785ed07bb..c86b377f6f0d 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -477,6 +477,16 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu) return state; } +static u64 a3xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + busy_cycles = gpu_read64(gpu, REG_A3XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -498,6 +508,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a3xx_gpu_busy, .gpu_state_get = a3xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = adreno_create_address_space, From patchwork Thu Feb 23 01:47:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60752 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp57877wrd; Wed, 22 Feb 2023 17:53:31 -0800 (PST) X-Google-Smtp-Source: AK7set91Z7PsZikcxoYQjCudAug8abVPnQcl/3B5X+Z7hekBi82S+D+3LOQHNpXnzRZSendLdZiC X-Received: by 2002:a17:907:9629:b0:870:baa6:6762 with SMTP id gb41-20020a170907962900b00870baa66762mr21568242ejc.14.1677117210838; Wed, 22 Feb 2023 17:53:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677117210; cv=none; d=google.com; s=arc-20160816; b=V4MX4H6VFiLlnuSLcRel4aFeN8BZCSZfQxRZomjBRTqYQCu3zzNoSWtxk9jRH8GSiM KmRGCnmXrPvEqc2q2NGD7A8LIHSC5hO+TlbFdiVUuHJn3UNAKFObvE8DumsamU1V0JIW wwXvW7fqkIj0mcR+4CPuExkOXtmA/6YJDBm3kGscYJj9q/HaYp/KN1nvRoDxCz/NsjCl 4A3aoXe2YzeeO6KoQWJkTOAIOrsFNtroB8HqBVzD4n16jyQogzT49sIGtvk/fT3fvUl/ 2z5YnnvohTFQAGvZR8zZfHyrXoaINRVQ9neOFJdIWwF0F8zg+/9icJGJvzI1jzhCEGbh tCDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=GGhJ8k8BvYcG4UvdUcw3fi971zbE82bjXqWQD3F+nXY=; b=piVUBZmIZeSi0D8kIuSEuxWayRR8u2M7C9GdFlAGoZ5URS22NuoKmmbz0jeiIddZbz OlirKJk8gQ+TmnFTspOz2uQtqUpZVhFoXcmGAVONmCtis3jOiYUcbMDqrHqdmuxwdDC+ +ybfHQWvGG8B50pLG2KSSmdd0s6jyXPpICw2dudTkOcgzQEBL0PJytHnCFbzBmfFoBOg cf2jVdTLT/EU5VrPHmPZYT0SDjASGVQOjkiMH4BBq56zt2NKE8lr5E7aIaPK6a6ggKz8 icar2o9k4esG5lBjQJMPCYq/xxPvPRO0hizq41ntVbCfWRwvDsP8uLSsUT6fECeyPYJw RGFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ldmW/ilz"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:45 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:41 +0100 Subject: [PATCH v2 5/6] drm/msm/a4xx: Implement .gpu_busy MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v2-5-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=1379; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Mfqjq6oPzn0mWycAv8UA9lcR+KDEDYvYmMvB7YZF6m4=; b=Mfz5NyNGrq9Nm2ebit78yYPih/DJD0y9rsEuSb/O6TQITG+HY8Lpy7U/ZcaAMxslu1ZDXovwWvec Sl2idkBSBQcCcNyqzRAVoMvNDIdkXp2SWe4SvswlugR1Av5gR6yI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758584856270369819?= X-GMAIL-MSGID: =?utf-8?q?1758584856270369819?= Add support for gpu_busy on a4xx, which is required for devfreq support. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 3e09d3a7a0ac..715436cb3996 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -611,6 +611,16 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) return 0; } +static u64 a4xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + busy_cycles = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a4xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR); @@ -632,6 +642,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a4xx_gpu_busy, .gpu_state_get = a4xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = adreno_create_address_space, From patchwork Thu Feb 23 01:47:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60751 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp57873wrd; Wed, 22 Feb 2023 17:53:29 -0800 (PST) X-Google-Smtp-Source: AK7set81wuALdZFUAvWNo37MN+as1isLK2ObT3mSxVzDij3zGleoQ/9xCP+zhp5St/r5mGS+at2J X-Received: by 2002:a17:90b:1b0f:b0:237:2edb:d4e3 with SMTP id nu15-20020a17090b1b0f00b002372edbd4e3mr6697294pjb.27.1677117209503; Wed, 22 Feb 2023 17:53:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677117209; cv=none; d=google.com; s=arc-20160816; b=qgPWSSCTiZGRcyRZhyqLE82nSZUQiILLN6SFWA7unWMuzsFB2FtM2Ry/kVDt88MgWf 3+eqZcD0KpTMgryAQCXw0uNfb+jxIdKlcz5deOJZAuiAcOrTzHCIMnhcHphiI9h/8CIG YFLp7Sjvytxconb2PlTN20Jv41a6iSRZHBRgOJOzCHvco/WTplDUOTANUltgmx1SRJFi d2KEh7cIIyazxLW+JUFmTdTtMurMn0hKjS03hMdXNCY6C0ojJG23C7PNOrsGoaR8bxbH tvIL90cQexPYnINAaAHtBDE5EwZ8X2iToaUdjaUO3bwFtn2k86SZL1FiomofgNo/Gb1l YYkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=Uw9ANW8A0HIEHlu0J95K8GI8spDLrbsMISUzwV0ijx4=; b=enB3owuIT7Q8G67aAIb8573Us6DX2DtyQyzCuwqcxT3Ro1SIhJbDUQo1Pa8xWRaZJY 8CnKcLDPijzrHgA0coGxAWbevAJJDr7AUr7MX5ogu9+7RdtxNXKSjSCmh0ZZfbC8tguY LFCJ9d10AI+45efnUgOr7HD6bifzip8nmN0gAvQ62E6lNvp/inw2JnptBF1he4RmHC7G B+apufOG8s3p6hnefYi9peDJdYOWuB2Q29cfBD2SqvvTg1Y7eHTANkr1B5Foc2/w/1x8 FiN6vlXqXTBtKqI9WF/FLNZCUQAMd2oogIjRModZKEBjggVuk8i0VVemR/zZMtnTh+s2 Q/eQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tQWLe5Wc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id 12-20020ac2482c000000b004dc807b904bsm427376lft.120.2023.02.22.17.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 17:47:46 -0800 (PST) From: Konrad Dybcio Date: Thu, 23 Feb 2023 02:47:42 +0100 Subject: [PATCH v2 6/6] drm/msm/adreno: Enable optional icc voting from OPP tables MIME-Version: 1.0 Message-Id: <20230223-topic-opp-v2-6-24ed24cd7358@linaro.org> References: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> In-Reply-To: <20230223-topic-opp-v2-0-24ed24cd7358@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677116858; l=767; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=lx2DqRTcWzcl/VYcOjFYV+HDGYAZOMxix7RaJuIvTv8=; b=mYkZ7qwqRbSRNaoLVDbG+NeuUgSJomROk/h9vglxkqTqHBuqRkB9BIoLFrYD7vD+bXjLGT7PYIoJ MeljqooSASz7mlvRrVYqcvglbqNK7hJ+uUF4kGeKVT8KaExP5mtI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758584855032004835?= X-GMAIL-MSGID: =?utf-8?q?1758584855032004835?= Add the dev_pm_opp_of_find_icc_paths() call to let the OPP framework handle bus voting as part of power level setting. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 36f062c7582f..5142a4c72cfc 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -548,6 +548,10 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(gpu); } + ret = dev_pm_opp_of_find_icc_paths(dev, NULL); + if (ret) + return ret; + return 0; }