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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:12 -0800 (PST) From: Konrad Dybcio Date: Wed, 22 Feb 2023 22:47:10 +0100 Subject: [PATCH 1/5] drm/msm/adreno: Use OPP for every GPU generation MIME-Version: 1.0 Message-Id: <20230222-konrad-longbois-next-v1-1-01021425781b@linaro.org> References: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> In-Reply-To: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=6142; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=XjCTxbeQ2g0wp3MiyX1zJyPLmA7rilIPN/CTVTjyz6M=; b=NWCfHrmYdFscaF+ZYcQO7FL3I6ZLWXdqVlElXTGvme3D9qz6OouxYc83qnwpMTuc1El3Yz+FLhWB 7FrMDyr3ALLVmn23zBM3AarmXDFJ4QvR3NuDoO98ZEbX4/9vjaRp X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758569632660336348?= X-GMAIL-MSGID: =?utf-8?q?1758569632660336348?= Some older GPUs (namely a2xx with no opp tables at all and a320 with downstream-remnants gpu pwrlevels) used not to have OPP tables. They both however had just one frequency defined, making it extremely easy to construct such an OPP table from within the driver if need be. Do so and switch all clk_set_rate calls on core_clk to their OPP counterparts. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 94 +++++++++++++++------------------ drivers/gpu/drm/msm/msm_gpu.c | 4 +- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- 3 files changed, 45 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index ce6b76c45b6f..9b940c0f063f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -922,73 +922,50 @@ void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) ring->id); } -/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ -static int adreno_get_legacy_pwrlevels(struct device *dev) -{ - struct device_node *child, *node; - int ret; - - node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); - if (!node) { - DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n"); - return -ENXIO; - } - - for_each_child_of_node(node, child) { - unsigned int val; - - ret = of_property_read_u32(child, "qcom,gpu-freq", &val); - if (ret) - continue; - - /* - * Skip the intentionally bogus clock value found at the bottom - * of most legacy frequency tables - */ - if (val != 27000000) - dev_pm_opp_add(dev, val, 0); - } - - of_node_put(node); - - return 0; -} - -static void adreno_get_pwrlevels(struct device *dev, +static int adreno_get_pwrlevels(struct device *dev, struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); unsigned long freq = ULONG_MAX; struct dev_pm_opp *opp; int ret; gpu->fast_rate = 0; - /* You down with OPP? */ - if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) - ret = adreno_get_legacy_pwrlevels(dev); - else { - ret = devm_pm_opp_of_add_table(dev); - if (ret) - DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); - } - - if (!ret) { + /* devm_pm_opp_of_add_table may error out but will still create an OPP table */ + ret = devm_pm_opp_of_add_table(dev); + if (ret == -ENODEV) { + /* Special cases for ancient hw with ancient DT bindings */ + if (adreno_is_a2xx(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 200 MHz.\n"); + dev_pm_opp_add(dev, 200000000, 0); + gpu->fast_rate = 200000000; + } else if (adreno_is_a320(adreno_gpu)) { + dev_warn(dev, "Unable to find the OPP table. Falling back to 450 MHz.\n"); + dev_pm_opp_add(dev, 450000000, 0); + gpu->fast_rate = 450000000; + } else { + DRM_DEV_ERROR(dev, "Unable to find the OPP table\n"); + return -ENODEV; + } + } else if (ret) { + DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); + return ret; + } else { /* Find the fastest defined rate */ opp = dev_pm_opp_find_freq_floor(dev, &freq); - if (!IS_ERR(opp)) { + + if (IS_ERR(opp)) + return PTR_ERR(opp); + else { gpu->fast_rate = freq; dev_pm_opp_put(opp); } } - if (!gpu->fast_rate) { - dev_warn(dev, - "Could not find a clock rate. Using a reasonable default\n"); - /* Pick a suitably safe clock speed for any target */ - gpu->fast_rate = 200000000; - } - DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); + + return 0; } int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, @@ -1046,6 +1023,17 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_rev *rev = &config->rev; const char *gpu_name; u32 speedbin; + int ret; + + /* This can only be done here, or devm_pm_opp_set_supported_hw will WARN_ON() */ + if (IS_ERR(devm_clk_get(dev, "core"))) { + /* + * If "core" is absent, go for the legacy clock name. + * If we got this far in probing, it's a given one of them exists. + */ + devm_pm_opp_set_clkname(dev, "core_clk"); + } else + devm_pm_opp_set_clkname(dev, "core"); adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); @@ -1070,7 +1058,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.nr_rings = nr_rings; - adreno_get_pwrlevels(dev, gpu); + ret = adreno_get_pwrlevels(dev, gpu); + if (ret) + return ret; pm_runtime_set_autosuspend_delay(dev, adreno_gpu->info->inactive_period); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 380249500325..cdcb00df3f25 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -59,7 +59,7 @@ static int disable_pwrrail(struct msm_gpu *gpu) static int enable_clk(struct msm_gpu *gpu) { if (gpu->core_clk && gpu->fast_rate) - clk_set_rate(gpu->core_clk, gpu->fast_rate); + dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); /* Set the RBBM timer rate to 19.2Mhz */ if (gpu->rbbmtimer_clk) @@ -78,7 +78,7 @@ static int disable_clk(struct msm_gpu *gpu) * will be rounded down to zero anyway so it all works out. */ if (gpu->core_clk) - clk_set_rate(gpu->core_clk, 27000000); + dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); if (gpu->rbbmtimer_clk) clk_set_rate(gpu->rbbmtimer_clk, 0); diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index e27dbf12b5e8..ea70c1c32d94 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -48,7 +48,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); mutex_unlock(&df->lock); } else { - clk_set_rate(gpu->core_clk, *freq); + dev_pm_opp_set_rate(dev, *freq); } dev_pm_opp_put(opp); From patchwork Wed Feb 22 21:47:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60699 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp829933wrd; Wed, 22 Feb 2023 13:50:21 -0800 (PST) X-Google-Smtp-Source: AK7set/lXujNg827LLfJ376X7TXiYxV594JwwriSH66Zn82tdX6uOL+STUD/+2icdeRODdBgB0Bo X-Received: by 2002:aa7:de13:0:b0:4ae:eb0f:4258 with SMTP id h19-20020aa7de13000000b004aeeb0f4258mr10212318edv.30.1677102621582; Wed, 22 Feb 2023 13:50:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677102621; cv=none; d=google.com; s=arc-20160816; b=cxD5Nw6CUzE25JQAdKQL+L2H977M8WM1CAxjyd0pmUnQtHv/RBS2blusulO1KkQ0EU MYn0ON9nVHKI9dgxe2AWwd83WJLs6oDzPr7AUBOwinA4fK957/hp0A3HehlvWmaNGBDe OJA99KCWVgVa3fRdBJZxSPT6On/5ZqFdoZ+mpMaGp6qmOQHpbmoCN59Yi1BtixfOv4Au egxM42aDCWKw907o7wZ3Oe9VJh5f6AcyEEc3tMBPfDNb+xDBCOm+u48IXXAwA4XzZGC8 cUW3BheFSKh0DLOoklP8LxI/wI+0mGHNx4h0uPEeTpxbblJ4GuGAEmuntvw9i8jhWFH4 qwtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=x5gYrnK/HoZ6yr2V7D097iQ8J8n4YHC77+UaKju5N+Q=; b=PC4hhRgb16uTXokaUWSYq7ngXUOwaZ9X7spZwudBZ1+XWJDBCecIvO06z9Pd8MilDe 8l7SmnGJWzZlvc+N3j9rB9UumEEivmgWA/E8JWGllYRkQ//4Dr0Moq1mQVeHRIxglaWq 1sph+rshPYetDujmyuiWyqKSFAItMMOCt2IFUguDvoLn+3/i8c4x8GKoIl9UvQZLhyGO ae0SPEsN7/OLBXkM7DNSdCMD7M6St1dkHr1/rXR82HeS2opjpYMn6Lt35VzYP1cYaA3Z jZgif4n1Myfyf7EZ82S8QYyaJsOZ4exhWabkHLLkv6lk2Os3e0MKOe5VrcnLDZYGr5e/ 1+gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mCXA83T3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:14 -0800 (PST) From: Konrad Dybcio Date: Wed, 22 Feb 2023 22:47:11 +0100 Subject: [PATCH 2/5] drm/msm/a2xx: Implement .gpu_busy MIME-Version: 1.0 Message-Id: <20230222-konrad-longbois-next-v1-2-01021425781b@linaro.org> References: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> In-Reply-To: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=2245; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=aOv4GpOcxYV0TegYhJBmwWoY68FI0H+2TrCshMKIIzs=; b=0OCPjYibSX+1IERZyu2BRoD05ys93RHFHJC69kwCa2fK2MoMZ7eN3CZd5G2p2wqPjAYeWIgEKIMK Tb6k+0SdB2SeaUXBlUrMeHAOl8klFw8++PiOSp/d9sF0R3zB5xlD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758569558524308883?= X-GMAIL-MSGID: =?utf-8?q?1758569558524308883?= Implement gpu_busy based on the downstream msm-3.4 code [1]. This allows us to use devfreq on this old old old hardware! [1] https://github.com/LineageOS/android_kernel_sony_apq8064/blob/lineage-16.0/drivers/gpu/msm/adreno_a2xx.c#L1975 Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c index c67089a7ebc1..6258c98e5a88 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -481,6 +481,33 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) return aspace; } +/* While the precise size of this field is unknown, it holds at least these three values.. */ +#define PERF_MODE_CNT GENMASK(2, 0) + #define PERF_STATE_RESET 0x0 + #define PERF_STATE_ENABLE 0x1 + #define PERF_STATE_FREEZE 0x2 +static u64 a2xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + /* Freeze the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_FREEZE)); + + busy_cycles = gpu_read64(gpu, REG_A2XX_RBBM_PERFCOUNTER1_LO); + + /* Reset the counter */ + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_RESET)); + + /* Re-enable the performance monitors */ + gpu_rmw(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, BIT(6), BIT(6)); + gpu_write(gpu, REG_A2XX_RBBM_PERFCOUNTER1_SELECT, 1); + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_ENABLE)); + + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -502,6 +529,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a2xx_gpu_busy, .gpu_state_get = a2xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = a2xx_create_address_space, From patchwork Wed Feb 22 21:47:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60700 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp829941wrd; Wed, 22 Feb 2023 13:50:23 -0800 (PST) X-Google-Smtp-Source: AK7set9bd7mmFmkLO/zEliMziC0RcNrb1qT1rDv2vst8xM8kMPKFQq0IWw6B/nGy/VMrbSy9Jvom X-Received: by 2002:aa7:c70b:0:b0:4af:6a7e:9218 with SMTP id i11-20020aa7c70b000000b004af6a7e9218mr920660edq.42.1677102623173; Wed, 22 Feb 2023 13:50:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677102623; cv=none; d=google.com; s=arc-20160816; b=K2hUdOGdjadtJAK+wos8GENhY4JQQVksn8SNsjqvgaeNIW+G+PtQkXOzaQjgr6xrlT cZ8G+8fPcvBhTyo8/lJj81V7hwvayhj1kX+zpHJhgKpXMcwXJA3A+q6hQSrOomZAQdyi 6rZToxwofdVu1DSI9f2dHJ1l9H8TQtU8baQMhAUZH0F9wfRsmQhiMC5eY11SZM9oUm/3 1TslsaEC5Htm2TIaH7ww5bBQs7TjKfGH+b8hK12Zj6dUHc53jFVuaE79hGnlMbK4a/yx wsyFEzi5A4gvCUzI43yA0niMvmIypIXbGYA3Mx2J5XDdeB51ClXdu0JCEAMvl9YKDsHX If2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=h4TOwLOMt599To1JExzRPWtUssAyU9NR4zE3oZiUZ+A=; b=F4I1ofrtL9iDlqpx+dIjcUQT7BrDC6rR46RRVaAaxbbOuYq9dm1z6kt4lVQVks/Hrd SbrEgDeVVJJdTWxwpPRgewZc7hcYY/2D6ukAC9dFQsfXgkPq8MpJFYBDK5De36TrEL0V VZuFXIOtvQXCI/LkiZzev0Y7zH5MOSMAEUse7u/srrmUTShrV3dqVf9e0wLAnxbPqQd5 eS79M3hnusD0TX9JsoH21V+CLyErWu+8bt70Rs2+2a1mzLg0Nsi+fQkXYkEGGeQF56Qm tSqYqCl58yXj96peIDlc2/cdt+X9PF3tKLeoxWELKXoxczpCXoeXxMJNVin/GjOKYcxQ BFYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vIL6E4WB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio Tested-by: Dmitry Baryshkov #ifc6410 Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 948785ed07bb..c86b377f6f0d 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -477,6 +477,16 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu) return state; } +static u64 a3xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + busy_cycles = gpu_read64(gpu, REG_A3XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); @@ -498,6 +508,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a3xx_gpu_busy, .gpu_state_get = a3xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = adreno_create_address_space, From patchwork Wed Feb 22 21:47:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60701 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp829946wrd; Wed, 22 Feb 2023 13:50:23 -0800 (PST) X-Google-Smtp-Source: AK7set84GuIlffdFJCbAc39n1Pcqs9ccM5cinwzCdWobPJN/jr4hfx1KG3lDl+Q6b9nshZ8qLyyN X-Received: by 2002:a17:906:f212:b0:8a9:f870:d25b with SMTP id gt18-20020a170906f21200b008a9f870d25bmr17058423ejb.15.1677102623658; Wed, 22 Feb 2023 13:50:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677102623; cv=none; d=google.com; s=arc-20160816; b=dokJEUaznCJOROHRSEg261bw2kE4Z77NYnNWyzjgIMMHTaOsNT3wXUgl9HBBemX4bm ZpBWl99WNNMpCs5FJII+LhYCQhMt03XgSKfyj1gnN0TWYAoXCEaiMlMANBLut1pDiMcG vMU7djBj2VHNmX0XjaPT7CKL6ol74Zo7RO5mhDzBNQCQFvqd3Rd/SDtEOygV5maPbCeD trZVMwQW9RHSbvb0gVvCVZCWpLxLuSaWmn+qgNsOk0gy8v7AnVsQPIOxlzUSD2dj1OPR S1fBLz+kHDQzGCnoG93alfR2+KTo5R9sOPJh84BQZTPQU+6atQEFukucjazZD808ZgnE xvxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=SBObAXrrIUPtcxXkSYb1/MPep4XlGTpRKBjzQvdnZZw=; b=stH610G0bVxDN8sNQPoR7HxK1gkjz2e/rpmBZdL1oUKHWvyV47dp5HGFmYxuopvJEy GwQMFIrn4eiO6LhcL+79hnq70VISJEhpUA4wf1+svKimMl20jbYiB1ieFtFutRT7xSZ9 MM19HuV1iOtGU4JHB6VImQmvgjmS155wtFZyQzX4zTtG0EFhpclHS+rpSKSoQKkgWSOy iYniEfaRNr7Np3TSHYJlA/ivuBGZjjjnZNv3ha0fv9vBcsYH4LKu233SMNQuBppwlhnk ELi/vX6o74UrY1rySERv40wgTFvL631bffBE/WJlRGKGrjOiB78E+Gy4ue/4bhOTbGKy draQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DYSfqZcq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 3e09d3a7a0ac..715436cb3996 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -611,6 +611,16 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) return 0; } +static u64 a4xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) +{ + u64 busy_cycles; + + busy_cycles = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_RBBM_1_LO); + *out_sample_rate = clk_get_rate(gpu->core_clk); + + return busy_cycles; +} + static u32 a4xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR); @@ -632,6 +642,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) .show = adreno_show, #endif + .gpu_busy = a4xx_gpu_busy, .gpu_state_get = a4xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, .create_address_space = adreno_create_address_space, From patchwork Wed Feb 22 21:47:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 60702 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp829971wrd; Wed, 22 Feb 2023 13:50:27 -0800 (PST) X-Google-Smtp-Source: AK7set/tmCNzXu6rac66YRWTehJddpgrbHY3h8+x6KLgnpFJU8D1uv/bCxI7HcPpp6UVqWElCXTu X-Received: by 2002:a17:906:8042:b0:8b1:788f:2198 with SMTP id x2-20020a170906804200b008b1788f2198mr22230835ejw.19.1677102627163; Wed, 22 Feb 2023 13:50:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677102627; cv=none; d=google.com; s=arc-20160816; b=ATaWyH/LwagjpniJj8gPuMdMiLr8eJSpdFK8CMVBscXdVxdS2yRNDUDxEdHuUPGMfE 5r/OV6cDAYKzf+oAAZat9larKDXCbP3L+CpPIC1gDeoKAYQ6odIH2/stqn5qGtOI9g4L L6Ux10TSsPtA5O+jQODaEZAw5brwTlod5WuQmRlfSnKzd7MJgBuCZzm2HQ9eLOuMVk/I JC3oW/lTd7aQyywrjWWH1TtbGi5imipNJmZfJOz/fgYFr3hfQUZyoWeOpHK1o67rQ25H 5fbnNJXfZ+ZmoOAYUmn1nv8+n+euDRg32bRRYt6DIE87V6pOsXWB1cYYpEwFL7Kx3ezI Zxpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=39aG+iURI09iswW6gk3gC6TBwToV0heQthXAeMfwVro=; b=iNADAHfFUDobAeNXXenrEx2vQsBuZ6g4ITEBjRQkUxjTVfzl/OckmOXeKckFZrvImp G93G8VvOktU+6mEbyCuHpRv0tgfsUOkLq40sUI1QRJkYCl3b4Gfa6ipnA/oSZJKDbSYM KnXfQ7Y9TQhvVflzNFYsy03MhHsz0+YgnT26+Tx5hYEfZ9CWDwbg3fuhB9l8ddZY9b8a ekR5mR6Vosc8UBhPb4KaaKfI2Ii+5C8TuZ4upWWCV8CVTHiLPESpNXHW2ozM7LzdQfCn Uagq/dUkNXJ0+1WwQsI8KV+kqu2Kd762dvu/5rRrILQ6kiGN/ptpsskrG3PSONJN0hVE JVjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HzIPoQRP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.151]) by smtp.gmail.com with ESMTPSA id c23-20020ac244b7000000b004db5081e3f7sm505126lfm.46.2023.02.22.13.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 13:47:18 -0800 (PST) From: Konrad Dybcio Date: Wed, 22 Feb 2023 22:47:14 +0100 Subject: [PATCH 5/5] drm/msm/a5xx: Enable optional icc voting from OPP tables MIME-Version: 1.0 Message-Id: <20230222-konrad-longbois-next-v1-5-01021425781b@linaro.org> References: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> In-Reply-To: <20230222-konrad-longbois-next-v1-0-01021425781b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1677102430; l=807; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=TMGW8gjkiQwEJ0fii5rrgM+Nl4d+tDtzpTg1fjmA9zo=; b=o1Nbuq1XpVhn6xnmPyYkuaAq0xiZ0aski/AfFD81WLJwQsE/JusmS5elxNiSQcEnM76oc3Ers35U eiDijrx9C0uZlUc59nitgz2e4VYiOpcCz4G/cJuX7NgFzniXRWFC X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758569564505163002?= X-GMAIL-MSGID: =?utf-8?q?1758569564505163002?= Add the dev_pm_opp_of_find_icc_paths() call to let the OPP framework handle bus voting as part of power level setting. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index d09221f97f71..a33af0cc27b6 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1775,5 +1775,9 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) /* Set up the preemption specific bits and pieces for each ringbuffer */ a5xx_preempt_init(gpu); + ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL); + if (ret) + return ERR_PTR(ret); + return gpu; }