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[2620:137:e000::1:20]) by mx.google.com with ESMTP id fy31-20020a1709069f1f00b008eb3867b243si322153ejc.46.2023.02.22.07.34.29; Wed, 22 Feb 2023 07:34:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nX0UqMMW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232523AbjBVPdR (ORCPT + 99 others); Wed, 22 Feb 2023 10:33:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232535AbjBVPdN (ORCPT ); Wed, 22 Feb 2023 10:33:13 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AACD3866E for ; Wed, 22 Feb 2023 07:33:11 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id cp7-20020a17090afb8700b0023756229427so442444pjb.1 for ; Wed, 22 Feb 2023 07:33:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gl2oK6m3W4idoG0++YXdR0eH/S7JB1Clcx3ixNJBnNA=; b=nX0UqMMW/E/UxVR2q2VD0VyQdZv/U42NNCRZwdTFx0DjM8Qyqtsg7ufdwoour0UicS wq1ZzUObu+TF5PHoVoH5zuoCj+k+M6DRqLhhkkmn11eyzeyNegyeA3TmxNu/ogBgVA7/ TF6RzsorxQ8e8lMsigtdFHwEpXi4mTgucncArvai3O1Lug3RECeqg3q1w+2xQxjjTM08 teK5+it+Nt0pXvwNWzSSGnmX4jp+A2iKSt2gOCmG4oEctC65y5rN8zZXxifQ/K7yhbDd ph25MXMBSO8ZE6ZiZljWEha52/6TxAARJJRyadNQgbnrkgBwtnt4RH+jiGVf5rh+jEGs ckbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gl2oK6m3W4idoG0++YXdR0eH/S7JB1Clcx3ixNJBnNA=; b=zy9dgja6zvW0HL3RY/e8CCXtHJ3AF2Ib9bzi64Txn8B5oHLoWfMYqvYHTMWZvKgPU5 3aRjD1bof76VotNW1FyfMQzCghrgcj9fU/LlGvoEAkQwSlLGzLRSG8u1jODovvarh1NF x4Qdjkwgio6J7PLVK+ngi3JZT54BB3EX0t+pNOe+0kQRIvxzyL9MA6bfJBe10IqqSq8E hBf2TOp/8VarnoCH2++bh+NBqoz8MjNoFq/z+wom6V1bOVW1BTBvNEItP8MOSCsTe5CE QSoGZ5TnwzAAfbBPoGmxeJppqvsYLpHd1xVQb0elxhu+symHZkKQ9k0AcVwTQUXOkYyh lh/g== X-Gm-Message-State: AO0yUKXNGS6ZiGkmAkXfRa5rdtk7oE92W+uHTk52SO8pSQmoPBNsSREW 5d6jB31PC+mqVXytaIeHWHtf X-Received: by 2002:a05:6a20:671a:b0:cb:7ae6:b42f with SMTP id q26-20020a056a20671a00b000cb7ae6b42fmr5975151pzh.62.1677079990532; Wed, 22 Feb 2023 07:33:10 -0800 (PST) Received: from localhost.localdomain ([117.216.123.15]) by smtp.gmail.com with ESMTPSA id f15-20020aa78b0f000000b005ac419804d3sm5222482pfd.186.2023.02.22.07.33.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 07:33:10 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 01/11] dt-bindings: PCI: qcom: Update maintainers entry Date: Wed, 22 Feb 2023 21:02:41 +0530 Message-Id: <20230222153251.254492-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230222153251.254492-1-manivannan.sadhasivam@linaro.org> References: <20230222153251.254492-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758545935685134877?= X-GMAIL-MSGID: =?utf-8?q?1758545935685134877?= Stan is no longer working with MMSOL and expressed his interest to not continue maintaining Qcom PCIe driver. Since I took over the driver maintainership, I'm stepping in to maintain the binding also. Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a5859bb3dc28..a3639920fcbb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -8,7 +8,7 @@ title: Qualcomm PCI express root complex maintainers: - Bjorn Andersson - - Stanimir Varbanov + - Manivannan Sadhasivam description: | Qualcomm PCIe root complex controller is based on the Synopsys DesignWare From patchwork Wed Feb 22 15:32:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 60579 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp643573wrd; Wed, 22 Feb 2023 07:34:56 -0800 (PST) X-Google-Smtp-Source: AK7set8F6pol8xc0x/3cwp5LVJl7nvutNPXZ5CR1iGJI+ZgH6qVg7PZGo4X7fUkMeSmrYZOCdHxc X-Received: by 2002:a17:907:75cf:b0:884:930:b017 with SMTP id jl15-20020a17090775cf00b008840930b017mr18246092ejc.60.1677080096184; Wed, 22 Feb 2023 07:34:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677080096; cv=none; d=google.com; s=arc-20160816; b=tMLbMZFEiVMQezPK4sXxQJV1WbdaPe148g0A98bBCDDflQYg+hi9doI1a8u476kO5a T6Drl0MqdeQkEKBGlBd4EOnPAaHhXRuZq6czwNeyn9uWmBVRA7HMZJOLLW8s9iEr9Q/v 3ytz6MFdWEIzQ7nCoWnsfxEIwQ/zKW/vmIqrpprCppe7kh9zYBy+Es/HepkPqn22Ef9R IS2gP1Ox+0IGZu8Bca1r0ZIz6+fLU2sZk6hqo4HEFdal7v73xo6HT/PDM+5jmZkAiczK FQvcQ9YtBbf6jMWT5LhpI/ic8AzgZvJuTeCUCoECIr89cYpLISGx28fA4BPDKFX8wIRG u39w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uGDet0K+1/m01Mue6GMZv5iNZBwdpYi4DRLEmHhKT40=; b=MJNW3J8vXP4ssEsGI1XwIRlu0IpaiUslru4WG7nTFIdqrLd0TkTOdPwjBeZo95PtpN xpQfazeBxGMaOJKd1y/f/Ze9yiixxtR0w3esScDnkyBT2UTjtfo2Q8yI73Bijxwo3xfc SqEytyWgMZ4k807ISyZyUNEshSphg9WCqhoVl3yRH/NM8o3tiIZ3DCWjTMJIUqQGHsvw p3rwAVOZiPy0wxtBcUo2uFlPJinmTOqw9nQUykUiS0cor4MtpbVaNve8hqgjStFT8a8L 5owHBLu51o3WqYftDFrU9tK5flZUcNgwM+KI8W2Ti/4xzorXCYrTCvVVGKkvotf1y41A YQew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e8OzNJHB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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So let's add them to the binding. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a3639920fcbb..f48d0792aa57 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -64,6 +64,11 @@ properties: dma-coherent: true + iommus: + maxItems: 1 + + iommu-map: true + interconnects: maxItems: 2 From patchwork Wed Feb 22 15:32:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 60582 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp643846wrd; Wed, 22 Feb 2023 07:35:30 -0800 (PST) X-Google-Smtp-Source: AK7set/1SCv2NBHBlNUvHxkWVaLNPwokSjK8eyh1RFFr2B25RUJ/IXLHkYMQHhAT6BKeMKz1SVNH X-Received: by 2002:a17:906:64a:b0:8b1:2c2d:4658 with SMTP id t10-20020a170906064a00b008b12c2d4658mr15591815ejb.33.1677080130606; Wed, 22 Feb 2023 07:35:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677080130; cv=none; d=google.com; s=arc-20160816; b=x8YBou9YHjUIDulT/GDnBJwwkg6iVuUdIHHnYJRp8e9XJ389duMjmkNXRN0dKQ6pev X0QLUh6xVl/qi9I4OhbbcyZiDzK22wTTggY+cKGOa4+sPyuCVsgnwMRSDhoRdyzioucY AigC9IU+D2Rv3otlEkbCB1rsKbMU4bbHsZs6d8SOIYIAWjbgSxnFVvyGYlSWwph2bqxZ vhPErcGUc/fJ4tFudeBRuS/t2hQOgKPyM8c/wLDHgs3LgG5ecRRGxgUGyEQHAot5AEYY eCExlm+RHuL+NTzRwsWrq6Sh+bvyIXczNBdiYjwVxCpUfcSvPOCE4k4KNKBN8qKGPCpS 4UkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LMSvnDU64o95J5N9i3H4OYKYP+QezDC8GOgpgloFHv8=; b=fBbXvwdIbhFDOVe8AGcArICfj4GHjbfhHB4YoyMka/wvN9iNpWip8sT01Rn2zcdInk D3rLEEn2HYKXnWsbf67lQ19GUZJ6GTwGdT0LKCKPpC+gtKq+Ds33vEiwyTuT+wPK+28B U1PAfdGi80rUOpHX62ubUO0vu9HOrH/t51Ab8Bt47xP8uEN5lAyusYwAl2aix3f2S7pA FfQCPBFNdarsfQMrlLZN4cREp+PnsXdizvf56GFIfxR49Tmfa/p6SQAJ0iSVg0AtXmtB WGLFFLFUv5tQOgiYCOwZuOHIcn1NanBZ8eyjk4RXo5/FZQwjbhPbgirrUByj/8L8tsCr K3XQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GDFmvn86; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index f48d0792aa57..3bba1ef3cff5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -30,6 +30,7 @@ properties: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdm845 + - qcom,pcie-sdx55 - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 @@ -199,6 +200,7 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sc8280xp + - qcom,pcie-sdx55 - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 @@ -646,6 +648,32 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sdx55 + then: + properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: sleep # PCIe Sleep clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: properties: compatible: From patchwork Wed Feb 22 15:32:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 60580 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp643706wrd; Wed, 22 Feb 2023 07:35:14 -0800 (PST) X-Google-Smtp-Source: AK7set+I1SjCic3hF3+iG5vc0D6XuaVu1OYfI2NJiBW/ZNDMxZdblZCuVvBCk4Q4PlN4g+FE7LcC X-Received: by 2002:a17:906:3ec9:b0:86f:fbcf:f30a with SMTP id d9-20020a1709063ec900b0086ffbcff30amr14033408ejj.58.1677080113790; Wed, 22 Feb 2023 07:35:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677080113; cv=none; d=google.com; s=arc-20160816; b=KhlGbAke73CicQAqLqirP8VNbLZv7N7RaXFmFoKJ9NxLUIlDSVuOB45rwUw3DGrqqd 5xfG5xeQwQyJ5EzLF2U6PJ80MQsx0POIlecyILbnMTopp3bnocKE4TlJeRNQAKl2yCRB XfrgT6jrMPOpeq64/Ub2We4NNZIk3fqaGTaes6AXDEmLCUjIAZu4+q6HiBEmr+XOiZuZ A99iEDuy/n4PR3TLzaMMhLtTFO/gWsLMF9ERPIUtI2qILfeAoYUvmwucjLZ3RL6Ls3eA vWyRIAq7oHdcwh2euMGemGHfdrcWSNVgbUo9GmugNLwwPBQB8H6ytr2hVSdHHfjEg+eU l3IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PaLsYMr6sPMtYqx6/6slHF8podsGBf53BiFDK64HXmc=; b=HF4buX98kP9YGrsou8kfnXVMpxlTeEpNI8lrIY8EgU/HTDia9+2ctmfzPlduRr32BW 37n9Tkj9WXu9EICMhefbvCm//Q71gdhQ5epXNeNE9RfGd18Zh8AekvJ1cO/ndykox8Zd kTtnCN0nN0vubjpJ+V2ZQWqEAK0Oo0vJDLKlGVH+kkfJywToYpqcaW31yeJZ/R24uGRn mQIL5tBbkIixWEQaVCV4Uczp0BxqFoveAUVoPpWGu4yiFFGXGA6GqLvbxtiAG37X1EOd 5q0gEQIvG7Tc7AGTo0YwxXVL+HtLP5wsmlxxZPSnXRlYNoQpVDurMerzO7vpLU+A9AyX dGTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JEBZurAR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Fixes: 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller") Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 8d7eb51edcb4..c1800e44f3da 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -164,7 +164,7 @@ examples: #include #include #include - pcie_ep: pcie-ep@40000000 { + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, <0x40000000 0xf1d>, From patchwork Wed Feb 22 15:32:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 60581 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp643711wrd; Wed, 22 Feb 2023 07:35:14 -0800 (PST) X-Google-Smtp-Source: AK7set9jViLwDiiKgiyxwIRMvKX89QKMIRDxeADCUCiWaeEwWX4h5ZrKmWQwRhN/PJWBS436dmIy X-Received: by 2002:a17:906:2446:b0:8af:a53a:189d with SMTP id a6-20020a170906244600b008afa53a189dmr15782609ejb.44.1677080114463; Wed, 22 Feb 2023 07:35:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677080114; cv=none; d=google.com; s=arc-20160816; b=PsXmexSOpSr7qYmSTunSq7HhrWiM2oK/QYyl2nh1hduuW92xVqeK/zg2rWDcJfbVlQ cei7SWkkuQXeTgBJssP3As1h+GOnZSuFu+CIo0+OCzpMiupvP7J4CqQzxrxmnuXo7puC ArUQic8lEG2ZCs7QBgZBCW/e/0RkW/pXY6bojwlTJ65bD4yMpRB+RRC0jR3dYQ1xRf8P M/yJVRmiqYFWJm2bMuARCRNzm6IPk17c0BmfmmruIMmOcbtdgEbYwd9Ytm5e2L1Ye+sm /93hP5iRx+skbZHYvEFsgnBClCXnQVq9AdLjXDmWy2gL5npqUpjupGPQIBLAUClvW6Zx H5Kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=A4e6XJvimzjayIq2V7Cw6k05l1eYQZOtV1NQM7gOwgU=; b=b6YRVduZGfisxSV1DtDSVWJqEaHrTP9oD6/KCZmMDps0Avnsl0ZexoDce76huymb71 pv8RblXFajmZSwFKkDRKdt8ZhK6mgYBtAL6X2a2Iym7K4Ezb2k29rzx50lSyMuPPpj4v hM8JDFZQQU+J8B2vkqKU3hFJklZRPhXLmnCwFPQ1FHz3V7vxMxtu3IZK2tgvVoW5eBsj 4Izd3UhI0VuShJR/X4m7s5g4Jv6kwoNOXlVoK9wXe6UpZXYrzo+YRAYlTV02ZPjCGPSu cnbpfguHhG3BAyMzQoQtst+2YmtC1jxwJn/k7B6fPUD25AWXtw46NH9Y+hl9DH8eHqPA ilZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hc/0ExDq"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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This also requires sorting the node in the ascending order. Fixes: 31c9ef002580 ("dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx55.dtsi | 78 +++++++++++++++---------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 93d71aff3fab..e84ca795cae6 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -303,6 +303,45 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; @@ -400,45 +439,6 @@ sdhc_1: mmc@8804000 { status = "disabled"; }; - pcie_ep: pcie-ep@40000000 { - compatible = "qcom,sdx55-pcie-ep"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, - <0x40200000 0x100000>, - <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio"; - - qcom,perst-regs = <&tcsr 0xb258 0xb270>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; - - interrupts = , - ; - interrupt-names = "global", "doorbell"; - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; - phy-names = "pciephy"; - max-link-speed = <3>; - num-lanes = <2>; - - status = "disabled"; - }; - remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; From patchwork Wed Feb 22 15:32:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 60583 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp643937wrd; Wed, 22 Feb 2023 07:35:42 -0800 (PST) X-Google-Smtp-Source: AK7set+Zt0rr8BQboZI/c8zwICVAWuq5GNlOW+MpsRezYyiT5ZfaZXx/lFwE+5EXcaQw8QpLgH3Q X-Received: by 2002:a17:906:3e43:b0:88a:2e57:9813 with SMTP id t3-20020a1709063e4300b0088a2e579813mr17067404eji.33.1677080141923; Wed, 22 Feb 2023 07:35:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677080141; cv=none; d=google.com; s=arc-20160816; b=ZqU7z71ECl/JdsdeWlD7XBm2EuwIkzgsFd0jhEYThyyP/tfOy2RiauTeIUKUPlRi/3 o9qt+qMGAT85iqcJ8FrvyBfpIGzoH+993ZY6GgRk3GuOjd8WSfqXEzfoVPOqrzGV7sSj VlwxdfGhD/T6Wt5z1A5yXrLoBd6arTb7xZg6lVhmc+UIh859CWvEODlraR6sZX8vZaFD vvvBb7UFwF/ZhGrZlmZLkpI93tQaM3jeEdf0odYjl+K/a1ugD1IQc56KsV9jWl9X6Kqv WWsypnj1/DfAX5vbhZZ5THb2iSAEAmP+KYEEZ0xYhCqT4CCg61J7iiSyrJp64VXHEkyV wRbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vMflvsnFsn2zSdUZQv5yrtakTBmlDgkLH0Li1CsV2To=; b=V2Ux2ecPvjkNdIEOgcK9UyD82e5Zo7Z46rCDtq3Po4XS9cA1DPQ4babqbHTWV0xCNI Qsl/MOzJDGlm3zi+iIZ6UyfZHwSRxUhAOAYXmYB08vIt9BkWR0oFHLCG60RsYYreTy7k PtHhw9sS5NHnZsDIB52JL4wkwbIPVpC7cLdm/NUDh8ClXAZ+p/Jmv+nDcENinYL8WWZ5 kJJcmhSBh5CVNdCBsbz5HxoXIiS+llB0x0OtKk/ahrB0u7alkagvor5oQaHk8swhhQzp PwE6DFi+0IhPNK7uxwGEhtmm1YZJt9LDJIVafTh/b4Icxo1go5Xq6XhfTkhnjjjByFNI 2SiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YZJTTFPH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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This also matches the naming convention of the PCIe controller. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 2 +- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index ac8b4626ae9a..b7ee0237608f 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -242,7 +242,7 @@ &ipa { memory-region = <&ipa_fw_mem>; }; -&pcie0_phy { +&pcie_phy { status = "okay"; vdda-phy-supply = <&vreg_l1e_bb_1p2>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index e84ca795cae6..a1f4a7b0904a 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -334,7 +334,7 @@ pcie_ep: pcie-ep@1c00000 { resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie_lane>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; @@ -342,7 +342,7 @@ pcie_ep: pcie-ep@1c00000 { status = "disabled"; }; - pcie0_phy: phy@1c07000 { + pcie_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; #address-cells = <1>; @@ -362,7 +362,7 @@ pcie0_phy: phy@1c07000 { status = "disabled"; - pcie0_lane: lanes@1c06000 { + pcie_lane: lanes@1c06000 { reg = <0x01c06000 0x104>, /* tx0 */ <0x01c06200 0x328>, /* rx0 */ <0x01c07200 0x1e8>, /* pcs */ From patchwork Wed Feb 22 15:32:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 60586 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp644443wrd; Wed, 22 Feb 2023 07:36:41 -0800 (PST) X-Google-Smtp-Source: AK7set/QH4EopkojWui+i50wcPM6SdW6lQ3o5iApQ85DRz6/kD6wb6Gq3w9DiEEgqa6TNROOGjvL X-Received: by 2002:a17:906:796:b0:8af:514f:1078 with SMTP id l22-20020a170906079600b008af514f1078mr14838819ejc.31.1677080200785; Wed, 22 Feb 2023 07:36:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677080200; cv=none; d=google.com; s=arc-20160816; b=UJdq5Y90H6iMmSHKQXRHrradwueVcvMtuNheK9E69AsHSwytlq2AgM38CvDpCv89j+ tTzFmHnDJaIifAPIlb+rGWNNMsmXcbU2Hxq4JbyQmj2j93Q3ldqucZ9zwfWO3/PYzbYa Y4ZOQLSEq1827Alefp5nArLjt1/djB1VaSAdexUW1BZRNANhLujPU3JIMnl0BpN9xoFK RYE0X+tf4uDQWL2o4Xi6WRQDoSv8Da9tR5yvTrvnGMsgf9fUoq3TC+URaoh/py1Xyu5L Kvd97/5/6PiKFKvK8BOQZmDmtdAINK75/K2jNXI3nZ9MYq7gUtoK6x74/1bbKazDKbQJ t10Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=frPAbJX6IbYMGdSO5i2vVIONplrg4szzCvfObYpFa4I=; b=kOXmUYKRvXUHJti52G/qpGbBoI4srVTni2pgH0yfCq6Av+TudrdHh42og0PISOxmkb KG96nLrnLB/gXzXCWBiUhI6rpu9XAXSDsCGjL3bWnYyg+qARAGnTwZ0aiNWpNHnyMldH MXpjuGiBYLJgsGcHB+r+7NgXMLI6c3FMGRYnOEWvg4HmVcx3FwCGRiGoUFVCP7PfHARC ocs9lVQIEdJfJlfot3KtXvtP81NT7qhyqm7Fj1eWkgZb3u9/cXzQHC9wArQwWvRfGw7A dQCi1OuaElitgLWD6FNUmGRotWJXXV/YMrhtCa/dLL88gnnsEtj9Ul6Y4eqnaxMPy9TG EyWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sRUZyKJQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Let's add support for it. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 72 +++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index a1f4a7b0904a..768d7d7f6335 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -303,6 +303,78 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_rc: pcie@1c00000 { + compatible = "qcom,pcie-sdx55"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", "msi2", "msi3", "msi4", + "msi5", "msi6", "msi7", "msi8"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep"; + + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x0200 0x0f>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, From patchwork Wed Feb 22 15:32:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 60584 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp644094wrd; Wed, 22 Feb 2023 07:36:00 -0800 (PST) X-Google-Smtp-Source: AK7set8RAm7vieHdWz0oIrZciWSZq30dbi0l4eEZ7JUxxAexNSOacoXi8b4eN2IXhMWgvGiZpnTc X-Received: by 2002:a05:6402:35d0:b0:4ad:f811:e267 with SMTP id z16-20020a05640235d000b004adf811e267mr9463765edc.12.1677080159874; Wed, 22 Feb 2023 07:35:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677080159; cv=none; d=google.com; s=arc-20160816; b=DnrPpTzyBOi8RBqOSXtXSrIRfbhepQQCWxOD49/ztjvhPJOjSASaJv8mqAns9x0Ldz +nNkYc+do+/96jIB/zGCGOT28zejz5VXeBrxmic+qb6jQew99MBKDB5wwRd2s0efFG2m ByyT1x1xBCAVRSF6nXVQrJufgOicjmOLK9THVCiBTTCEo8APaO/A20f0ld7nY9VDj8Xa QfrRnaAA4cvHmy2WucXEgN76ELm2WR1jOZnb2LR3ZGE6dCvRs3XspCuhVkW4ob1UhS7n zVbEpinvjN89fQ28alLKXYxgKvS3AD0kfN4YRfQLCJzPN9Cv2pKtouk0Wgs88kUcyleP cSLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2+9Sxg1sb41EUH4zAEeTtmCUVlAMIKcvxnijBOORmOY=; b=DRvbCVyMoVHew+A8fhJSzHv1wt/Szx+X7k9vR+CynnvRFe8wIbEZGaEzToLb1orBcd LLRD6sY2tE3cHe2htD0yQHeT6pKIPz1xCVBrBmFkRpoMycYI4B+UYWNzQpkZ5+4Li1Y0 6hqkUQJ0qL3IhxhH5eTK0mUnn3hfdHeEcwy83PLSplbh/HKDu7ErZpm5TxT/zzwEZgoI sSIOYdCDzmV0a1v328kS5Gdwh8J21G8QF7rHvHwfse+MEMlpKk2wY2eZRulpvU1LBPan VnMQ6cTuxo2iZ6ZdvMbYmG/GftgRhNAQ95r2MqME+y/4MUfKPDpIdgpbyGNGbOKym5XY YhCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jlL9hkET; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 7ed8feb99afb..fb5b9264077c 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -242,6 +242,23 @@ &ipa { memory-region = <&ipa_fw_mem>; }; +&pcie_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; +}; + +&pcie_rc { + status = "okay"; + + perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; +}; + &qpic_bam { status = "ok"; }; @@ -265,6 +282,31 @@ &remoteproc_mpss { memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_default: pcie-default-state { + clkreq-pins { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; From patchwork Wed Feb 22 15:32:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 60585 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp644246wrd; Wed, 22 Feb 2023 07:36:17 -0800 (PST) X-Google-Smtp-Source: AK7set8h6D1qofIfOdTAso6OjRBygPOkAhwiYA00YJzTZXcyT+rEpd1uWh+mzwI+laKuzhje7g7z X-Received: by 2002:a17:906:4a12:b0:8a9:e031:c4b7 with SMTP id w18-20020a1709064a1200b008a9e031c4b7mr16971192eju.4.1677080177153; Wed, 22 Feb 2023 07:36:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677080177; cv=none; d=google.com; s=arc-20160816; b=YDJbQuwyadzHiOnsGElrWObxSaBC7CQvqN508RZ5mGf+SSGbCCy0IBcqSatrvWp4BJ 16MIZKOjc0OM0NwZLQR85yIpA73ln9vJPYB8El7tQ73Lb42OkmRI23XfEV/7hWefsMFF mv87Oo+pKyXC4KbyD9UHqOtt0N8uqEHfNRhTPnZBrl/6LU2C5Jl3eLraqEd72lCadkUB dusAdULwwxNmFnaagussqfJcaF1i+oTqaRnONLM0NB/JyMzlGOUpj+7rCLuL+HI+6spg 5jFslEjXtYtJh444lLBYPhyzh4RSW7beBwmYigy7/8CaJfGCtItb7PgGE5QHZcczYmdZ 1O+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UXASpO0hsEy3ilJiBaB6wUQHYL6reFOimLPyPRNZ9VA=; b=Kh6YcAbz2EjcEzCkeUH+NNhin8F0rHKrKgqPdTx1oTUwZo5HTs7ICle7Fhd8MAS71U U/enLELHT9NW4fzj0gzFSHOoGrgYjlgEqnB6OntGOBUa1ZFNnoLEsg4VtAklhdCNxvI1 qEcdc9yYz50bBSJmC8gQOlN+aeFf/3PXwKV1PFAD3NhzOlNWd7fNzndObQyYtsTQIL9Y cboaPOg0eSFZr+eNKmrEmrdkrPOnLGjfeOpx6sN+FoKZzBhqM6pH3+ZYOw643Jeo+Gry ygvBO5vJdtrJIr1/qYEzphxc4IvflrBfKzFprBoUajRFqU1Ph6vaNLMk4E/F+CFfiCtF br+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XTDVVzjz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h6-20020a170906530600b008c740508747si17391220ejo.586.2023.02.22.07.35.53; Wed, 22 Feb 2023 07:36:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XTDVVzjz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232603AbjBVPe3 (ORCPT + 99 others); Wed, 22 Feb 2023 10:34:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232583AbjBVPeW (ORCPT ); Wed, 22 Feb 2023 10:34:22 -0500 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B451438035 for ; Wed, 22 Feb 2023 07:33:50 -0800 (PST) Received: by mail-pf1-x431.google.com with SMTP id b20so5369459pfo.6 for ; Wed, 22 Feb 2023 07:33:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UXASpO0hsEy3ilJiBaB6wUQHYL6reFOimLPyPRNZ9VA=; b=XTDVVzjzYW6OglYKpErlEY5BTxwcoMAJ78jl41dTOOTDf55Kv5cfcE08L8Pc9AISuF /2q0DiiRDIViwFC7mM3YCiGJzfXzSoxUS3YPr3wvU9u/CwGq599m07Y32Rjc7cM8SF/I Kh0nB5eoL2iyG7Ey2oEG7LCwEgM5kvZctcnzF93D97rK5C9193/pK6aSXUPLWm82x91J Lj9HKLF+ZbYjeJAqoa61CzKXJzuFk32CI6OCvuTXlnL2NqiHZ+aE3sPhzfb1a0ry14Tp Ti+qYZs2rNvTnRijVowszUav5QMwx7E3Xr+Synw/G1kpyrqi4PR5jcoetbiNqQ6P9bzb ldlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UXASpO0hsEy3ilJiBaB6wUQHYL6reFOimLPyPRNZ9VA=; b=RzATrNvi72rHZqzobpQjGsgsaum/+pCxmtV3nROpgyfLIbpKPS1KZyl64azMS9pYba d/QQZYI4iNDPoqUUjfQVum6jEnVN9A5tv2CLAxzRng1g2/5LwtUmNw+DQgyGM/HWC6/z isMoHIJZqnjd5SvvcrSJ6GPu1Bx5cv+hdnmDOHlWuanB0/E33FxWhVtpFniMdEQfeeSY Cs0IxXJPSIqAW8BKciLEPxY2WpqhRF+5lF6PVog0upVoDh3hO0l151eoyB4jsY+p6MgZ AeucHHKb+EwOaGjvM6Aaob3zLQlo1Q1RD2Tsfw+JXlUmZi1lTiyXpbmbsTzMg2mi5TQO bpdg== X-Gm-Message-State: AO0yUKVEO92apXzixyNb5tq6BnbmqRE0e3K980UDN7LqdI1gG2zELfzB nQGGkly8trLxF7ZKp7QHSHpI X-Received: by 2002:a62:1b4a:0:b0:5a8:ada1:cc6f with SMTP id b71-20020a621b4a000000b005a8ada1cc6fmr7092178pfb.33.1677080030353; Wed, 22 Feb 2023 07:33:50 -0800 (PST) Received: from localhost.localdomain ([117.216.123.15]) by smtp.gmail.com with ESMTPSA id f15-20020aa78b0f000000b005ac419804d3sm5222482pfd.186.2023.02.22.07.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 07:33:49 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 09/11] phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55 Date: Wed, 22 Feb 2023 21:02:49 +0530 Message-Id: <20230222153251.254492-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230222153251.254492-1-manivannan.sadhasivam@linaro.org> References: <20230222153251.254492-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758546023499962115?= X-GMAIL-MSGID: =?utf-8?q?1758546023499962115?= In preparation for adding RC support, let's split out the EP related init sequence so that the common sequence could be reused by RC as well. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 42 ++++++++++++++++-------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 1b136a87053f..f526f73f76ef 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1122,10 +1122,25 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { }; static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), @@ -1133,8 +1148,6 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), @@ -1146,21 +1159,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), }; static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { @@ -1212,6 +1215,9 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), +}; + +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), }; @@ -2003,6 +2009,14 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), }, + + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { + .serdes = sdx55_qmp_pcie_ep_serdes_tbl, + .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), + .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), + }, + .clk_list = sdm845_pciephy_clk_l, .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, From patchwork Wed Feb 22 15:32:50 2023 Content-Type: text/plain; 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The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 49 ++++++++++++++++++- .../qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h | 2 + 2 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index f526f73f76ef..9d92facd47a6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1138,6 +1138,41 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), }; +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), +}; + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), @@ -1217,6 +1252,11 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), }; +static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +}; + static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), @@ -2010,6 +2050,13 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), }, + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { + .serdes = sdx55_qmp_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), + .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), + }, + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { .serdes = sdx55_qmp_pcie_ep_serdes_tbl, .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), @@ -2025,7 +2072,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = sm8250_pcie_regs_layout, - .pwrdn_ctrl = SW_PWRDN, + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, }; diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h index af273602998e..ac872a9eff9a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h @@ -6,6 +6,8 @@ #ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ #define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_ +#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 From patchwork Wed Feb 22 15:32:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 60587 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp644978wrd; Wed, 22 Feb 2023 07:37:51 -0800 (PST) X-Google-Smtp-Source: AK7set/HPNWKMJnDRRY5UAts4XGT+JJrpRM3Gt7+Y/bYbWAHZSOOdg69udRMh1KEjjRc7j4jbSou X-Received: by 2002:a17:906:c44a:b0:8b1:fc:d737 with SMTP id ck10-20020a170906c44a00b008b100fcd737mr18247648ejb.19.1677080271524; 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The PCIe controller is of version 1.10.0 but it is compatible with the 1.9.0 config. This SoC also requires "sleep" clock which is added as an optional clock in the driver, since it is not required on other SoCs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 77e5dc7b88ad..659df73114dd 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[13]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "sleep"; num_opt_clks = idx - num_clks; res->num_clks = idx; @@ -1824,6 +1825,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, + { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },