From patchwork Tue Feb 21 19:08:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 60224 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp177862wrd; Tue, 21 Feb 2023 11:11:02 -0800 (PST) X-Google-Smtp-Source: AK7set8Ifblv8391yNptbN9SN7+csidAv1040aMmpM7MPcy+lODPCLCnYUGUSoHWVflGxBXg5s1Y X-Received: by 2002:a05:6a20:3d0c:b0:c7:1bac:6ef9 with SMTP id y12-20020a056a203d0c00b000c71bac6ef9mr3768250pzi.46.1677006661692; Tue, 21 Feb 2023 11:11:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677006661; cv=none; d=google.com; s=arc-20160816; b=pCLtQjYKtLK/4eEOW6a4mWD1HbKtw7HBThht/ezdSz9aYyuJzsfonwQpr4ZXY3nIkH q9d9bLpUCFio4dBedJq1OU6+lEUdKxMWKF4QFbsPF1wpJHRv9NcbubHtiuV23qNcink1 6aGL2aB1m2gcmlbSKNx6jq2gXfHG6ZEchov8oA0xooSxQKoF/RrGFZRhkORAlBHi1SzE XxYDCqJnqLIm7sy5uYnKOvgCvWGE0X1k7lu2ulRZ0FDi3g7rtslqTBl5kDzHLvdiBroy Uayw9jBppZxoASCCeGYTKRvKvpjeffeLNfM6gg0LPxyfNY87Ag8x6A9Y+fZTlqAL2ADQ 4i8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5PlwZzP1OOkIe8VY/GWOoEev+10r3VEkS4WO6Gk8l2k=; b=Kc1tEIOK+niG+KERkV+3A2kb5k3gEWnlyIq1dJrrZ1SuXNMhEy0UG0RKPyrm71NseJ CzT00UC7HgkXFKws71AS/kPL0Ix7TOEAVdJNBSJrvje52y6+eT8ZTuCuXdAtmD88I9v8 6nP1dhKBJ3hHDgnuzDj1T5/ppcSx5p8oCAEhEeSuN0KJGhcf9c2uyLQM+lHmiKfpxCSZ 6NCa1yPmu0ws7G41mrJx6QnnUlRtdPpR6f2m6lDi3gbyN0QuV4leMfde+ybo2dQ21dxX bHZ77hmRgzljZCuq+lFLGhtBwe1H3Ammc2UryHyzSLOQyPOWEi09Tnruz/RUr6e1a6Fy MKeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=QQBnZajv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t12-20020a65608c000000b00502d74a68c2si3346411pgu.22.2023.02.21.11.10.49; Tue, 21 Feb 2023 11:11:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=QQBnZajv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229866AbjBUTJb (ORCPT + 99 others); Tue, 21 Feb 2023 14:09:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229507AbjBUTJ2 (ORCPT ); Tue, 21 Feb 2023 14:09:28 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BD5E2D15D for ; Tue, 21 Feb 2023 11:09:22 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id s5so6098039plg.0 for ; Tue, 21 Feb 2023 11:09:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5PlwZzP1OOkIe8VY/GWOoEev+10r3VEkS4WO6Gk8l2k=; b=QQBnZajvWt8L0J2op7Y8kbVD/inXT8jI1jPRtrAaF1l32CC/UmkDKZntxGEkxJT9A6 RXUSdeohaBNYxrUQ0keb/sWyK7iBM1289G/b7aRD5jchfFz3o4/HGm4ySSqAa1DsvEwY IFoMRUFDU+aQ1bFAs+wWir3DnVgSR8eE5W6ixGdGxdQr+vORYiuR7OBS1iAFoNih8X56 tYuBPx3j25tO75A0wH5LzIduopQFOwGLI4EMG+UU7vXPk6D9HoyAqtEgibBGTc90hnLk 7IpYLiiJAU3s9OgqZJQa1VBtSf8nmzaZIld31oJqqb3L3Ph5b6DDIH+rsXj4ab3Uks2r 0hew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5PlwZzP1OOkIe8VY/GWOoEev+10r3VEkS4WO6Gk8l2k=; b=kU4caqs4/XtPlIixKsKg5shViBFLNu2uNM6CIN1pEL5w0kxEi3vdo5xazo5Rgou7wd k9/ynSLDn8UPB5ZGNYxbrN2jeggnnGp1KwFKfnNabkuYICgjzH+21RePXmABUXld/y5G o0v5xD8b/gJv80lMwGPHEN8irUWBGK5vndI2YwUQyH6gbmr+8d0CFBnK6KD7I6odt4wS McX33kGH5EwdEIFWSsCwSc7T2NngpjqT93qLOBiuF/add+eiww9dVLigtkCG7SIudE79 8L2ldbXYlSDhESd44cMONoPVlz15sYXvM5UiyYiWPmBV3FDT6A5A5K9o47ir5alob8o2 DIqw== X-Gm-Message-State: AO0yUKVC15AOPOcJ48gKzF2MhesEu4pVqqW2uaHxSGZI+KfT+5VlI/dl 7KOP4wRhMrxoqhqAiEebB53tnQ== X-Received: by 2002:a17:902:e886:b0:199:15bb:8316 with SMTP id w6-20020a170902e88600b0019915bb8316mr8643038plg.68.1677006561719; Tue, 21 Feb 2023 11:09:21 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id b16-20020a170902b61000b0019602b2c00csm1583863pls.175.2023.02.21.11.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 11:09:21 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: heiko@sntech.de, Conor Dooley , slewis@rivosinc.com, vineetg@rivosinc.com, Evan Green , Conor Dooley , Albert Ou , Anup Patel , Atish Patra , Palmer Dabbelt , Paul Walmsley , Randy Dunlap , Sunil V L , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 1/7] RISC-V: Move struct riscv_cpuinfo to new header Date: Tue, 21 Feb 2023 11:08:52 -0800 Message-Id: <20230221190858.3159617-2-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221190858.3159617-1-evan@rivosinc.com> References: <20230221190858.3159617-1-evan@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758468937394802122?= X-GMAIL-MSGID: =?utf-8?q?1758468937394802122?= In preparation for tracking and exposing microarchitectural details to userspace (like whether or not unaligned accesses are fast), move the riscv_cpuinfo struct out to its own new cpufeatures.h header. It will need to be used by more than just cpu.c. Signed-off-by: Evan Green Reviewed-by: Conor Dooley --- Changes in v3: - Updated copyright date in cpufeature.h - Fixed typo in cpufeature.h comment (Conor) Changes in v2: - Factored the move of struct riscv_cpuinfo to its own header arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++ arch/riscv/kernel/cpu.c | 8 ++------ 2 files changed, 23 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/include/asm/cpufeature.h diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h new file mode 100644 index 000000000000..66ebaae449c8 --- /dev/null +++ b/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2022-2023 Rivos, Inc + */ + +#ifndef _ASM_CPUFEATURE_H +#define _ASM_CPUFEATURE_H + +/* + * These are probed via a device_initcall(), via either the SBI or directly + * from the corresponding CSRs. + */ +struct riscv_cpuinfo { + unsigned long mvendorid; + unsigned long marchid; + unsigned long mimpid; +}; + +DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); + +#endif diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..684e5419d37d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -70,12 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) return -1; } -struct riscv_cpuinfo { - unsigned long mvendorid; - unsigned long marchid; - unsigned long mimpid; -}; -static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); unsigned long riscv_cached_mvendorid(unsigned int cpu_id) { From patchwork Tue Feb 21 19:08:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 60225 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp178011wrd; Tue, 21 Feb 2023 11:11:22 -0800 (PST) X-Google-Smtp-Source: AK7set+KqTXhZJR/Jc+h1Zei1NoBdRTUy4AI4GMh23N95ppwFr/ULUMMrfAmnow+cKAPAtXaP5bw X-Received: by 2002:a05:6a20:1609:b0:bf:8840:ffd0 with SMTP id l9-20020a056a20160900b000bf8840ffd0mr16302965pzj.29.1677006681967; Tue, 21 Feb 2023 11:11:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677006681; cv=none; d=google.com; s=arc-20160816; b=y8bRbff+D/Ft3wJw5GkbQLT6ddBA3OF8KZcCj54CS1MLN7v/q+xxKk/C9td7oK1jGW 1SM+T0O1ffJ3jtoFMnHiyynV5qS2Lgw3Tt4yhCrctwVR8UHGQxdF7Yl6nyOR1+kFN9hm 9JqJ5a3bCskP/TpHifji8Rmi66bg2l6eMnuxnlW6R6J+KAIy2cgLRNy66OWcdNoqSqfw uj83xWh4yzQPPkM6imOxZii6ZsRzu4lun4O+cmDh/QPpL1XwrY9GvHCy/5/I6CNaPwEu AFiumtb43i3QbqGDax/V7EOoXKnjWcm4va5PwXhjL7HDYgGminvq7t4kdODramovjyGn 1o9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1d1h6gvf1z05DXGK1jMMZmsuuxnjdONUzCq/fBHE8HU=; b=PCq7/s9dLO8zxvoQ2JI9w/+AAe4qNEQXzmCSENJx/7ZOgkM/Yojc4h2bGWmBUVQTeY 7Nyg7Aba8VQDVzORi9k0RF/y5ALUkXLnylY65fo/HJCCIK8oakaycHgLO1w8XdapgAJt EnKUoMZ3vYkKPam0R7huXgauJLxBQSWSQ/chKYfCwv/XhQrEme809vj4VhOQMOmHPEPU 7kLM30dieGML2JS0zudGRJjMbEH/VA5+rdbVZPY13B3WHib3EzGbgON2tHUZXn64Vm32 rGYfp3suFmmAixmZn4zUnxsPwQA/TLTvlhlgyGfxdD3y1uuQ4yQn7OJcjDqwcexR7uLK G47Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=NQWHRkJK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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This currently just provides m{arch,imp,vendor}id, but with the key-value pairs we can pass more in the future. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green Reviewed-by: Conor Dooley --- Changes in v3: - Refactored functions so that kernel mode can query too, in preparation for the vDSO data population. - Changed the vendor/arch/imp IDs to return a value of -1 on mismatch rather than failing the whole call. - Const cpumask pointer in hwprobe_mid() - Embellished documentation WRT cpu_set and the returned values. - Renamed hwprobe_mid() to hwprobe_arch_id() (Conor) - Fixed machine ID doc warnings, changed elements to c:macro:. - Completed dangling unistd.h comment (Conor) - Fixed line breaks and minor logic optimization (Conor). - Use riscv_cached_mxxxid() (Conor) Changes in v2: - Changed the interface to look more like poll(). Rather than supplying key_offset and getting back an array of values with numerically contiguous keys, have the user pre-fill the key members of the array, and the kernel will fill in the corresponding values. For any key it doesn't recognize, it will set the key of that element to -1. This allows usermode to quickly ask for exactly the elements it cares about, and not get bogged down in a back and forth about newer keys that older kernels might not recognize. In other words, the kernel can communicate that it doesn't recognize some of the keys while still providing the data for the keys it does know. - Added a shortcut to the cpuset parameters that if a size of 0 and NULL is provided for the CPU set, the kernel will use a cpu mask of all online CPUs. This is convenient because I suspect most callers will only want to act on a feature if it's supported on all CPUs, and it's a headache to dynamically allocate an array of all 1s, not to mention a waste to have the kernel loop over all of the offline bits. --- Documentation/riscv/hwprobe.rst | 39 ++++++++ Documentation/riscv/index.rst | 1 + arch/riscv/include/asm/hwprobe.h | 13 +++ arch/riscv/include/asm/syscall.h | 3 + arch/riscv/include/uapi/asm/hwprobe.h | 25 +++++ arch/riscv/include/uapi/asm/unistd.h | 9 ++ arch/riscv/kernel/cpu.c | 3 +- arch/riscv/kernel/sys_riscv.c | 134 +++++++++++++++++++++++++- 8 files changed, 225 insertions(+), 2 deletions(-) create mode 100644 Documentation/riscv/hwprobe.rst create mode 100644 arch/riscv/include/asm/hwprobe.h create mode 100644 arch/riscv/include/uapi/asm/hwprobe.h diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst new file mode 100644 index 000000000000..88b015a2026e --- /dev/null +++ b/Documentation/riscv/hwprobe.rst @@ -0,0 +1,39 @@ +.. SPDX-License-Identifier: GPL-2.0 + +RISC-V Hardware Probing Interface +--------------------------------- + +The RISC-V hardware probing interface is based around a single syscall, which +is defined in :: + + struct riscv_hwprobe { + __s64 key; + __u64 value; + }; + + long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, + size_t cpu_count, cpu_set_t *cpus, + unsigned long flags); + +The arguments are split into three groups: an array of key-value pairs, a CPU +set, and some flags. The key-value pairs are supplied with a count. Userspace +must prepopulate the key field for each element, and the kernel will fill in the +value if the key is recognized. If a key is unknown to the kernel, its key field +will be cleared to -1, and its value set to 0. The CPU set is defined by +CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will +be only be valid if all CPUs in the given set have the same value. Otherwise -1 +will be returned. For boolean-like keys, the value returned will be a logical +AND of the values for the specified CPUs. Usermode can supply NULL for cpus and +0 for cpu_count as a shortcut for all online CPUs. There are currently no flags, +this value must be zero for future compatibility. + +On success 0 is returned, on failure a negative error code is returned. + +The following keys are defined: + +* :c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Contains the value of ``mvendorid``, + as defined by the RISC-V privileged architecture specification. +* :c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contains the value of ``marchid``, as + defined by the RISC-V privileged architecture specification. +* :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as + defined by the RISC-V privileged architecture specification. diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index 2e5b18fbb145..175a91db0200 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -7,6 +7,7 @@ RISC-V architecture boot-image-header vm-layout + hwprobe patch-acceptance uabi diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h new file mode 100644 index 000000000000..08d1c3bdd78a --- /dev/null +++ b/arch/riscv/include/asm/hwprobe.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright 2022 Rivos, Inc + */ + +#ifndef _ASM_HWPROBE_H +#define _ASM_HWPROBE_H + +#include + +#define RISCV_HWPROBE_MAX_KEY 2 + +#endif diff --git a/arch/riscv/include/asm/syscall.h b/arch/riscv/include/asm/syscall.h index 384a63b86420..78a6302ef711 100644 --- a/arch/riscv/include/asm/syscall.h +++ b/arch/riscv/include/asm/syscall.h @@ -75,4 +75,7 @@ static inline int syscall_get_arch(struct task_struct *task) } asmlinkage long sys_riscv_flush_icache(uintptr_t, uintptr_t, uintptr_t); + +asmlinkage long sys_riscv_hwprobe(uintptr_t, uintptr_t, uintptr_t, uintptr_t, + uintptr_t, uintptr_t); #endif /* _ASM_RISCV_SYSCALL_H */ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h new file mode 100644 index 000000000000..591802047460 --- /dev/null +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright 2022 Rivos, Inc + */ + +#ifndef _UAPI_ASM_HWPROBE_H +#define _UAPI_ASM_HWPROBE_H + +#include + +/* + * Interface for probing hardware capabilities from userspace, see + * Documentation/riscv/hwprobe.rst for more information. + */ +struct riscv_hwprobe { + __s64 key; + __u64 value; +}; + +#define RISCV_HWPROBE_KEY_MVENDORID 0 +#define RISCV_HWPROBE_KEY_MARCHID 1 +#define RISCV_HWPROBE_KEY_MIMPID 2 +/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ + +#endif diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi/asm/unistd.h index 73d7cdd2ec49..950ab3fd4409 100644 --- a/arch/riscv/include/uapi/asm/unistd.h +++ b/arch/riscv/include/uapi/asm/unistd.h @@ -43,3 +43,12 @@ #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) #endif __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) + +/* + * Allows userspace to query the kernel for CPU architecture and + * microarchitecture details across a given set of CPUs. + */ +#ifndef __NR_riscv_hwprobe +#define __NR_riscv_hwprobe (__NR_arch_specific_syscall + 14) +#endif +__SYSCALL(__NR_riscv_hwprobe, sys_riscv_hwprobe) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 684e5419d37d..d0fb3567cc3d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -4,15 +4,16 @@ */ #include +#include #include #include #include #include #include #include +#include #include #include -#include /* * Returns the hart ID of the given device tree node, or -ENODEV if the node diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5d3f2fbeb33c..02c2f1f7417e 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -6,8 +6,11 @@ */ #include -#include #include +#include +#include +#include +#include #include static long riscv_sys_mmap(unsigned long addr, unsigned long len, @@ -69,3 +72,132 @@ SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, return 0; } + +/* + * The hwprobe interface, for allowing userspace to probe to see which features + * are supported by the hardware. See Documentation/riscv/hwprobe.rst for more + * details. + */ +static void hwprobe_arch_id(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + u64 cpu, id = -1ULL; + bool first = true; + + for_each_cpu(cpu, cpus) { + u64 cpu_id; + + switch (pair->key) { + case RISCV_HWPROBE_KEY_MVENDORID: + cpu_id = riscv_cached_mvendorid(cpu); + break; + case RISCV_HWPROBE_KEY_MIMPID: + cpu_id = riscv_cached_mimpid(cpu); + break; + case RISCV_HWPROBE_KEY_MARCHID: + cpu_id = riscv_cached_marchid(cpu); + break; + } + + if (first) + id = cpu_id; + + /* + * If there's a mismatch for the given set, return -1 in the + * value. + */ + if (id != cpu_id) { + id = -1ULL; + break; + } + } + + pair->value = id; +} + +static void hwprobe_one_pair(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + switch (pair->key) { + case RISCV_HWPROBE_KEY_MVENDORID: + case RISCV_HWPROBE_KEY_MARCHID: + case RISCV_HWPROBE_KEY_MIMPID: + hwprobe_arch_id(pair, cpus); + break; + + /* + * For forward compatibility, unknown keys don't fail the whole + * call, but get their element key set to -1 and value set to 0 + * indicating they're unrecognized. + */ + default: + pair->key = -1; + pair->value = 0; + break; + } +} + +static +int do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, long pair_count, + long cpu_count, unsigned long __user *cpus_user, + unsigned long flags) +{ + size_t out; + int ret; + cpumask_t cpus; + + /* Check the reserved flags. */ + if (flags != 0) + return -EINVAL; + + /* + * The interface supports taking in a CPU mask, and returns values that + * are consistent across that mask. Allow userspace to specify NULL and + * 0 as a shortcut to all online CPUs. + */ + cpumask_clear(&cpus); + if (!cpu_count && !cpus_user) { + cpumask_copy(&cpus, cpu_online_mask); + } else { + if (cpu_count > cpumask_size()) + cpu_count = cpumask_size(); + + ret = copy_from_user(&cpus, cpus_user, cpu_count); + if (!ret) + return -EFAULT; + + /* + * Userspace must provide at least one online CPU, without that + * there's no way to define what is supported. + */ + cpumask_and(&cpus, &cpus, cpu_online_mask); + if (cpumask_empty(&cpus)) + return -EINVAL; + } + + for (out = 0; out < pair_count; out++, pairs++) { + struct riscv_hwprobe pair; + + if (get_user(pair.key, &pairs->key)) + return -EFAULT; + + pair.value = 0; + hwprobe_one_pair(&pair, &cpus); + ret = put_user(pair.key, &pairs->key); + if (ret == 0) + ret = put_user(pair.value, &pairs->value); + + if (ret) + return -EFAULT; + } + + return 0; + +} + +SYSCALL_DEFINE5(riscv_hwprobe, uintptr_t, pairs, uintptr_t, pair_count, + uintptr_t, cpu_count, uintptr_t, cpus, uintptr_t, flags) +{ + return do_riscv_hwprobe((void __user *)pairs, pair_count, cpu_count, + (void __user *)cpus, flags); +} From patchwork Tue Feb 21 19:08:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 60226 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp178026wrd; Tue, 21 Feb 2023 11:11:24 -0800 (PST) X-Google-Smtp-Source: AK7set9EPb5WWdiGYgQvo3w7N63fXRwdbnjd6xv94XQU6KGoOuZVf0oqczrUxFGbmyY12erBV/eX X-Received: by 2002:a17:903:22c8:b0:192:4f85:b91d with SMTP id y8-20020a17090322c800b001924f85b91dmr6773771plg.46.1677006683705; Tue, 21 Feb 2023 11:11:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677006683; cv=none; d=google.com; s=arc-20160816; b=srFryJsQ9YZJSn44FrLAJ6WeOs6aFO9C3iH/IcOwDUENqOTnsOkbDkYdZpY63zMEvQ F1LS//n18iscIVKAIDugtTM8yYx8BK/OXqLEEIvgbb/dGOB/K+YLp9UdohoPv9ZWQGv5 pLcgDuE+LIY+rEV0ASnvtCaVK0Ih9iCbFhqNxN5FaneKQSn4uU+DKSSza4WeiUYg3hE4 96qA9Swh6cAqVPsTpHHqrJZqJbOeWiernzzWLYQH+fxbwHtiyiALvMQu4JExBSn7AWRG VAAEcbyrZSqwhADpyEug0sf9M3ZbgnCqwWwKN79AA6h5iAmRjKu7+Cg2/4NEcNUS8P0N geYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=U7/hoqMIAepRETH3jO107eIeJ+UfvD3eJMNfG127+yc=; b=B1GPlESVrGWrEaO6TmW9WC83baTyRfl3PZUzNxpATNNs7H2+ePBAuIbS2k4pW1N1nQ WNaM3oA1t6bHScytrHMseQeKvVBLfuQ/G0AvIZy0/4O4pu6tjTO48/e3YqenaNHum78h f70caSU7I3GaGnmrtYV4Db3onZx3DxElIMxI+I2J5g3nUPPvuWoxz5GPzq+qo39lznrH X2QUcVqrGXu9FYRsUn/40cvMDggzAGRhJsd6gnnmlsWJahBzT1bLkiX6skuDw5go3W9k QDvF8fNu6CYfBFw762bzVzICLcerCh/O/a05ZFj43deFZ+7PsqdwG3n2vlJ9nuhj7H4Q 0j+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b="ML/TqptG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green Reviewed-by: Conor Dooley --- Changes in v3: - Refactored base ISA behavior probe to allow kernel probing as well, in prep for vDSO data initialization. - Fixed doc warnings in IMA text list, use :c:macro:. Documentation/riscv/hwprobe.rst | 21 +++++++++++++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_riscv.c | 20 ++++++++++++++++++++ 4 files changed, 47 insertions(+), 1 deletion(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 88b015a2026e..9f2da414fbf8 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -37,3 +37,24 @@ The following keys are defined: defined by the RISC-V privileged architecture specification. * :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as defined by the RISC-V privileged architecture specification. +* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base + user-visible behavior that this kernel supports. The following base user ABIs + are defined: + + * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or + rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the + privileged ISA, with the following known exceptions (more exceptions may be + added, but only if it can be demonstrated that the user ABI is not broken): + + * The :fence.i: instruction cannot be directly executed by userspace + programs (it may still be executed in userspace via a + kernel-controlled mechanism such as the vDSO). +* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions + that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: + base system behavior. + + * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as + defined by commit cd20cee ("FMIN/FMAX now implement + minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined + by version 2.2 of the RISC-V ISA manual. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 08d1c3bdd78a..7e52f1e1fe10 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include -#define RISCV_HWPROBE_MAX_KEY 2 +#define RISCV_HWPROBE_MAX_KEY 4 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 591802047460..fc5665411782 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -20,6 +20,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MVENDORID 0 #define RISCV_HWPROBE_KEY_MARCHID 1 #define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 02c2f1f7417e..f2b224550923 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -124,6 +125,25 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, case RISCV_HWPROBE_KEY_MIMPID: hwprobe_arch_id(pair, cpus); break; + /* + * The kernel already assumes that the base single-letter ISA + * extensions are supported on all harts, and only supports the + * IMA base, so just cheat a bit here and tell that to + * userspace. + */ + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA; + break; + + case RISCV_HWPROBE_KEY_IMA_EXT_0: + pair->value = 0; + if (has_fpu()) + pair->value |= RISCV_HWPROBE_IMA_FD; + + if (elf_hwcap & RISCV_ISA_EXT_c) + pair->value |= RISCV_HWPROBE_IMA_C; + + break; /* * For forward compatibility, unknown keys don't fail the whole From patchwork Tue Feb 21 19:08:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 60231 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp178211wrd; Tue, 21 Feb 2023 11:11:51 -0800 (PST) X-Google-Smtp-Source: AK7set8n2xwfcwsQ3N1ZP2qrlXA1TlNT7x3ebb79kQnUQokVroJ6QEo2rKnL1EF6XduX8FkwLnNU X-Received: by 2002:a05:6a20:3d94:b0:c7:6f26:ca2 with SMTP id s20-20020a056a203d9400b000c76f260ca2mr20516723pzi.58.1677006710828; Tue, 21 Feb 2023 11:11:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677006710; cv=none; d=google.com; s=arc-20160816; b=hMoGrBwYayRMU9q6TmK6YxI2u9fBIGu9DuoY6kgVlHKDCJzgMYI+3hN2HO77ITv68G Z/2zKSDDmtUkJ7grzy7JCveFlKWx6p5Le5udoYj+osYzzj3yHQIZlnlp7TOnQE9vvi0A FOIqqSJQpmGu/yUR2ncrTDZFe+D9iOwGpXxG/sgm3C3nx+ICNDuuSjTwUEKoXTEb6UrG yGfjU0KJFhVqQDKTaYgWjsgyyCShDhirqz2i0t5pVLCwh/88NstgvWTaGS1LpeOy3kOa ywrupp/RPSKR3CoLlTTGyMmzdfL+dqgEL0hD6ldx8SodMnRMHYK3uq3nzaYOeR1uBKze y7Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=h4Uz8oInxrBVxdaNnCcRWzHNxIOpRGtwNCns0Csq24o=; b=XoPc5xCnvmSVHPSy+2RWySeFulmMX4WUflFvdUuj64Taww8FsHJdL05dJxvgDQsW4f hvf2xZ4ujtFPUofldzx8R9oB+7TKGaq42BUlbrgy8+qfyy436OaMnzW0fXOVwFcR67ah sTyWiuGr8YH/EmTsPXCTjIyh4aTKtswoombQ0HfZYpegP7ITyDjubjMsBfnXc+is5ZKQ G0d7JHkoMSOR2icsITiKLBNz/oFFZYOt1yP1c1if6IbbgeoSiBx6V42IMIzAIgkyXDxB vsEeklMRiPjehqyPivHCLL563vOmgOsLovOMw/qfdSVGvpmxEECEOIV0NQO2WndSfRug M8YA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=5CAoJgBa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- Changes in v3: - Added | to description: to make dt-checker happy. Documentation/devicetree/bindings/riscv/cpus.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765..f79e9e5c5ee9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -85,6 +85,21 @@ properties: $ref: "/schemas/types.yaml#/definitions/string" pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + riscv,misaligned-access-performance: + description: | + Identifies the performance of misaligned memory accesses to main memory + regions. There are three flavors of unaligned access performance: "emulated" + means that misaligned accesses are emulated via software and thus + extremely slow, "slow" means that misaligned accesses are supported by + hardware but still slower that aligned accesses sequences, and "fast" + means that misaligned accesses are as fast or faster than the + cooresponding aligned accesses sequences. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - emulated + - slow + - fast + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false From patchwork Tue Feb 21 19:08:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 60234 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp178940wrd; Tue, 21 Feb 2023 11:13:34 -0800 (PST) X-Google-Smtp-Source: AK7set8L8ebS/JQOjsxXcUHyHvf43+JckujhYJ1C5W+euhUyzlgXbLcygHfFDbDS429BeMKV34r9 X-Received: by 2002:a17:906:9f1d:b0:8e4:dd4d:7b07 with SMTP id fy29-20020a1709069f1d00b008e4dd4d7b07mr857774ejc.15.1677006814151; Tue, 21 Feb 2023 11:13:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677006814; cv=none; d=google.com; s=arc-20160816; b=ETJ/wJzPGZEvQD9Dv8CG1myPMItaNLbBHKb6wfOc7MuOCkJpF7J3vqbVK46+hZMC2e lVy9I22npJ3x5zVPuwAuzSq/7V2ADEfMvkMG041eBFU3B0GEPlPqn0lA4YxF8/rCh/tR 5blTm7k2fIOgYw3sIZrsmGANGaFwq9z26GxMd/O9SBKRLntpGzyNXg+vX6cQuXQsUnZg XfUg4K77v6JnfQvP5RfQ4inVlMxZS1KZhXAIOg04A7qcgvASJ4AEFoVEt7dyd1kPg7aF HcL//JXnHLFusQVZ8v2kzGEBG3PWuTnDlgnvQuJ6wEd8IBk6RzrRttYi50b1O2MxaVSw uw1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ngg8NDFZzsFlILqqXwu8UXpBsOAV4Baprs2BRNqdLJ0=; b=J8oqZdrnUuNunQI473176aGkfrqrghipfKVKhz2HM88Z6n3LGzZ9h6HnreACdtTJrD uvo/gC1cLoeNZzRvjTxwW/PZmZqrMUejYCrCRfiO5oXuj+70BOekrQSrWesjyZOmGrh+ /QXjJ7qHjg5Q7Eyk1NHPDavrGqa6RchfGqH7jLNYNi1cU9H6yptV1wzK6aRoAj3ve29z txsOTTzgoB4B2oPHcSR2jXbT/8eFbIjeWxWgoXkFQpOCRejP86kzgbxQ36WTgMWsEZ+8 hYL8WP9Obh+Mc3scQtEhmypZVohHKot4mXaQr3aaiidr8BG2x95eVoVEaLP6ntLfOevq c08g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=FRaQAuEc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- Changes in v3: - Have hwprobe_misaligned return int instead of long. - Constify cpumask pointer in hwprobe_misaligned() - Fix warnings in _PERF_O list documentation, use :c:macro:. - Move include cpufeature.h to misaligned patch. - Fix documentation mismatch for RISCV_HWPROBE_KEY_CPUPERF_0 (Conor) - Use for_each_possible_cpu() instead of NR_CPUS (Conor) - Break early in misaligned access iteration (Conor) - Increase MISALIGNED_MASK from 2 bits to 3 for possible UNSUPPORTED future value (Conor) Changes in v2: - Fixed logic error in if(of_property_read_string...) that caused crash - Include cpufeature.h in cpufeature.h to avoid undeclared variable warning. - Added a _MASK define - Fix random checkpatch complaints Documentation/riscv/hwprobe.rst | 14 ++++++++++++ arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/asm/smp.h | 11 ++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 6 ++++++ arch/riscv/kernel/cpufeature.c | 31 +++++++++++++++++++++++++-- arch/riscv/kernel/sys_riscv.c | 27 +++++++++++++++++++++++ 7 files changed, 90 insertions(+), 3 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 9f2da414fbf8..ac6ded9eb0da 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -58,3 +58,17 @@ The following keys are defined: minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. +* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance + information about the selected set of processors. + + * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned + accesses is unknown. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are + emulated via software, either in or below the kernel. These accesses are + always extremely slow. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are supported + in hardware, but are slower than the cooresponding aligned accesses + sequences. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are supported + in hardware and are faster than the cooresponding aligned accesses + sequences. diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 66ebaae449c8..808d5403f2ac 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -18,4 +18,6 @@ struct riscv_cpuinfo { DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +DECLARE_PER_CPU(long, misaligned_access_speed); + #endif diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 7e52f1e1fe10..4e45e33015bc 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include -#define RISCV_HWPROBE_MAX_KEY 4 +#define RISCV_HWPROBE_MAX_KEY 5 #endif diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 3831b638ecab..4f77a64194e5 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -26,6 +26,17 @@ struct riscv_ipi_ops { */ extern unsigned long __cpuid_to_hartid_map[NR_CPUS]; #define cpuid_to_hartid_map(cpu) __cpuid_to_hartid_map[cpu] +static inline long hartid_to_cpuid_map(unsigned long hartid) +{ + long i; + + for_each_possible_cpu(i) { + if (cpuid_to_hartid_map(i) == hartid) + return i; + } + + return -1; +} /* print IPI stats */ void show_ipi_stats(struct seq_file *p, int prec); diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index fc5665411782..93fde30fc4a8 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,6 +25,12 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_KEY_CPUPERF_0 5 +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) +#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) +#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) +#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) +#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 93e45560af30..12af6f7a2f53 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -14,8 +14,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -32,6 +34,9 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); EXPORT_SYMBOL(riscv_isa_ext_keys); +/* Performance information */ +DEFINE_PER_CPU(long, misaligned_access_speed); + /** * riscv_isa_extension_base() - Get base extension word * @@ -89,11 +94,11 @@ static bool riscv_isa_extension_check(int id) void __init riscv_fill_hwcap(void) { struct device_node *node; - const char *isa; + const char *isa, *misaligned; char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; - unsigned long hartid; + unsigned long hartid, cpu; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -246,6 +251,28 @@ void __init riscv_fill_hwcap(void) bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + + /* + * Check for the performance of misaligned accesses. + */ + cpu = hartid_to_cpuid_map(hartid); + if (cpu < 0) + continue; + + if (!of_property_read_string(node, "riscv,misaligned-access-performance", + &misaligned)) { + if (strcmp(misaligned, "emulated") == 0) + per_cpu(misaligned_access_speed, cpu) = + RISCV_HWPROBE_MISALIGNED_EMULATED; + + if (strcmp(misaligned, "slow") == 0) + per_cpu(misaligned_access_speed, cpu) = + RISCV_HWPROBE_MISALIGNED_SLOW; + + if (strcmp(misaligned, "fast") == 0) + per_cpu(misaligned_access_speed, cpu) = + RISCV_HWPROBE_MISALIGNED_FAST; + } } /* We don't support systems with F but without D, so mask those out diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index f2b224550923..afc1b96d5c1a 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -116,6 +117,28 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, pair->value = id; } +static int hwprobe_misaligned(const struct cpumask *cpus) +{ + int cpu, perf = -1; + + for_each_cpu(cpu, cpus) { + int this_perf = per_cpu(misaligned_access_speed, cpu); + + if (perf == -1) + perf = this_perf; + + if (perf != this_perf) { + perf = RISCV_HWPROBE_MISALIGNED_UNKNOWN; + break; + } + } + + if (perf == -1) + return RISCV_HWPROBE_MISALIGNED_UNKNOWN; + + return perf; +} + static void hwprobe_one_pair(struct riscv_hwprobe *pair, const struct cpumask *cpus) { @@ -145,6 +168,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, break; + case RISCV_HWPROBE_KEY_CPUPERF_0: + pair->value = hwprobe_misaligned(cpus); + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 From patchwork Tue Feb 21 19:08:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 60233 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp178805wrd; Tue, 21 Feb 2023 11:13:14 -0800 (PST) X-Google-Smtp-Source: AK7set/R6gB4Nyo0urHJk5qI08jZ/OpbKlKVlbiM6kq5RzwmhuELD2ATXpwvFtr1wckkGhXQGcfW X-Received: by 2002:a17:906:53c7:b0:885:fee4:69ee with SMTP id p7-20020a17090653c700b00885fee469eemr12142462ejo.59.1677006794377; Tue, 21 Feb 2023 11:13:14 -0800 (PST) ARC-Seal: i=1; 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It happens to be the first selftest we have for RISC-V, so I've added some infrastructure for those as well. The build stuff looks pretty straight-forward, but there's also a tiny C library to avoid coupling this to any userspace implementation. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- (no changes since v2) Changes in v2: - Updated the selftests to the new API and added some more. - Fixed indentation, comments in .S, and general checkpatch complaints. --- tools/testing/selftests/Makefile | 1 + tools/testing/selftests/riscv/Makefile | 58 ++++++++++++ .../testing/selftests/riscv/hwprobe/Makefile | 10 +++ .../testing/selftests/riscv/hwprobe/hwprobe.c | 89 +++++++++++++++++++ .../selftests/riscv/hwprobe/sys_hwprobe.S | 12 +++ 5 files changed, 170 insertions(+) create mode 100644 tools/testing/selftests/riscv/Makefile create mode 100644 tools/testing/selftests/riscv/hwprobe/Makefile create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.c create mode 100644 tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile index 41b649452560..a599ef726310 100644 --- a/tools/testing/selftests/Makefile +++ b/tools/testing/selftests/Makefile @@ -62,6 +62,7 @@ TARGETS += pstore TARGETS += ptrace TARGETS += openat2 TARGETS += resctrl +TARGETS += riscv TARGETS += rlimits TARGETS += rseq TARGETS += rtc diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftests/riscv/Makefile new file mode 100644 index 000000000000..32a72902d045 --- /dev/null +++ b/tools/testing/selftests/riscv/Makefile @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +# Originally tools/testing/arm64/Makefile + +# When ARCH not overridden for crosscompiling, lookup machine +ARCH ?= $(shell uname -m 2>/dev/null || echo not) + +ifneq (,$(filter $(ARCH),riscv)) +RISCV_SUBTARGETS ?= hwprobe +else +RISCV_SUBTARGETS := +endif + +CFLAGS := -Wall -O2 -g + +# A proper top_srcdir is needed by KSFT(lib.mk) +top_srcdir = $(realpath ../../../../) + +# Additional include paths needed by kselftest.h and local headers +CFLAGS += -I$(top_srcdir)/tools/testing/selftests/ + +CFLAGS += $(KHDR_INCLUDES) + +export CFLAGS +export top_srcdir + +all: + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + mkdir -p $$BUILD_TARGET; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +install: all + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +run_tests: all + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +# Avoid any output on non riscv on emit_tests +emit_tests: all + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +clean: + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +.PHONY: all clean install run_tests emit_tests diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing/selftests/riscv/hwprobe/Makefile new file mode 100644 index 000000000000..ebdbb3c22e54 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2021 ARM Limited +# Originally tools/testing/arm64/abi/Makefile + +TEST_GEN_PROGS := hwprobe + +include ../../lib.mk + +$(OUTPUT)/hwprobe: hwprobe.c sys_hwprobe.S + $(CC) -o$@ $(CFLAGS) $(LDFLAGS) $^ diff --git a/tools/testing/selftests/riscv/hwprobe/hwprobe.c b/tools/testing/selftests/riscv/hwprobe/hwprobe.c new file mode 100644 index 000000000000..ddfb61de2938 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/hwprobe.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +/* + * Rather than relying on having a new enough libc to define this, just do it + * ourselves. This way we don't need to be coupled to a new-enough libc to + * contain the call. + */ +long riscv_hwprobe(struct riscv_hwprobe *pairs, long pair_count, + long cpu_count, unsigned long *cpus, unsigned long flags); + +int main(int argc, char **argv) +{ + struct riscv_hwprobe pairs[8]; + unsigned long cpus; + long out; + + /* Fake the CPU_SET ops. */ + cpus = -1; + + /* + * Just run a basic test: pass enough pairs to get up to the base + * behavior, and then check to make sure it's sane. + */ + for (long i = 0; i < 8; i++) + pairs[i].key = i; + out = riscv_hwprobe(pairs, 8, 1, &cpus, 0); + if (out != 0) + return -1; + for (long i = 0; i < 4; ++i) { + /* Fail if the kernel claims not to recognize a base key. */ + if ((i < 4) && (pairs[i].key != i)) + return -2; + + if (pairs[i].key != RISCV_HWPROBE_KEY_BASE_BEHAVIOR) + continue; + + if (pairs[i].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA) + continue; + + return -3; + } + + /* + * This should also work with a NULL CPU set, but should not work + * with an improperly supplied CPU set. + */ + out = riscv_hwprobe(pairs, 8, 0, 0, 0); + if (out != 0) + return -4; + + out = riscv_hwprobe(pairs, 8, 0, &cpus, 0); + if (out == 0) + return -5; + + out = riscv_hwprobe(pairs, 8, 1, 0, 0); + if (out == 0) + return -6; + + /* + * Check that keys work by providing one that we know exists, and + * checking to make sure the resultig pair is what we asked for. + */ + pairs[0].key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR; + out = riscv_hwprobe(pairs, 1, 1, &cpus, 0); + if (out != 0) + return -7; + if (pairs[0].key != RISCV_HWPROBE_KEY_BASE_BEHAVIOR) + return -8; + + /* + * Check that an unknown key gets overwritten with -1, + * but doesn't block elements after it. + */ + pairs[0].key = 0x5555; + pairs[1].key = 1; + pairs[1].value = 0xAAAA; + out = riscv_hwprobe(pairs, 2, 0, 0, 0); + if (out != 0) + return -9; + + if (pairs[0].key != -1) + return -10; + + if ((pairs[1].key != 1) || (pairs[1].value == 0xAAAA)) + return -11; + + return 0; +} diff --git a/tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S b/tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S new file mode 100644 index 000000000000..ed8d28863b27 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2022 Rivos, Inc */ + +.text +.global riscv_hwprobe +riscv_hwprobe: + # Put __NR_riscv_hwprobe in the syscall number register, then just shim + # back the kernel's return. This doesn't do any sort of errno + # handling, the caller can deal with it. + li a7, 258 + ecall + ret From patchwork Tue Feb 21 19:08:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 60232 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp178589wrd; Tue, 21 Feb 2023 11:12:47 -0800 (PST) X-Google-Smtp-Source: AK7set8/vuixCU5Zd35WgE+fwfuyGwuhA2p6qp5A9awHjZapPe8ZnOMjF6F75pYnazf9Atvc96Zu X-Received: by 2002:a17:906:9f25:b0:8b1:7569:ad58 with SMTP id fy37-20020a1709069f2500b008b17569ad58mr10099908ejc.2.1677006767264; Tue, 21 Feb 2023 11:12:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677006767; cv=none; d=google.com; s=arc-20160816; b=l1TByseU5m6oVSaTZhEWHyW1lFZfRZ3uaZzrkpvV0hdvBhTsI5Xxlz9eN+COPWsFJ4 oehtVs1moaSTA5Yw3RcVWl7NGleuSJafwqo7r0n7G6KsFuG8c0pW+cnbMRksAbb4i4lA lIIOqCf8RTJLe8M6OrR/kDH2Djqfii5sjftA3Fgua0WV873Izn5HVBq8WYQk7lXc2H4+ tXo0KXaA5fF/Em6ntpxH1XkNj6JIPxDJVxrIdWi0THM6+A0FBk1ZkJoxuv2+eFhCpueq nCgnmv/t1nqDDMH6pjQrl3mD2IOO3FWUFfDsiP0wuE2tpKWcNJzTgVwjO+4Ex4pd2ZEg nkgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KbdXcY/cyfsn3vuj+G9y8VbBmqDYFOwE9fF3Bt0phIY=; b=MgEL/n51V/qmN+I6eJX/GSMlRHMPfE5EhzaAIbBFhmMuGLpFAhTOOvZHKhDWWyBqaT bcWbWaqTVxaww+uk4AVFmYHMjAOX4FztCLBB+BZ1WDzrm91830cA0pIZhvdH/5Gi6ju0 O6q6epvrjEKQuKq+qcTCr7SsY19oD/y2qkAIOkgVaZSWCigvdPljN0rhSVxioxwsI8X4 UvcKQ175c4uoSeCDkhxPNrFDqtq4FYEd/OCdPzjjeXo502jbP0Ag1E6kOaAspS1gyzGT VGQ8CQwXAjYY1QU8U/EwTrKGqUaGil1fVqXrNZ6OPiiM1B9atIqMKNPI5SYGEezVxXUI o6HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20210112.gappssmtp.com header.s=20210112 header.b=csHRX7en; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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We stash a copy of static answers for the "all CPUs" case in the vDSO data page. This data is private to the vDSO, so we can decide later to change what's stored there or under what conditions we defer to the syscall. Currently all data can be discovered at boot, so the vDSO function answers all queries when the cpumask is set to the "all CPUs" hint. There's also a boolean in the data that lets the vDSO function know that all CPUs are the same. In that case, the vDSO will also answer queries for arbitrary CPU masks in addition to the "all CPUs" hint. Signed-off-by: Evan Green --- Changes in v3: - Introduced vDSO function One aspect of this that's less than perfect is that there are two copies of the arch_vdso_data in the data page. This stems from the fact that vdso_data is arrayed by CS_BASES. Since we're very far away from filling up the page, and this is not ABI, I left it for now. If things get full we can move this data out to its own page, or refactor vdso_data tree-wide to allow for non-arrayed data. --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/vdso/data.h | 17 ++++++++++ arch/riscv/kernel/sys_riscv.c | 41 ++++++++++++++++++++++++ arch/riscv/kernel/vdso/Makefile | 2 ++ arch/riscv/kernel/vdso/hwprobe.c | 47 ++++++++++++++++++++++++++++ arch/riscv/kernel/vdso/sys_hwprobe.S | 15 +++++++++ arch/riscv/kernel/vdso/vdso.lds.S | 1 + 7 files changed, 124 insertions(+) create mode 100644 arch/riscv/include/asm/vdso/data.h create mode 100644 arch/riscv/kernel/vdso/hwprobe.c create mode 100644 arch/riscv/kernel/vdso/sys_hwprobe.S diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e2b656043abf..218e75975a15 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -33,6 +33,7 @@ config RISCV select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UBSAN_SANITIZE_ALL + select ARCH_HAS_VDSO_DATA select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT select ARCH_STACKWALK diff --git a/arch/riscv/include/asm/vdso/data.h b/arch/riscv/include/asm/vdso/data.h new file mode 100644 index 000000000000..dc2f76f58b76 --- /dev/null +++ b/arch/riscv/include/asm/vdso/data.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __RISCV_ASM_VDSO_DATA_H +#define __RISCV_ASM_VDSO_DATA_H + +#include +#include +#include + +struct arch_vdso_data { + /* Stash static answers to the hwprobe queries when all CPUs are selected. */ + __u64 all_cpu_hwprobe_values[RISCV_HWPROBE_MAX_KEY + 1]; + + /* Boolean indicating all CPUs have the same static hwprobe values. */ + __u8 homogeneous_cpus; +}; + +#endif /* __RISCV_ASM_VDSO_DATA_H */ diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index afc1b96d5c1a..113b3d97c8cc 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -14,6 +14,7 @@ #include #include #include +#include static long riscv_sys_mmap(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, @@ -242,6 +243,46 @@ int do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, long pair_count, } +static int __init init_hwprobe_vdso_data(void) +{ + struct vdso_data *vd = __arch_get_k_vdso_data(); + struct arch_vdso_data *avd = &vd->arch_data; + u64 id_bitsmash = 0; + struct riscv_hwprobe pair; + int key; + + /* + * Initialize vDSO data with the answers for the "all CPUs" case, to + * save a syscall in the common case. + */ + for (key = 0; key <= RISCV_HWPROBE_MAX_KEY; key++) { + pair.key = key; + hwprobe_one_pair(&pair, cpu_online_mask); + + WARN_ON_ONCE(pair.key < 0); + + avd->all_cpu_hwprobe_values[key] = pair.value; + /* + * Smash together the vendor, arch, and impl IDs to see if + * they're all 0 or any negative. + */ + if (key <= RISCV_HWPROBE_KEY_MIMPID) + id_bitsmash |= pair.value; + } + + /* + * If the arch, vendor, and implementation ID are all the same across + * all harts, then assume all CPUs are the same, and allow the vDSO to + * answer queries for arbitrary masks. However if all values are 0 (not + * populated) or any value returns -1 (varies across CPUs), then the + * vDSO should defer to the kernel for exotic cpu masks. + */ + avd->homogeneous_cpus = (id_bitsmash > 0); + return 0; +} + +arch_initcall_sync(init_hwprobe_vdso_data); + SYSCALL_DEFINE5(riscv_hwprobe, uintptr_t, pairs, uintptr_t, pair_count, uintptr_t, cpu_count, uintptr_t, cpus, uintptr_t, flags) { diff --git a/arch/riscv/kernel/vdso/Makefile b/arch/riscv/kernel/vdso/Makefile index 06e6b27f3bcc..107fd2162cdf 100644 --- a/arch/riscv/kernel/vdso/Makefile +++ b/arch/riscv/kernel/vdso/Makefile @@ -12,6 +12,8 @@ vdso-syms += vgettimeofday endif vdso-syms += getcpu vdso-syms += flush_icache +vdso-syms += hwprobe +vdso-syms += sys_hwprobe # Files to link into the vdso obj-vdso = $(patsubst %, %.o, $(vdso-syms)) note.o diff --git a/arch/riscv/kernel/vdso/hwprobe.c b/arch/riscv/kernel/vdso/hwprobe.c new file mode 100644 index 000000000000..1792d6c30c97 --- /dev/null +++ b/arch/riscv/kernel/vdso/hwprobe.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2023 Rivos, Inc + */ + +#include +#include +#include + +extern int riscv_hwprobe(struct riscv_hwprobe *pairs, long pair_count, + long cpu_count, unsigned long *cpus, + unsigned long flags); + +int __vdso_riscv_hwprobe(struct riscv_hwprobe *pairs, long pair_count, + long cpu_count, unsigned long *cpus, + unsigned long flags) +{ + const struct vdso_data *vd = __arch_get_vdso_data(); + const struct arch_vdso_data *avd = &vd->arch_data; + bool all_cpus = !cpu_count && !cpus; + struct riscv_hwprobe *p = pairs; + struct riscv_hwprobe *end = pairs + pair_count; + + /* + * Defer to the syscall for exotic requests. The vdso has answers + * stashed away only for the "all cpus" case. If all CPUs are + * homogeneous, then this function can handle requests for arbitrary + * masks. + */ + if ((flags != 0) || (!all_cpus && !avd->homogeneous_cpus)) + return riscv_hwprobe(pairs, pair_count, cpu_count, cpus, flags); + + /* This is something we can handle, fill out the pairs. */ + while (p < end) { + if (p->key <= RISCV_HWPROBE_MAX_KEY) { + p->value = avd->all_cpu_hwprobe_values[p->key]; + + } else { + p->key = -1; + p->value = 0; + } + + p++; + } + + return 0; +} diff --git a/arch/riscv/kernel/vdso/sys_hwprobe.S b/arch/riscv/kernel/vdso/sys_hwprobe.S new file mode 100644 index 000000000000..2511c8ba8f86 --- /dev/null +++ b/arch/riscv/kernel/vdso/sys_hwprobe.S @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2022 Rivos, Inc */ + +#include +#include + +.text +ENTRY(riscv_hwprobe) + .cfi_startproc + li a7, __NR_riscv_hwprobe + ecall + ret + + .cfi_endproc +ENDPROC(riscv_hwprobe) diff --git a/arch/riscv/kernel/vdso/vdso.lds.S b/arch/riscv/kernel/vdso/vdso.lds.S index 150b1a572e61..dfe63fb71041 100644 --- a/arch/riscv/kernel/vdso/vdso.lds.S +++ b/arch/riscv/kernel/vdso/vdso.lds.S @@ -75,6 +75,7 @@ VERSION #endif __vdso_getcpu; __vdso_flush_icache; + __vdso_riscv_hwprobe; local: *; }; }