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Mon, 17 Oct 2022 20:21:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1666063281; bh=5rez8qYjf0NKGjU9X2fo6bHVw919Ec9FBSH61oJQCaA=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=nuHpR0uUQbAZRV03IPprYEp3zjTQD4IUrrcgHsLGCEvDm1A0TcD5d1BxAlnC5T8Yo stmucL3WEA6POSQailbbpJfCwnZyrbJCZpwiXcMkpui1DfJMgfexm7FnyWuLkAaBW+ 3XKUGfXEs3JD6TzMSsW7Rin+egEjN0u9Loqp11FCGUOUO9Xql00pF/LxU65XOWkLQG gh8PE9UDQtObQEHy6aWAxzuX3eoy9CYSQ1Yw9cWfwil6+9DV2EJ+EE2NZPLhAzhFK3 dUzZwxT9q7gPWeOMxVxtoh3J4ErXzy9Qb/o8nUUk79f0DRTvZO2qS1ip7UzCdgmNeT C/TuY22P4184Q== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: ira.weiny@intel.com, Jonathan.Cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, bwidawsk@kernel.org, vishal.l.verma@intel.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support Date: Mon, 17 Oct 2022 20:00:09 -0700 Message-Id: <20221018030010.20913-2-dave@stgolabs.net> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018030010.20913-1-dave@stgolabs.net> References: <20221018030010.20913-1-dave@stgolabs.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746996324689882707?= X-GMAIL-MSGID: =?utf-8?q?1746996324689882707?= Introduce a generic irq table for CXL components/features that can have standard irq support - DOE requires dynamic vector sizing and is not considered here. For now the table is empty. Create an infrastructure to query the max vectors required for the CXL device. Upon successful allocation, users can plug in their respective isr at any point thereafter, which is supported by a new cxlds->has_irq flag, for example, if the irq setup is not done in the PCI driver, such as the case of the CXL-PMU. Reviewed-by: Dave Jiang Signed-off-by: Davidlohr Bueso Reviewed-by: Jonathan Cameron --- drivers/cxl/cxlmem.h | 3 ++ drivers/cxl/pci.c | 72 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 88e3a8e54b6a..72b69b003302 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -211,6 +211,7 @@ struct cxl_endpoint_dvsec_info { * @info: Cached DVSEC information about the device. * @serial: PCIe Device Serial Number * @doe_mbs: PCI DOE mailbox array + * @has_irq: PCIe MSI-X/MSI support * @mbox_send: @dev specific transport for transmitting mailbox commands * * See section 8.2.9.5.2 Capacity Configuration and Label Storage for @@ -247,6 +248,8 @@ struct cxl_dev_state { struct xarray doe_mbs; + bool has_irq; + int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); }; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index faeb5d9d7a7a..9c3e95ebaa26 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -428,6 +428,73 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) } } +/** + * struct cxl_irq_cap - CXL feature that is capable of receiving MSI-X/MSI irqs. + * + * @name: Name of the device/component generating this interrupt. + * @get_max_msgnum: Get the feature's largest interrupt message number. If the + * feature does not have the Interrupt Supported bit set, then + * return -1. + */ +struct cxl_irq_cap { + const char *name; + int (*get_max_msgnum)(struct cxl_dev_state *cxlds); +}; + +static const struct cxl_irq_cap cxl_irq_cap_table[] = { + NULL +}; + +static void cxl_pci_free_irq_vectors(void *data) +{ + pci_free_irq_vectors(data); +} + +/* + * Attempt to allocate the largest amount of necessary vectors. + * + * Returns 0 upon a successful allocation of *all* vectors, or a + * negative value otherwise. + */ +static int cxl_pci_alloc_irq_vectors(struct cxl_dev_state *cxlds) +{ + struct device *dev = cxlds->dev; + struct pci_dev *pdev = to_pci_dev(dev); + int rc, i, vectors = -1; + + for (i = 0; i < ARRAY_SIZE(cxl_irq_cap_table); i++) { + int irq; + + if (!cxl_irq_cap_table[i].get_max_msgnum) + continue; + + irq = cxl_irq_cap_table[i].get_max_msgnum(cxlds); + vectors = max_t(int, irq, vectors); + } + + /* + * Semantically lack of irq support is not an error, but we + * still fail to allocate, so return negative. + */ + if (vectors == -1) + return -1; + + vectors++; + rc = pci_alloc_irq_vectors(pdev, vectors, vectors, + PCI_IRQ_MSIX | PCI_IRQ_MSI); + if (rc < 0) + return rc; + + if (rc != vectors) { + dev_dbg(dev, "Not enough interrupts; use polling instead.\n"); + /* some got allocated, clean them up */ + cxl_pci_free_irq_vectors(pdev); + return -ENOSPC; + } + + return devm_add_action_or_reset(dev, cxl_pci_free_irq_vectors, pdev); +} + static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct cxl_register_map map; @@ -494,6 +561,11 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) return rc; + if (!cxl_pci_alloc_irq_vectors(cxlds)) { + cxlds->has_irq = true; + } else + cxlds->has_irq = false; + cxlmd = devm_cxl_add_memdev(cxlds); if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); From patchwork Tue Oct 18 03:00:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Davidlohr Bueso X-Patchwork-Id: 3915 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1760555wrs; Mon, 17 Oct 2022 20:47:17 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4c1Bterbba7fNzPy5qDiO0OEVPBhLhstaxEsnnMXAqPDZxBC4tWCeAsn8Hy+Oqaip6bDRl X-Received: by 2002:a05:6402:4505:b0:451:1551:7b14 with SMTP id ez5-20020a056402450500b0045115517b14mr775216edb.300.1666064837291; Mon, 17 Oct 2022 20:47:17 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666064837; cv=pass; d=google.com; s=arc-20160816; b=RVnjkdYOqIafl6gAxWk2y3ULP68fz5EaPocbALRJBCfzauWDRRPiv2cGwDj1Z+3P/U pVpS9Mh5DQTX7jUSXYnNE4bbmkV1rKjJoBZ1aHDc6krYI1IRhTHHGSz2HbCUOxAQMfjy c1YPa7ZJzil4ke5c65dwrRE0f+VAOxkWw00yHBVb/B9XKt3mq+jIrQsB3PlWo8FnXj4f 7Cvrq1/aK3GiVt8ayEdgXGeWFp03xmWw5yA7Fg3MWb/fdyEPl8fFxajBjLvtE941S/zc opuXCjTfcomNIasEJ5rS2Zo4SgBjOVS9v+bXEagwea+80N1ObHFvvMs7Ce2J4u865RVG 71EA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+F77OywPESqqbC+/oPvGc0AQuP7cONHmICZM40h0KBY=; b=aXuTctSe7YSHhV6/1yRcRYv5Ab3o2CtswQJk8HZO8lmVMhxoiCrtj60QkeCgtig6ah E2xi4DgKTIHAYAdIWnJ3EPzsZpAj9Vu1SaG8mPUli95lG7fgaIabKaSilLOuFfT74wVZ qVI/tI7l5iJmIV/JzF6WzaMoISR+KUvpYTKlYvIWMS6tWAGjQ5qQng9FXnwGF8dpQDsj Hor6s4CGWxqNQBbSjdiUeh5AJ9uV39iwa8ctxsD61Ss4CpKAElYCqtOknRc2iE10ulvZ QVlHQeTvppawiVbIPrkfGVPC8ok29M8DtS4hN4HVjA3iG5TgeK0qiGpkj5dbJS5aubUX vjtQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@stgolabs.net header.s=dreamhost header.b=AU8abd9B; arc=pass (i=1); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Mon, 17 Oct 2022 20:21:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1666063282; bh=+F77OywPESqqbC+/oPvGc0AQuP7cONHmICZM40h0KBY=; h=From:To:Cc:Subject:Date:Content-Transfer-Encoding; b=AU8abd9B2gT8pXCbb1HVa2wtEwJD7UPCT98DA++jcGBufcCBd3vRzosXU5rhtQPkZ ANNbuIDk82wJiei8hR++2OkTJaRk3bbr865B8SqGeL4cey05gK0f7zSkSOgi2UggS9 DJu7I8rFna9uAh5I/Nbp6VQzlVn2uP1aw1+e8tThOqOUyRUwEvJg9nfohu2UAavXhL oH3ybDdo4PwtW9icrLt/av6h09Kj78bvAzRFRxgQQxyTaUtbT+KkqFjEfC/QAjZHYE Iy5Q6jYp4IJvE0iHnfeQlX6YYEK8vMFm/MjX+7HWUw/D91iyQw2RWtc4MQowF6IkNU XxHvVCQ2QTRVg== From: Davidlohr Bueso To: dan.j.williams@intel.com Cc: ira.weiny@intel.com, Jonathan.Cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, bwidawsk@kernel.org, vishal.l.verma@intel.com, a.manzanares@samsung.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, dave@stgolabs.net Subject: [PATCH 2/2] cxl/mbox: Wire up irq support Date: Mon, 17 Oct 2022 20:00:10 -0700 Message-Id: <20221018030010.20913-3-dave@stgolabs.net> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018030010.20913-1-dave@stgolabs.net> References: <20221018030010.20913-1-dave@stgolabs.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746995602843328252?= X-GMAIL-MSGID: =?utf-8?q?1746995602843328252?= With enough vectors properly allocated, this adds support for (the primary) mailbox interrupt, which is needed for background completion handling, beyond polling. Signed-off-by: Davidlohr Bueso --- drivers/cxl/cxl.h | 1 + drivers/cxl/pci.c | 29 ++++++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index f680450f0b16..13a9743b0012 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -135,6 +135,7 @@ static inline int ways_to_cxl(unsigned int ways, u8 *iw) /* CXL 2.0 8.2.8.4 Mailbox Registers */ #define CXLDEV_MBOX_CAPS_OFFSET 0x00 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) +#define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) #define CXLDEV_MBOX_CTRL_OFFSET 0x04 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) #define CXLDEV_MBOX_CMD_OFFSET 0x08 diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 9c3e95ebaa26..c3f3ee307d7a 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -274,6 +274,32 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds) return 0; } +static int cxl_pci_mbox_get_max_msgnum(struct cxl_dev_state *cxlds) +{ + int cap; + + cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); + return FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); +} + +static irqreturn_t cxl_pci_mbox_irq(int irq, void *id) +{ + /* TODO: handle completion of background commands */ + return IRQ_HANDLED; +} + +static void cxl_pci_mbox_irqsetup(struct cxl_dev_state *cxlds) +{ + struct device *dev = cxlds->dev; + struct pci_dev *pdev = to_pci_dev(dev); + int irq; + + irq = cxl_pci_mbox_get_max_msgnum(cxlds); + if (!pci_request_irq(pdev, irq, cxl_pci_mbox_irq, NULL, + cxlds, "%s-mailbox", dev_name(dev))) + dev_dbg(dev, "Mailbox irq (%d) supported", irq); +} + static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map) { void __iomem *addr; @@ -442,7 +468,7 @@ struct cxl_irq_cap { }; static const struct cxl_irq_cap cxl_irq_cap_table[] = { - NULL + { "mailbox", cxl_pci_mbox_get_max_msgnum }, }; static void cxl_pci_free_irq_vectors(void *data) @@ -562,6 +588,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return rc; if (!cxl_pci_alloc_irq_vectors(cxlds)) { + cxl_pci_mbox_irqsetup(cxlds); cxlds->has_irq = true; } else cxlds->has_irq = false;