From patchwork Mon Feb 20 07:01:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 59353 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1231418wrn; Mon, 20 Feb 2023 02:27:37 -0800 (PST) X-Google-Smtp-Source: AK7set+PE9g0fMVAbXXzwhOXhhWHkOLaCbbZHgWfOEuatBQz3qJMto3BFWO9BvbhLrz+f5C2UKbb X-Received: by 2002:a17:906:d118:b0:8d9:383a:be39 with SMTP id b24-20020a170906d11800b008d9383abe39mr873951ejz.41.1676888857692; Mon, 20 Feb 2023 02:27:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676888857; cv=none; d=google.com; s=arc-20160816; b=G5oPmG7RCBZ1ylxpgRMZiCYaNsFVQiaul8F7UQRfE8bstqHI8HaXSpe38S/p8MG449 VzVcorMS5us5uFfJ9TUOPJ4hE1wzp9PPINT4GGU5lAsFl+vW9bJ39bg5kBRtaZkcWqUa m3DGKmQE3bcxiITw+WZXVjHw99jRUzeJSiNzrWKAdH3HR2h5hxBaQ3pfJ5KVtmImgBhH fybCOddrLrXEzaZcFC3jhl6HVrXmfd84vyVv62qF3NEbbdzrq8k7nyxsNgiUUzmCTVne veWpfGYoeyW48PY7eNJdVXLleWz7gcavaFh3Ciw0bNnaJhJX2IHm8FyKb+jUpgbFIUJX 0gmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=iRsrn2nweMHt6YxplGjC+Db5ugEbrA08yxO8lSEjfAg=; b=yGjgAbBSO01TBsqDzMdJMk7bgUWj2ZDREtRIz9tDGT48bYuaDZz9j+u9lMW1OrIevm fxcsGfux0i/sPBm0GDNwFx6Ug3eCOZHA1hg9aXmR3OtSlgrIXooT9MPXsDTIBRfYgXKT 3JB8V0iXy+LZWL4wTexyCTioy/sbK3hb6+rRD5ewi/8MLLEDUGaUtE5kEREAoeEUq6zX UxQVvEzX1txElDbTSq/JlEpY1KBZ5GeaQTB+kXIdDBiPOkMsGfy+PEUJLMEYdZT9jEEz SihhoWkaraE+mGoUFE1GrHMSmTYvlXet6mbVYtK34ZB9s9dheKXzhCbNX0nBC+FL6eb+ oD6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id i4-20020a056402054400b004accfcb093csi2255366edx.240.2023.02.20.02.27.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 02:27:37 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0B667393BC10 for ; Mon, 20 Feb 2023 10:16:04 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 1ED0B3858416 for ; Mon, 20 Feb 2023 10:15:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1ED0B3858416 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowABHoNfVGvNjlPdOBg--.59272S3; Mon, 20 Feb 2023 15:01:42 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Liao Shihua Subject: [PATCH V3 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Date: Mon, 20 Feb 2023 15:01:21 +0800 Message-Id: <20230220070125.2291-2-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230220070125.2291-1-shihua@iscas.ac.cn> References: <20230220070125.2291-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABHoNfVGvNjlPdOBg--.59272S3 X-Coremail-Antispam: 1UD129KBjvJXoWxCryxCFW5tr1ftrWUAF4ruFg_yoW5WF13pa 10g3Z5Crn5G3Z3Gr4xtF1rtr4ft39ag3y5JwnIvF45AFW7WryktF1DWa1UWw1DCF1UGw1j k34rKFyFvr4Ykr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9v14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1Y6r1xM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48JMxC20s 026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_ JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14 v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xva j40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JV W8JrUvcSsGvfC2KfnxnUUI43ZEXa7VU1IPfPUUUUU== X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiBwMIEWPy4dOfggAAsj X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758345410773907621?= X-GMAIL-MSGID: =?utf-8?q?1758345410773907621?= This patch adds prototypes for RISC-V Crypto built-in functions. gcc/ChangeLog: * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): (RISCV_FTYPE_NAME3): (RISCV_ATYPE_QI): (RISCV_ATYPE_HI): (RISCV_FTYPE_ATYPES2): (RISCV_FTYPE_ATYPES3): * config/riscv/riscv-ftypes.def (2): (3): Co-Authored-By: SiYu Wu --- gcc/config/riscv/riscv-builtins.cc | 8 ++++++++ gcc/config/riscv/riscv-ftypes.def | 10 ++++++++++ 2 files changed, 18 insertions(+) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 25ca407f9a9..ded91e17554 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -42,6 +42,8 @@ along with GCC; see the file COPYING3. If not see /* Macros to create an enumeration identifier for a function prototype. */ #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B +#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C +#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D /* Classifies the prototype of a built-in function. */ enum riscv_function_type { @@ -132,6 +134,8 @@ AVAIL (always, (!0)) /* Argument types. */ #define RISCV_ATYPE_VOID void_type_node #define RISCV_ATYPE_USI unsigned_intSI_type_node +#define RISCV_ATYPE_QI intQI_type_node +#define RISCV_ATYPE_HI intHI_type_node #define RISCV_ATYPE_SI intSI_type_node #define RISCV_ATYPE_DI intDI_type_node #define RISCV_ATYPE_VOID_PTR ptr_type_node @@ -142,6 +146,10 @@ AVAIL (always, (!0)) RISCV_ATYPE_##A #define RISCV_FTYPE_ATYPES1(A, B) \ RISCV_ATYPE_##A, RISCV_ATYPE_##B +#define RISCV_FTYPE_ATYPES2(A, B, C) \ + RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C +#define RISCV_FTYPE_ATYPES3(A, B, C, D) \ + RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D static const struct riscv_builtin_description riscv_builtins[] = { #include "riscv-cmo.def" diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 3a40c33e7c2..3b518195a29 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -32,3 +32,13 @@ DEF_RISCV_FTYPE (1, (VOID, USI)) DEF_RISCV_FTYPE (1, (VOID, VOID_PTR)) DEF_RISCV_FTYPE (1, (SI, SI)) DEF_RISCV_FTYPE (1, (DI, DI)) +DEF_RISCV_FTYPE (2, (SI, QI, QI)) +DEF_RISCV_FTYPE (2, (SI, HI, HI)) +DEF_RISCV_FTYPE (2, (SI, SI, SI)) +DEF_RISCV_FTYPE (2, (DI, QI, QI)) +DEF_RISCV_FTYPE (2, (DI, HI, HI)) +DEF_RISCV_FTYPE (2, (DI, SI, SI)) +DEF_RISCV_FTYPE (2, (DI, DI, SI)) +DEF_RISCV_FTYPE (2, (DI, DI, DI)) +DEF_RISCV_FTYPE (3, (SI, SI, SI, SI)) +DEF_RISCV_FTYPE (3, (DI, DI, DI, SI)) From patchwork Mon Feb 20 07:01:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 59355 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1232055wrn; Mon, 20 Feb 2023 02:29:39 -0800 (PST) X-Google-Smtp-Source: AK7set/RTBLfXG1GCAClYoX68naAMJpZ61pbpgDjIV/2VIhwUvCFbkb1p2xD/NqDevNNT/KFFaKu X-Received: by 2002:a17:906:5acb:b0:886:7eae:26c4 with SMTP id x11-20020a1709065acb00b008867eae26c4mr6124287ejs.5.1676888979346; Mon, 20 Feb 2023 02:29:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676888979; cv=none; d=google.com; s=arc-20160816; b=lfDLChDGHPkEOxOqP2OWKvfzgxlubJiQ1SRE/a8dMs2SxbskS51uDl7EmYZXcH1K36 wdszubXocbCJVO4zoHlkE1DBfWAB3DH91Y37r2sf2aX3WVskjgf7m+mSxr+NvoAkEX/w 1urquUdPVJQ5svmdqoK7Zftd29tIXhW2RhlJRbDEAZC8Rt9FXRLpu8V3cklOLO4ysI7V AUWoJ1/bx4VWfBnJoDR3B2Rnx9/CtD+3VMxVPeP5za+nN4FD/GioQSqqibaAY4nhb2WX aU9e9QAMS4ZCOStFsrqntQfZkgZEgvEoJyzH0xgHcunCtgMmeAX5tlA2O7ivW873W+gO iymQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=CcGJa0oMiKpn00cYZGYaijHmU+JhM3Hgd0NihFjCEtU=; b=GZ5Q2yW+PQXfeUfIDjPD739eEwWfwBRHt5mD6t68EiOkjcQTLzyz4kmRvqKlCyj/tI iJU5Rszy+vKOW8xmSStqqr7bsyDzogyh9dMs4bJmvpqYNaAaGY9ji5AG5URxaeUaciYX 5xnEqXvsolU9PX1ws4PTpn+/nR5CZpIv9WNEtVaY67KJzK3dYRk0Z8pO3a/Zi+8fFSzZ YtBR4tb8d32AtaVDZuBdr3a0VcF2BMb4zL4cPAz4czjg7O5KM15N8nymA/IrMScqax8p VyWSMtKyHbGckxDYma4wOP9ANxk86JvhVgz6Boyp/U72xGQEmYPDQE5WqeaUpqvZML/C BdcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id gk3-20020a17090790c300b008be6648db8asi8076523ejb.408.2023.02.20.02.29.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 02:29:39 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6F2E4380E0E9 for ; Mon, 20 Feb 2023 10:16:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 16CB53858C31 for ; Mon, 20 Feb 2023 10:15:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 16CB53858C31 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowABHoNfVGvNjlPdOBg--.59272S4; Mon, 20 Feb 2023 15:01:42 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Liao Shihua Subject: [PATCH V3 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions Date: Mon, 20 Feb 2023 15:01:22 +0800 Message-Id: <20230220070125.2291-3-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230220070125.2291-1-shihua@iscas.ac.cn> References: <20230220070125.2291-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABHoNfVGvNjlPdOBg--.59272S4 X-Coremail-Antispam: 1UD129KBjvAXoWfXF18Ar1UAw15trykGrWUXFb_yoW8ZF4xKo Z3tr4kJr45GFyI9ws8uw43XrnrW3Wqyrs5Xa90vrWFy3Z5Jr1rKw17Kan8Aas3Xr1xXFyU Za97uan7XFWkWas3n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYm7AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr 0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUdl19UUUUU= X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiAw4IEWPy4r6apAAAsn X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758345538475166266?= X-GMAIL-MSGID: =?utf-8?q?1758345538475166266?= This patch supports Zkbk, Zbkc and Zkbx extension. It includes instruction's machine description and built-in funtions. It is worth mentioning that this patch only adds instructions in Zbkb but no longer in Zbb. If any instructions both in Zbb and Zbkb, they will be generated by code generator instead of built-in functions. gcc/ChangeLog: * config/riscv/bitmanip.md: Add ZBKB's instructions. * config/riscv/riscv-builtins.cc (AVAIL): * config/riscv/riscv.md: * config/riscv/crypto.md: Add Scalar Cryptography extension's machine description file. * config/riscv/riscv-scalar-crypto.def: Add Scalar Cryptography extension's built-in function file. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbkb32.c: New test. * gcc.target/riscv/zbkb64.c: New test. * gcc.target/riscv/zbkc32.c: New test. * gcc.target/riscv/zbkc64.c: New test. * gcc.target/riscv/zbkx32.c: New test. * gcc.target/riscv/zbkx64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/bitmanip.md | 20 ++-- gcc/config/riscv/crypto.md | 128 +++++++++++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 7 ++ gcc/config/riscv/riscv-scalar-crypto.def | 45 ++++++++ gcc/config/riscv/riscv.md | 4 +- gcc/testsuite/gcc.target/riscv/zbkb32.c | 36 +++++++ gcc/testsuite/gcc.target/riscv/zbkb64.c | 28 +++++ gcc/testsuite/gcc.target/riscv/zbkc32.c | 17 +++ gcc/testsuite/gcc.target/riscv/zbkc64.c | 17 +++ gcc/testsuite/gcc.target/riscv/zbkx32.c | 18 ++++ gcc/testsuite/gcc.target/riscv/zbkx64.c | 18 ++++ 11 files changed, 327 insertions(+), 11 deletions(-) create mode 100644 gcc/config/riscv/crypto.md create mode 100644 gcc/config/riscv/riscv-scalar-crypto.def create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 14d18edbe62..f076ba35832 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -189,7 +189,7 @@ [(set (match_operand:X 0 "register_operand" "=r") (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r")) (match_operand:X 2 "register_operand" "r")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "n\t%0,%2,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) @@ -203,7 +203,7 @@ (const_int 0))) (match_operand:DI 2 "register_operand"))) (clobber (match_operand:DI 3 "register_operand"))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63))) (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))]) @@ -211,7 +211,7 @@ [(set (match_operand:X 0 "register_operand" "=r") (not:X (xor:X (match_operand:X 1 "register_operand" "r") (match_operand:X 2 "register_operand" "r"))))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "xnor\t%0,%1,%2" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) @@ -277,7 +277,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -285,7 +285,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (rotatert:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "ror%i2\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -293,7 +293,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r"))))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "rorw\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -301,7 +301,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "rol%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -309,7 +309,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (rotate:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "rol\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -317,7 +317,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r"))))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "rolw\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -332,7 +332,7 @@ (define_insn "bswap2" [(set (match_operand:X 0 "register_operand" "=r") (bswap:X (match_operand:X 1 "register_operand" "r")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "rev8\t%0,%1" [(set_attr "type" "bitmanip")]) diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md new file mode 100644 index 00000000000..a270036e39b --- /dev/null +++ b/gcc/config/riscv/crypto.md @@ -0,0 +1,128 @@ +;; Machine description for RISC-V Scalar Cryptography extensions. +;; Copyright (C) 2023 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_c_enum "unspec" [ + ;; Zbkb unspecs + UNSPEC_BREV8 + UNSPEC_ZIP + UNSPEC_UNZIP + UNSPEC_PACK + UNSPEC_PACKH + UNSPEC_PACKW + + ;; Zbkc unspecs + UNSPEC_CLMUL + UNSPEC_CLMULH + + ;; Zbkx unspecs + UNSPEC_XPERM8 + UNSPEC_XPERM4 +]) + +;; ZBKB extension +(define_insn "riscv_brev8_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_BREV8))] + "TARGET_ZBKB" + "brev8\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_zip" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_ZIP))] + "TARGET_ZBKB && !TARGET_64BIT" + "zip\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_unzip" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_UNZIP))] + "TARGET_ZBKB && !TARGET_64BIT" + "unzip\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_pack_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:HISI 1 "register_operand" "r") + (match_operand:HISI 2 "register_operand" "r")] + UNSPEC_PACK))] + "TARGET_ZBKB" + "pack\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_packh_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:QI 1 "register_operand" "r") + (match_operand:QI 2 "register_operand" "r")] + UNSPEC_PACKH))] + "TARGET_ZBKB" + "packh\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_packw" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:HI 1 "register_operand" "r") + (match_operand:HI 2 "register_operand" "r")] + UNSPEC_PACKW))] + "TARGET_ZBKB && TARGET_64BIT" + "packw\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +;; ZBKC extension + +(define_insn "riscv_clmul_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMUL))] + "TARGET_ZBKC" + "clmul\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_clmulh_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMULH))] + "TARGET_ZBKC" + "clmulh\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +;; ZBKX extension + +(define_insn "riscv_xperm4_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_XPERM4))] + "TARGET_ZBKX" + "xperm4\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_xperm8_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_XPERM8))] + "TARGET_ZBKX" + "xperm8\t%0,%1,%2" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index ded91e17554..f0d60709c7d 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -100,6 +100,12 @@ AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT) AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT) AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) +AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT) +AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT) +AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT) +AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT) +AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT) +AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. @@ -153,6 +159,7 @@ AVAIL (always, (!0)) static const struct riscv_builtin_description riscv_builtins[] = { #include "riscv-cmo.def" + #include "riscv-scalar-crypto.def" DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float), diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def new file mode 100644 index 00000000000..e4c97acbc05 --- /dev/null +++ b/gcc/config/riscv/riscv-scalar-crypto.def @@ -0,0 +1,45 @@ +/* Builtin functions for RISC-V Scalar Cryptography extensions. + Copyright (C) 2023 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +// ZBKB +RISCV_BUILTIN (pack_sihi, "pack", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_HI_HI, crypto_zbkb32), +RISCV_BUILTIN (pack_disi, "pack", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_SI_SI, crypto_zbkb64), + +RISCV_BUILTIN (packh_si, "packh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_QI_QI, crypto_zbkb32), +RISCV_BUILTIN (packh_di, "packh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_QI_QI, crypto_zbkb64), + +RISCV_BUILTIN (packw, "packw", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_HI_HI, crypto_zbkb64), + +RISCV_BUILTIN (zip, "zip", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), +RISCV_BUILTIN (unzip, "unzip", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), + +RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), +RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zbkb64), + +// ZBKC +RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32), +RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64), +RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32), +RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64), + +// ZBKX +RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), +RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), +RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), +RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c8adc5af5d2..ddd014b1bb5 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -242,6 +242,7 @@ ;; bitmanip bit manipulation instructions ;; rotate rotation instructions ;; atomic atomic instructions +;; crypto cryptography instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read @@ -333,7 +334,7 @@ "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, - atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, + atomic,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, @@ -3086,6 +3087,7 @@ ) (include "bitmanip.md") +(include "crypto.md") (include "sync.md") (include "peephole.md") (include "pic.md") diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c new file mode 100644 index 00000000000..d12cec226ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int32_t foo1(int16_t rs1, int16_t rs2) +{ + return __builtin_riscv_pack(rs1, rs2); +} + +int32_t foo2(int8_t rs1, int8_t rs2) +{ + return __builtin_riscv_packh(rs1, rs2); +} + +int32_t foo3(int32_t rs1) +{ + return __builtin_riscv_brev8(rs1); +} + +int32_t foo4(int32_t rs1) +{ + return __builtin_riscv_zip(rs1); +} + +int32_t foo5(int32_t rs1) +{ + return __builtin_riscv_unzip(rs1); +} + +/* { dg-final { scan-assembler-times "pack\t" 1 } } */ +/* { dg-final { scan-assembler-times "packh" 1 } } */ +/* { dg-final { scan-assembler-times "brev8" 1 } } */ +/* { dg-final { scan-assembler-times "\tzip\t" 1 } } */ +/* { dg-final { scan-assembler-times "unzip" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c new file mode 100644 index 00000000000..645a35324c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include + +int64_t foo1(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_pack(rs1, rs2); +} + +int64_t foo2(int8_t rs1, int8_t rs2) +{ + return __builtin_riscv_packh(rs1, rs2); +} + +int64_t foo3(int16_t rs1, int16_t rs2) +{ + return __builtin_riscv_packw(rs1, rs2); +} + +int64_t foo4(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_brev8(rs1); +} +/* { dg-final { scan-assembler-times "pack\t" 1 } } */ +/* { dg-final { scan-assembler-times "packh" 1 } } */ +/* { dg-final { scan-assembler-times "packw" 1 } } */ +/* { dg-final { scan-assembler-times "brev8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c new file mode 100644 index 00000000000..aae588e6933 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbkc -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include + +int32_t foo1(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_clmul(rs1, rs2); +} + +int32_t foo2(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_clmulh(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c new file mode 100644 index 00000000000..3cb9ff711f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkc64.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbkc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_clmul(rs1, rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_clmulh(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c new file mode 100644 index 00000000000..dc3161bc494 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkx32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbkx -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int32_t foo3(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_xperm8(rs1, rs2); +} + +int32_t foo4(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_xperm4(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "xperm8" 1 } } */ +/* { dg-final { scan-assembler-times "xperm4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c new file mode 100644 index 00000000000..dbf3407cca4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkx64.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbkx -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_xperm8(rs1, rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_xperm4(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "xperm8" 1 } } */ +/* { dg-final { scan-assembler-times "xperm4" 1 } } */ From patchwork Mon Feb 20 07:01:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 59354 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1231876wrn; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id dy17-20020a05640231f100b004ad7c7c307bsi2010626edb.567.2023.02.20.02.29.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 02:29:02 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9D3543AA9910 for ; Mon, 20 Feb 2023 10:16:35 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 197893858409 for ; Mon, 20 Feb 2023 10:15:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 197893858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowABHoNfVGvNjlPdOBg--.59272S5; Mon, 20 Feb 2023 15:01:42 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Liao Shihua Subject: [PATCH V3 3/5] RISC-V: Implement ZKND and ZKNE extensions Date: Mon, 20 Feb 2023 15:01:23 +0800 Message-Id: <20230220070125.2291-4-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230220070125.2291-1-shihua@iscas.ac.cn> References: <20230220070125.2291-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABHoNfVGvNjlPdOBg--.59272S5 X-Coremail-Antispam: 1UD129KBjvAXoW3tr4ftFW5uw45KFy8JFWUJwb_yoW8JFy8Zo ZYgF1kJr4fWF1I9ws3ua13Ww1DXa4vyr45Xa90qFW5tan5Jrn5Kr15Ka1rCas7trs7XF1U Zan7uFs7ZFWku3s3n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYm7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r1rM28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr 0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUHmhwUUUUU= X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiAwkIEWPy4r6aogAAsm X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758345499557468110?= X-GMAIL-MSGID: =?utf-8?q?1758345499557468110?= This patch supports Zkne and Zknd extension. It includes instruction's machine description and built-in funtions. gcc/ChangeLog: * config/riscv/constraints.md (D03): Add constants of bs and rnum. (DsA): * config/riscv/crypto.md (riscv_aes32dsi): Add ZKND's and ZKNE's instructions. (riscv_aes32dsmi): (riscv_aes64ds): (riscv_aes64dsm): (riscv_aes64im): (riscv_aes64ks1i): (riscv_aes64ks2): (riscv_aes32esi): (riscv_aes32esmi): (riscv_aes64es): (riscv_aes64esm): * config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL. * config/riscv/riscv-scalar-crypto.def (DIRECT_BUILTIN): Add ZKND's and ZKNE's built-in functions. gcc/testsuite/ChangeLog: * gcc.target/riscv/zknd32.c: New test. * gcc.target/riscv/zknd64.c: New test. * gcc.target/riscv/zkne32.c: New test. * gcc.target/riscv/zkne64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/constraints.md | 8 ++ gcc/config/riscv/crypto.md | 121 +++++++++++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 5 + gcc/config/riscv/riscv-scalar-crypto.def | 15 +++ gcc/testsuite/gcc.target/riscv/zknd32.c | 18 ++++ gcc/testsuite/gcc.target/riscv/zknd64.c | 36 +++++++ gcc/testsuite/gcc.target/riscv/zkne32.c | 18 ++++ gcc/testsuite/gcc.target/riscv/zkne64.c | 30 ++++++ 8 files changed, 251 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 3637380ee47..3f46f14b10f 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -83,6 +83,14 @@ (and (match_code "const_int") (match_test "SINGLE_BIT_MASK_OPERAND (~ival)"))) +(define_constraint "D03" + "0, 1, 2 or 3 immediate" + (match_test "IN_RANGE (ival, 0, 3)")) + +(define_constraint "DsA" + "0 - 10 immediate" + (match_test "IN_RANGE (ival, 0, 10)")) + ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is ;; not available in RV32. (define_constraint "G" diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index a270036e39b..7568466ec97 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -33,6 +33,21 @@ ;; Zbkx unspecs UNSPEC_XPERM8 UNSPEC_XPERM4 + + ;; Zknd unspecs + UNSPEC_AES_DSI + UNSPEC_AES_DSMI + UNSPEC_AES_DS + UNSPEC_AES_DSM + UNSPEC_AES_IM + UNSPEC_AES_KS1I + UNSPEC_AES_KS2 + + ;; Zkne unspecs + UNSPEC_AES_ES + UNSPEC_AES_ESM + UNSPEC_AES_ESI + UNSPEC_AES_ESMI ]) ;; ZBKB extension @@ -126,3 +141,109 @@ "TARGET_ZBKX" "xperm8\t%0,%1,%2" [(set_attr "type" "crypto")]) + +;; ZKND extension + +(define_insn "riscv_aes32dsi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_DSI))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes32dsmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_DSMI))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsmi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64ds" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DS))] + "TARGET_ZKND && TARGET_64BIT" + "aes64ds\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64dsm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DSM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64dsm\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64im" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_AES_IM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64im\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64ks1i" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "DsA")] + UNSPEC_AES_KS1I))] + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" + "aes64ks1i\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64ks2" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_KS2))] + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" + "aes64ks2\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +;; ZKNE extension + +(define_insn "riscv_aes32esi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_ESI))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes32esmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_ESMI))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esmi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64es" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ES))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64es\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64esm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ESM))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64esm\t%0,%1,%2" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index f0d60709c7d..6632009734b 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -106,6 +106,11 @@ AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT) AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT) AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT) AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT) +AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT) +AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT) +AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT) +AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT) +AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def index e4c97acbc05..fe1a4e13d2d 100644 --- a/gcc/config/riscv/riscv-scalar-crypto.def +++ b/gcc/config/riscv/riscv-scalar-crypto.def @@ -43,3 +43,18 @@ RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), + +// ZKND +DIRECT_BUILTIN (aes32dsi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32), +DIRECT_BUILTIN (aes32dsmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32), +DIRECT_BUILTIN (aes64ds, RISCV_DI_FTYPE_DI_DI, crypto_zknd64), +DIRECT_BUILTIN (aes64dsm, RISCV_DI_FTYPE_DI_DI, crypto_zknd64), +DIRECT_BUILTIN (aes64im, RISCV_DI_FTYPE_DI, crypto_zknd64), +DIRECT_BUILTIN (aes64ks1i, RISCV_DI_FTYPE_DI_SI, crypto_zkne_or_zknd), +DIRECT_BUILTIN (aes64ks2, RISCV_DI_FTYPE_DI_DI, crypto_zkne_or_zknd), + +// ZKNE +DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), +DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), +DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), +DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), diff --git a/gcc/testsuite/gcc.target/riscv/zknd32.c b/gcc/testsuite/gcc.target/riscv/zknd32.c new file mode 100644 index 00000000000..203e3337d2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknd32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zknd -mabi=ilp32d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int32_t foo1(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_aes32dsi(rs1,rs2,bs); +} + +int32_t foo2(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_aes32dsmi(rs1,rs2,bs); +} + +/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */ +/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.target/riscv/zknd64.c new file mode 100644 index 00000000000..396c512fd3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknd64.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zknd -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64ds(rs1,rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64dsm(rs1,rs2); +} + +int64_t foo3(int64_t rs1, int rnum) +{ + return __builtin_riscv_aes64ks1i(rs1,rnum); +} + +int64_t foo4(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64ks2(rs1,rs2); +} + +int64_t foo5(int64_t rs1) +{ + return __builtin_riscv_aes64im(rs1); +} + +/* { dg-final { scan-assembler-times "aes64ds\t" 1 } } */ +/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */ +/* { dg-final { scan-assembler-times "aes64im" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zkne32.c b/gcc/testsuite/gcc.target/riscv/zkne32.c new file mode 100644 index 00000000000..b3bf984a140 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zkne32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zkne -mabi=ilp32d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int32_t foo1(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_aes32esi(rs1, rs2, bs); +} + +int32_t foo2(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_aes32esmi(rs1, rs2, bs); +} + +/* { dg-final { scan-assembler-times "aes32esi" 1 } } */ +/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zkne64.c b/gcc/testsuite/gcc.target/riscv/zkne64.c new file mode 100644 index 00000000000..894bab44fb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zkne64.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zkne -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64es(rs1,rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64esm(rs1,rs2); +} + +int64_t foo3(int64_t rs1, int rnum) +{ + return __builtin_riscv_aes64ks1i(rs1,rnum); +} + +int64_t foo4(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64ks2(rs1,rs2); +} + +/* { dg-final { scan-assembler-times "aes64es\t" 1 } } */ +/* { dg-final { scan-assembler-times "aes64esm" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */ From patchwork Mon Feb 20 07:01:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 59356 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1232424wrn; Mon, 20 Feb 2023 02:30:37 -0800 (PST) X-Google-Smtp-Source: AK7set9Ek7F0cwnf9Qjx6FwZxpc+YX9cFuvTLLvXMcwqzmYOSW7ojDYEZWJH366R54dGIXwuYodK X-Received: by 2002:a17:907:7f23:b0:8b1:7de3:cfb4 with SMTP id qf35-20020a1709077f2300b008b17de3cfb4mr15136516ejc.4.1676889037670; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id e10-20020a170906748a00b008b138238f31si14824321ejl.970.2023.02.20.02.30.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 02:30:37 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1E85F384DD2B for ; Mon, 20 Feb 2023 10:17:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 1C1D13858414 for ; Mon, 20 Feb 2023 10:15:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1C1D13858414 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowABHoNfVGvNjlPdOBg--.59272S6; Mon, 20 Feb 2023 15:01:43 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Liao Shihua Subject: [PATCH V3 4/5] RISC-V: Implement ZKNH extension Date: Mon, 20 Feb 2023 15:01:24 +0800 Message-Id: <20230220070125.2291-5-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230220070125.2291-1-shihua@iscas.ac.cn> References: <20230220070125.2291-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABHoNfVGvNjlPdOBg--.59272S6 X-Coremail-Antispam: 1UD129KBjvAXoW3CrW3JF1fZF1fAF1UXw13urg_yoW8JFyfWo Z5Krn5WF1fJFyIkFsxuw4ag3s8X3WkAr1kXan0qayFyan5Jrn5CwnYyan8C3sYyw17XF15 Zws7WFs7WaykCwn5n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYd7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r 4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxGrw CFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE 14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2 IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxK x2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI 0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JU-o7_UUUUU= X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiAw4IEWPy4r6aowAAsg X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758345599576454244?= X-GMAIL-MSGID: =?utf-8?q?1758345599576454244?= This patch supports Zknh extension. It includes instruction's machine description and built-in funtions. gcc/ChangeLog: * config/riscv/crypto.md (riscv_sha256sig0_): Add ZKNH's instructions. (riscv_sha256sig1_): (riscv_sha256sum0_): (riscv_sha256sum1_): (riscv_sha512sig0h): (riscv_sha512sig0l): (riscv_sha512sig1h): (riscv_sha512sig1l): (riscv_sha512sum0r): (riscv_sha512sum1r): (riscv_sha512sig0): (riscv_sha512sig1): (riscv_sha512sum0): (riscv_sha512sum1): * config/riscv/riscv-builtins.cc (AVAIL): And ZKNH's AVAIL. * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): And ZKNH's built-in functions. (DIRECT_BUILTIN): gcc/testsuite/ChangeLog: * gcc.target/riscv/zknh-sha256.c: New test. * gcc.target/riscv/zknh-sha512-32.c: New test. * gcc.target/riscv/zknh-sha512-64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/crypto.md | 138 ++++++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 2 + gcc/config/riscv/riscv-scalar-crypto.def | 22 +++ gcc/testsuite/gcc.target/riscv/zknh-sha256.c | 28 ++++ .../gcc.target/riscv/zknh-sha512-32.c | 42 ++++++ .../gcc.target/riscv/zknh-sha512-64.c | 31 ++++ 6 files changed, 263 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index 7568466ec97..17e7440c0b5 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -48,6 +48,22 @@ UNSPEC_AES_ESM UNSPEC_AES_ESI UNSPEC_AES_ESMI + + ;; Zknh unspecs + UNSPEC_SHA_256_SIG0 + UNSPEC_SHA_256_SIG1 + UNSPEC_SHA_256_SUM0 + UNSPEC_SHA_256_SUM1 + UNSPEC_SHA_512_SIG0 + UNSPEC_SHA_512_SIG0H + UNSPEC_SHA_512_SIG0L + UNSPEC_SHA_512_SIG1 + UNSPEC_SHA_512_SIG1H + UNSPEC_SHA_512_SIG1L + UNSPEC_SHA_512_SUM0 + UNSPEC_SHA_512_SUM0R + UNSPEC_SHA_512_SUM1 + UNSPEC_SHA_512_SUM1R ]) ;; ZBKB extension @@ -247,3 +263,125 @@ "TARGET_ZKNE && TARGET_64BIT" "aes64esm\t%0,%1,%2" [(set_attr "type" "crypto")]) + +;; ZKNH - SHA256 + +(define_insn "riscv_sha256sig0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG0))] + "TARGET_ZKNH" + "sha256sig0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sig1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG1))] + "TARGET_ZKNH" + "sha256sig1\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM0))] + "TARGET_ZKNH" + "sha256sum0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM1))] + "TARGET_ZKNH" + "sha256sum1\t%0,%1" + [(set_attr "type" "crypto")]) + +;; ZKNH - SHA512 + +(define_insn "riscv_sha512sig0h" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0h\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig0l" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0l\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig1h" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG1H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig1h\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig1l" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG1L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig1l\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum0r" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SUM0R))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sum0r\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum1r" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SUM1R))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sum1r\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig0" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SIG0))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sig0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig1" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SIG1))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sig1\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum0" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SUM0))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sum0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum1" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SUM1))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sum1\t%0,%1" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 6632009734b..ab5bd52ee7f 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -111,6 +111,8 @@ AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT) AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT) AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT) AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT) +AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT) +AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def index fe1a4e13d2d..d38aad122e5 100644 --- a/gcc/config/riscv/riscv-scalar-crypto.def +++ b/gcc/config/riscv/riscv-scalar-crypto.def @@ -58,3 +58,25 @@ DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), + +// ZKNH +RISCV_BUILTIN (sha256sig0_si, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sig0_di, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), +RISCV_BUILTIN (sha256sig1_si, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sig1_di, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), +RISCV_BUILTIN (sha256sum0_si, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sum0_di, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), +RISCV_BUILTIN (sha256sum1_si, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sum1_di, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), + +DIRECT_BUILTIN (sha512sig0h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sig0l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sig1h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sig1l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sum0r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sum1r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), + +DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64), +DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64), +DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64), +DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64), diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256.c b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c new file mode 100644 index 00000000000..54329aa6af2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +long foo1(long rs1) +{ + return __builtin_riscv_sha256sig0(rs1); +} + +long foo2(long rs1) +{ + return __builtin_riscv_sha256sig1(rs1); +} + +long foo3(long rs1) +{ + return __builtin_riscv_sha256sum0(rs1); +} + +long foo4(long rs1) +{ + return __builtin_riscv_sha256sum1(rs1); +} + +/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */ +/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */ +/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */ +/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c new file mode 100644 index 00000000000..eff9978922e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zknh -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int32_t foo1(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_sha512sig0h(rs1,rs2); +} + +int32_t foo2(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_sha512sig0l(rs1,rs2); +} + +int32_t foo3(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_sha512sig1h(rs1,rs2); +} + +int32_t foo4(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_sha512sig1l(rs1,rs2); +} + +int32_t foo5(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_sha512sum0r(rs1,rs2); +} + +int32_t foo6(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_sha512sum1r(rs1,rs2); +} + +/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c new file mode 100644 index 00000000000..53cbd302b3c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int64_t foo1(int64_t rs1) +{ + return __builtin_riscv_sha512sig0(rs1); +} + +int64_t foo2(int64_t rs1) +{ + return __builtin_riscv_sha512sig1(rs1); +} + +int64_t foo3(int64_t rs1) +{ + return __builtin_riscv_sha512sum0(rs1); +} + +int64_t foo4(int64_t rs1) +{ + return __builtin_riscv_sha512sum1(rs1); +} + + +/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum1" 1 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[8.43.85.97]) by mx.google.com with ESMTPS id 20-20020a17090600d400b008d34401e9b6si3089732eji.327.2023.02.20.02.27.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 02:27:28 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 55E383953809 for ; Mon, 20 Feb 2023 10:16:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 07C5E3858C74 for ; Mon, 20 Feb 2023 10:15:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 07C5E3858C74 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowABHoNfVGvNjlPdOBg--.59272S7; Mon, 20 Feb 2023 15:01:43 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Liao Shihua Subject: [PATCH V3 5/5] RISC-V: Implement ZKSH and ZKSED extensions Date: Mon, 20 Feb 2023 15:01:25 +0800 Message-Id: <20230220070125.2291-6-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230220070125.2291-1-shihua@iscas.ac.cn> References: <20230220070125.2291-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABHoNfVGvNjlPdOBg--.59272S7 X-Coremail-Antispam: 1UD129KBjvJXoW3Jw1xWw48Cr1xAryUtr4xWFg_yoW3tFyDpa ykGw4UCFy8XFs3G3WSqFyrJryrAws7G3y5u3sruw4qy3yUtrWktFn2kr1IyrW5JF45Cr1a ka13ua1Y9w12q3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9G14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48JMx C20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAF wI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20x vE14v26r4j6ryUMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v2 0xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxV W8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjLvKUUUUUU== X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiBwEIEWPy4dOfgwAAsg X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758345402019807886?= X-GMAIL-MSGID: =?utf-8?q?1758345402019807886?= This patch supports Zksh and Zksed extension. It includes instruction's machine description and built-in funtions. gcc/ChangeLog: * config/riscv/crypto.md (riscv_sm3p0_): Add ZKSED's and ZKSH's instructions. (riscv_sm3p1_): (riscv_sm4ed_): (riscv_sm4ks_): * config/riscv/riscv-builtins.cc (AVAIL): Add ZKSED's and ZKSH's AVAIL. * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): Add ZKSED's and ZKSH's built-in functions. gcc/testsuite/ChangeLog: * gcc.target/riscv/zksed32.c: New test. * gcc.target/riscv/zksed64.c: New test. * gcc.target/riscv/zksh32.c: New test. * gcc.target/riscv/zksh64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/crypto.md | 48 ++++++++++++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 4 ++ gcc/config/riscv/riscv-scalar-crypto.def | 12 ++++++ gcc/testsuite/gcc.target/riscv/zksed32.c | 19 ++++++++++ gcc/testsuite/gcc.target/riscv/zksed64.c | 19 ++++++++++ gcc/testsuite/gcc.target/riscv/zksh32.c | 19 ++++++++++ gcc/testsuite/gcc.target/riscv/zksh64.c | 19 ++++++++++ 7 files changed, 140 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zksed32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zksed64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index 17e7440c0b5..777aa529005 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -64,6 +64,14 @@ UNSPEC_SHA_512_SUM0R UNSPEC_SHA_512_SUM1 UNSPEC_SHA_512_SUM1R + + ;; Zksh unspecs + UNSPEC_SM3_P0 + UNSPEC_SM3_P1 + + ;; Zksed unspecs + UNSPEC_SM4_ED + UNSPEC_SM4_KS ]) ;; ZBKB extension @@ -385,3 +393,43 @@ "TARGET_ZKNH && TARGET_64BIT" "sha512sum1\t%0,%1" [(set_attr "type" "crypto")]) + + ;; ZKSH + +(define_insn "riscv_sm3p0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SM3_P0))] + "TARGET_ZKSH" + "sm3p0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sm3p1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SM3_P1))] + "TARGET_ZKSH" + "sm3p1\t%0,%1" + [(set_attr "type" "crypto")]) + +;; ZKSED + +(define_insn "riscv_sm4ed_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_SM4_ED))] + "TARGET_ZKSED" + "sm4ed\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sm4ks_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_SM4_KS))] + "TARGET_ZKSED" + "sm4ks\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index ab5bd52ee7f..390f8a38309 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -113,6 +113,10 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT) AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT) AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT) AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT) +AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT) +AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT) +AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT) +AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def index d38aad122e5..139793c6360 100644 --- a/gcc/config/riscv/riscv-scalar-crypto.def +++ b/gcc/config/riscv/riscv-scalar-crypto.def @@ -80,3 +80,15 @@ DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64), DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64), DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64), DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64), + +// ZKSH +RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32), +RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64), +RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32), +RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64), + +// ZKSED +RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32), +RISCV_BUILTIN (sm4ed_di, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64), +RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32), +RISCV_BUILTIN (sm4ks_di, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64), diff --git a/gcc/testsuite/gcc.target/riscv/zksed32.c b/gcc/testsuite/gcc.target/riscv/zksed32.c new file mode 100644 index 00000000000..38c7ef5a62b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zksed32.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zksed -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int32_t foo1(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_sm4ks(rs1,rs2,bs); +} + +int32_t foo2(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_sm4ed(rs1,rs2,bs); +} + + +/* { dg-final { scan-assembler-times "sm4ks" 1 } } */ +/* { dg-final { scan-assembler-times "sm4ed" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksed64.c b/gcc/testsuite/gcc.target/riscv/zksed64.c new file mode 100644 index 00000000000..323d4fe1070 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zksed64.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zksed -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int64_t foo1(int64_t rs1, int64_t rs2, int bs) +{ + return __builtin_riscv_sm4ks(rs1,rs2,bs); +} + +int64_t foo2(int64_t rs1, int64_t rs2, int bs) +{ + return __builtin_riscv_sm4ed(rs1,rs2,bs); +} + + +/* { dg-final { scan-assembler-times "sm4ks" 1 } } */ +/* { dg-final { scan-assembler-times "sm4ed" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksh32.c b/gcc/testsuite/gcc.target/riscv/zksh32.c new file mode 100644 index 00000000000..edbabd8cdb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zksh32.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zksh -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int32_t foo1(int32_t rs1) +{ + return __builtin_riscv_sm3p0(rs1); +} + +int32_t foo2(int32_t rs1) +{ + return __builtin_riscv_sm3p1(rs1); +} + + +/* { dg-final { scan-assembler-times "sm3p0" 1 } } */ +/* { dg-final { scan-assembler-times "sm3p1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zksh64.c b/gcc/testsuite/gcc.target/riscv/zksh64.c new file mode 100644 index 00000000000..832a9557880 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zksh64.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zksh -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int64_t foo1(int64_t rs1) +{ + return __builtin_riscv_sm3p0(rs1); +} + +int64_t foo2(int64_t rs1) +{ + return __builtin_riscv_sm3p1(rs1); +} + + +/* { dg-final { scan-assembler-times "sm3p0" 1 } } */ +/* { dg-final { scan-assembler-times "sm3p1" 1 } } */