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[8.43.85.97]) by mx.google.com with ESMTPS id bf18-20020a170906c51200b0084cd1ecf33csi4240048ejb.739.2023.02.17.06.04.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 06:04:50 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=WoUzwv93; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 373DB385B523 for ; Fri, 17 Feb 2023 14:03:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 373DB385B523 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676642620; bh=34SQiUiUD0LuDMpRav3/fx8LWXHwtQ3B2jLWZ78gIc0=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=WoUzwv93i0wEmS4/IsmlaqnBHJqdQdUG6npFm89ivn2wSOB0B35F6L4x4ikAh+sCe XgGDjM6KFMuy9D535h35ZdqinIZjqq2IDfsTM+5kurfXqqKruVJd/rMX77Oq0etCYT LqUc9mhFanMgjaf+DvJesUl2H9BytPShMohrKEDc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by sourceware.org (Postfix) with ESMTPS id 3728E382E6B8 for ; Fri, 17 Feb 2023 14:02:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3728E382E6B8 Received: by mail-lj1-x234.google.com with SMTP id r12so1255894ljg.4 for ; Fri, 17 Feb 2023 06:02:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=zswTCrXvuW6W+Lp7x9N1DMCkM6CD9lA5ZzYLjQrbzBE=; b=7H9INxNckzk0j6AjR0MOpNaU6yBcXgjxW/fdKCZ4RC8Qppowh5FR8lBMO2Knr/sgum CbPm1NtUqWVJidEQ+yFgDb9eDGO5w3KGvVo/mn/laXCBFsuNv+d01ayguOPyDSw4u6sk w7W9WAKBUlbQFXqFsRR9FzK8xQRyDiRJzna6AzSk0fnj3bMgChZ+Lz5qSQUUHKTtleC3 7feTW/txSzkrYjZbzbH0G2v8rMCMwPny7MFnMl9cG/wRCjUhMHE1iX5i+lUc+KAaIE/B uA+vE/M+nCNd9u/csU94uciBYokVWi7VJVKYQezGY1HNnXAocey2NyQR1oS13KoqF0Pv iMoA== X-Gm-Message-State: AO0yUKXNPQDiWR76S+icxmT9RrAZqeU/c+xbu4ZShI0WZdLAp4NQi5w/ oezzPiZmG+oxpjUUPxD4lLck9kwNy8qXt9ycu8Tg6XX3dDvw/A== X-Received: by 2002:a05:651c:39e:b0:294:6de5:e63b with SMTP id e30-20020a05651c039e00b002946de5e63bmr1238181ljp.7.1676642571720; Fri, 17 Feb 2023 06:02:51 -0800 (PST) MIME-Version: 1.0 Date: Fri, 17 Feb 2023 18:02:40 +0400 Message-ID: Subject: RISC-V: Add divmod instruction support To: gcc-patches@gcc.gnu.org X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, HTML_MESSAGE, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Matevos Mehrabyan via Gcc-patches From: Matevos Mehrabyan Reply-To: Matevos Mehrabyan Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758087285856488094?= X-GMAIL-MSGID: =?utf-8?q?1758087285856488094?= Hi all, If we have division and remainder calculations with the same operands: a = b / c; d = b % c; We can replace the calculation of remainder with multiplication + subtraction, using the result from the previous division: a = b / c; d = a * c; d = b - d; Which will be faster. Currently, it isn't done for RISC-V. I've added an expander for DIVMOD which replaces 'rem' with 'mul + sub'. Best regards, Matevos. gcc/ChangeLog: * config/riscv/riscv.md: Added divmod expander. gcc/testsuite/ChangeLog: * gcc.target/riscv/divmod.c: New testcase. --- inline copy of the patch --- diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index f95dd405e12..d941483d9f1 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -148,6 +148,11 @@ ;; from the same template. (define_code_iterator any_mod [mod umod]) +;; These code iterators allow unsigned and signed divmod to be generated +;; from the same template. +(define_code_iterator only_div [div udiv]) +(define_code_attr paired_mod [(div "mod") (udiv "umod")]) + ;; These code iterators allow the signed and unsigned scc operations to use ;; the same template. (define_code_iterator any_gt [gt gtu]) @@ -175,7 +180,8 @@ (gt "") (gtu "u") (ge "") (geu "u") (lt "") (ltu "u") - (le "") (leu "u")]) + (le "") (leu "u") + (div "") (udiv "u")]) ;; is like , but the signed form expands to "s" rather than "". (define_code_attr su [(sign_extend "s") (zero_extend "u")]) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c8adc5af5d2..2d48ff3f8de 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1044,6 +1044,22 @@ [(set_attr "type" "idiv") (set_attr "mode" "DI")]) +(define_expand "divmod4" + [(parallel + [(set (match_operand:GPR 0 "register_operand") + (only_div:GPR (match_operand:GPR 1 "register_operand") + (match_operand:GPR 2 "register_operand"))) + (set (match_operand:GPR 3 "register_operand") + (:GPR (match_dup 1) (match_dup 2)))])] + "TARGET_DIV" + { + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_div3 (operands[0], operands[1], operands[2])); + emit_insn (gen_mul3 (tmp, operands[0], operands[2])); + emit_insn (gen_sub3 (operands[3], operands[1], tmp)); + DONE; + }) + (define_insn "*si3_extended" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI diff --git a/gcc/testsuite/gcc.target/riscv/divmod.c b/gcc/testsuite/gcc.target/riscv/divmod.c new file mode 100644 index 00000000000..254b25e654d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/divmod.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + +void +foo(int a, int b, int *c, int *d) +{ + *c = a / b; + *d = a % b; +} + +/* { dg-final { scan-assembler-not "rem" } } */ +/* { dg-final { scan-assembler-times "mul" 1 } } */ +/* { dg-final { scan-assembler-times "sub" 1 } } */