From patchwork Thu Feb 16 07:50:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 57900 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp165844wrn; Wed, 15 Feb 2023 23:51:15 -0800 (PST) X-Google-Smtp-Source: AK7set+l7lRNYgqyIhfEB2ik7ppp863AbrHYiE0mKHdzYcIlSXm6jtJESgCWm+gmqQlgri+DwaSW X-Received: by 2002:a17:906:3588:b0:8b1:2d1e:d53b with SMTP id o8-20020a170906358800b008b12d1ed53bmr3690327ejb.70.1676533875678; Wed, 15 Feb 2023 23:51:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676533875; cv=none; d=google.com; s=arc-20160816; b=kXL1HvR9sGYbd5LN+oZ6vSwCop9nmqiJfWfM1RhcnvlE9mZBKyHyUN9YXcbTFJA9G1 5DNNt6sNxDwqTu1mvEYY9ExsIkJR6GVPtyIfZoHQAY3z9KOGM8L64AsKMwuARXY/nGTm UxrqrhfXdYXdTICfVDF+SxpYlRkLngX1IEgQH4m2vbkEmZhxB2JVqokcGumNHugbbsit 83JVgR+FfnGQ712dFkIdGSjFsIJvlo8ZNw2LbfOZO7T0JsgfQiJ/V6lIt2j94UNwR1EY kE9Sev9addPShbVm+sjVnkt3MUhfKfVFG/nZqmgaJ1vCvdhlCCSndJo5WtreZoRm4Kmj 4kVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=G8uyw0srTkrLfGx1EJEbjVC1A+fXsM0M9k8ra205lEw=; b=LYiqkJnkYixM5mYakR0h25r3ghhKITp4KFRKK0wR8uqdMi8XmeekuQoFH1loSQwE3W VNKPkw0HFWxvonG1hd10nErh9ffr6CbTADS5C+OsMxDWq5xQaSEtTeiyXLrmTf4eYSTs /XfaN9cseQHHypJmTaK8e3l9BveXmclhWrWHhX/xhyxzhMf6MiaAvIBhEQ0eDJspglIm KPS1l6JcyN0GJjQ9GzaoXMexTUydqT7Q4TOUmCQh/sbs+hAd6bZ95Y/6UxEPJRBiqjkm Dv/Ptc+t8EI/isXRhuqVgsMLvzsNCDR9/t3BXkDl+k9G2RnyiCTKvAW3QdB+cn1ywOgy dUig== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id 17-20020a170906029100b008b13f0a8621si1587579ejf.675.2023.02.15.23.51.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 23:51:15 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D85B4383FBAC for ; Thu, 16 Feb 2023 07:50:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 48ECA3858D33 for ; Thu, 16 Feb 2023 07:50:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 48ECA3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowAAXG0c54O1jP3dbBQ--.9892S3; Thu, 16 Feb 2023 15:50:19 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: jiawei@iscas.ac.cn, kito.cheng@gmail.com, mjos@iki.fi, palmer@dabbelt.com, shiyulong@iscas.ac.cn, ben.marshall@pqshield.com, christoph.muellner@vrull.eu, Liao Shihua Subject: [PATCH V2 1/5] Add prototypes for RISC-V Crypto built-in functions Date: Thu, 16 Feb 2023 15:50:01 +0800 Message-Id: <20230216075005.2600-2-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230216075005.2600-1-shihua@iscas.ac.cn> References: <20230216075005.2600-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAAXG0c54O1jP3dbBQ--.9892S3 X-Coremail-Antispam: 1UD129KBjvJXoWxuF4UWr13Zr4DKryftw1kKrg_yoW5Ar1kpa 18Kan5Crn5G3ZrGw4xtF1rtr4ft39ag3y5JwsxZF43AFW7WryvqF1qqa1UWw1DuF4UGw1j 934rKFyF9r4Ykr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9C14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j6rxd M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48JMx C20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAF wI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20x vE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxK x2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI 0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUHyIUUUUUU= X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCQ0EEWPt2tcTOgAAs7 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757973185156867285?= X-GMAIL-MSGID: =?utf-8?q?1757973185156867285?= gcc/ChangeLog: * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New enumeration identifier. (RISCV_FTYPE_NAME3): Likewise. (RISCV_ATYPE_QI): New Argument types. (RISCV_ATYPE_HI): Likewise. (RISCV_FTYPE_ATYPES2): New RISCV_ATYPE. (RISCV_FTYPE_ATYPES3): Likewise. * config/riscv/riscv-ftypes.def (2): New Definitions of prototypes. (3):Likewise Co-Authored-By: SiYu Wu --- gcc/config/riscv/riscv-builtins.cc | 8 ++++++++ gcc/config/riscv/riscv-ftypes.def | 10 ++++++++++ 2 files changed, 18 insertions(+) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 25ca407f9a9..ded91e17554 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -42,6 +42,8 @@ along with GCC; see the file COPYING3. If not see /* Macros to create an enumeration identifier for a function prototype. */ #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B +#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C +#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D /* Classifies the prototype of a built-in function. */ enum riscv_function_type { @@ -132,6 +134,8 @@ AVAIL (always, (!0)) /* Argument types. */ #define RISCV_ATYPE_VOID void_type_node #define RISCV_ATYPE_USI unsigned_intSI_type_node +#define RISCV_ATYPE_QI intQI_type_node +#define RISCV_ATYPE_HI intHI_type_node #define RISCV_ATYPE_SI intSI_type_node #define RISCV_ATYPE_DI intDI_type_node #define RISCV_ATYPE_VOID_PTR ptr_type_node @@ -142,6 +146,10 @@ AVAIL (always, (!0)) RISCV_ATYPE_##A #define RISCV_FTYPE_ATYPES1(A, B) \ RISCV_ATYPE_##A, RISCV_ATYPE_##B +#define RISCV_FTYPE_ATYPES2(A, B, C) \ + RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C +#define RISCV_FTYPE_ATYPES3(A, B, C, D) \ + RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D static const struct riscv_builtin_description riscv_builtins[] = { #include "riscv-cmo.def" diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 3a40c33e7c2..3b518195a29 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -32,3 +32,13 @@ DEF_RISCV_FTYPE (1, (VOID, USI)) DEF_RISCV_FTYPE (1, (VOID, VOID_PTR)) DEF_RISCV_FTYPE (1, (SI, SI)) DEF_RISCV_FTYPE (1, (DI, DI)) +DEF_RISCV_FTYPE (2, (SI, QI, QI)) +DEF_RISCV_FTYPE (2, (SI, HI, HI)) +DEF_RISCV_FTYPE (2, (SI, SI, SI)) +DEF_RISCV_FTYPE (2, (DI, QI, QI)) +DEF_RISCV_FTYPE (2, (DI, HI, HI)) +DEF_RISCV_FTYPE (2, (DI, SI, SI)) +DEF_RISCV_FTYPE (2, (DI, DI, SI)) +DEF_RISCV_FTYPE (2, (DI, DI, DI)) +DEF_RISCV_FTYPE (3, (SI, SI, SI, SI)) +DEF_RISCV_FTYPE (3, (DI, DI, DI, SI)) From patchwork Thu Feb 16 07:50:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 57904 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp166647wrn; Wed, 15 Feb 2023 23:53:52 -0800 (PST) X-Google-Smtp-Source: AK7set+Pe+28XwZz5H8eG2UoA4W5v7YYJFQ/E8GbHRL+Om5WmmEnuhGL16jIbYltnpOQjabeH2fv X-Received: by 2002:a05:6402:b3c:b0:4ac:b431:4762 with SMTP id bo28-20020a0564020b3c00b004acb4314762mr4824602edb.23.1676534032734; Wed, 15 Feb 2023 23:53:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676534032; cv=none; d=google.com; s=arc-20160816; b=HNx6vdeuTC3fcfClzjwfwF3ZEaTft5ulg2kNkBkNhVf5WG7x46C+1VDwNVoLwZdjH7 e7OBUhkdmP3uVe3Lrry62R1wpk6KsRwTj6qhBWR+USGxJQlQQdANmGHta4UgEtpMuZYw tycDGnaf3izI34Ljb7ksrcm1auHt8sax79eIoxJ17UkPz4QEa996HRlKJ054L/GbYEmb XxG/oGxUZ3/NFCJ5J5dz+1TLwe0K79s7GDCcQC8g3HmzGyaDUqr4FGo5fp2+j8IvDc3f 9l/44VPOSBzKK08yx/kCGn1iSvEV8h3NVd5MJuWqBoBbUmCcOuPT010RmjFfupl+KKrS Tu2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=LRK3l88XBagt2mVQ72FPEJ/IC6zjR1Lx48kGz9gTq6Y=; b=QBSHB2qLpwT0KzbrmZbe5hoiEiHt/qGZoxTozVDUWvMVM+on4gkvLQFeqEQDkWov59 526t2cRXrVJ6WE3g80DiOGb2qcgL4w/KyKV3Ww58ysR8rcn+w6XE7ICCyM9B4pJQfoYP ESx1YnYUsTJ/ngVjp+/8qeitvWIdarV5VEm/xvYS446QP0bQchIorIfsP4NS6unQFSP1 4/tuerBUMDQZ64VA/3cPzrxyEYO7FpTGWiJyewqwy5qCmaxCSQF3vjE9O864jZOLrYRC UW4/RRkq4FptnDw1RmhaYijKvVQ6PDqJxdGkIRIjXOq3/JbIGI7ZggL531wjv2rKYnXF 5WRQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d16-20020aa7d5d0000000b004acbea7f4f7si1409963eds.570.2023.02.15.23.53.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 23:53:52 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 361343885C14 for ; Thu, 16 Feb 2023 07:52:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 70D2B385840D for ; Thu, 16 Feb 2023 07:50:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 70D2B385840D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowAAXG0c54O1jP3dbBQ--.9892S4; Thu, 16 Feb 2023 15:50:19 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: jiawei@iscas.ac.cn, kito.cheng@gmail.com, mjos@iki.fi, palmer@dabbelt.com, shiyulong@iscas.ac.cn, ben.marshall@pqshield.com, christoph.muellner@vrull.eu, Liao Shihua Subject: [PATCH V2 2/5] Implement ZBKB, ZBKC and ZBKX extensions Date: Thu, 16 Feb 2023 15:50:02 +0800 Message-Id: <20230216075005.2600-3-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230216075005.2600-1-shihua@iscas.ac.cn> References: <20230216075005.2600-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAAXG0c54O1jP3dbBQ--.9892S4 X-Coremail-Antispam: 1UD129KBjvAXoWfCFyrWFWUtryUCw15AFy7Jrb_yoW5JF47Zo Z3trs5AF4rGFyI9ws09w4fXrnrXF1jyr4rXa90qrWrt3Z5Jr1Fkw1a9an8Aasaqr1xXFyU Za97uan7XFWkWas3n29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOU7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4UJVW0 owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxVWUtV W8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v2 6r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2 Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_ Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJw CI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUvcSsGvfC2KfnxnUUI43ZEXa7VUjpuWJUU UUU== X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiBwAEEWPt1e4i-QAAs4 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757973349754699274?= X-GMAIL-MSGID: =?utf-8?q?1757973349754699274?= This patch support Zkbk, Zbkc and Zkbx extension. It includes instruction's machine description, built-in funtion, and intrinsics. It is worth mentioning that this patch only adds instructions in Zbkb but no longer in Zbb. If any instructions both in Zbb and Zbkb, they will be generated by code generator instead of built-in functions and intrinsics. gcc/ChangeLog: * config.gcc: Add intrinsics header in extra_headers. * config/riscv/bitmanip.md: Add TARGET_ZBKB if these instructions are included in ZBKB extension. * config/riscv/riscv-builtins.cc (AVAIL): Add ZBKB's,ZBKC's,ZBKX's AVAIL. * config/riscv/riscv.md: include crypto.md. * config/riscv/crypto.md: Scalar Cryptography Machine description file. * config/riscv/riscv-crypto.def: Scalar Cryptography built-in function file. * config/riscv/riscv_scalar_crypto.h: Scalar Cryptography intrinsics header. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbkb32.c: New test. * gcc.target/riscv/zbkb64.c: New test. * gcc.target/riscv/zbkc32.c: New test. * gcc.target/riscv/zbkc64.c: New test. * gcc.target/riscv/zbkx32.c: New test. * gcc.target/riscv/zbkx64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config.gcc | 2 +- gcc/config/riscv/bitmanip.md | 20 ++-- gcc/config/riscv/crypto.md | 130 ++++++++++++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 7 ++ gcc/config/riscv/riscv-crypto.def | 45 ++++++++ gcc/config/riscv/riscv.md | 4 +- gcc/config/riscv/riscv_scalar_crypto.h | 104 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zbkb32.c | 36 +++++++ gcc/testsuite/gcc.target/riscv/zbkb64.c | 28 +++++ gcc/testsuite/gcc.target/riscv/zbkc32.c | 17 ++++ gcc/testsuite/gcc.target/riscv/zbkc64.c | 17 ++++ gcc/testsuite/gcc.target/riscv/zbkx32.c | 18 ++++ gcc/testsuite/gcc.target/riscv/zbkx64.c | 18 ++++ 13 files changed, 434 insertions(+), 12 deletions(-) create mode 100644 gcc/config/riscv/crypto.md create mode 100644 gcc/config/riscv/riscv-crypto.def create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c diff --git a/gcc/config.gcc b/gcc/config.gcc index f0958e1c959..951b92b2028 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -532,7 +532,7 @@ riscv*) extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o" extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o" d_target_objs="riscv-d.o" - extra_headers="riscv_vector.h" + extra_headers="riscv_vector.h riscv_scalar_crypto.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h" ;; diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 14d18edbe62..f076ba35832 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -189,7 +189,7 @@ [(set (match_operand:X 0 "register_operand" "=r") (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r")) (match_operand:X 2 "register_operand" "r")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "n\t%0,%2,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) @@ -203,7 +203,7 @@ (const_int 0))) (match_operand:DI 2 "register_operand"))) (clobber (match_operand:DI 3 "register_operand"))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63))) (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))]) @@ -211,7 +211,7 @@ [(set (match_operand:X 0 "register_operand" "=r") (not:X (xor:X (match_operand:X 1 "register_operand" "r") (match_operand:X 2 "register_operand" "r"))))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "xnor\t%0,%1,%2" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) @@ -277,7 +277,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -285,7 +285,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (rotatert:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "ror%i2\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -293,7 +293,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r"))))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "rorw\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -301,7 +301,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "rol%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -309,7 +309,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (rotate:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "rol\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -317,7 +317,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r"))))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "rolw\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -332,7 +332,7 @@ (define_insn "bswap2" [(set (match_operand:X 0 "register_operand" "=r") (bswap:X (match_operand:X 1 "register_operand" "r")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "rev8\t%0,%1" [(set_attr "type" "bitmanip")]) diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md new file mode 100644 index 00000000000..6792f19ed68 --- /dev/null +++ b/gcc/config/riscv/crypto.md @@ -0,0 +1,130 @@ +;; Machine description for RISC-V Scalar Cryptography extensions. +;; Copyright (C) 2023 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_c_enum "unspec" [ + ;; ZBKB unspecs + UNSPEC_BREV8 + UNSPEC_ZIP + UNSPEC_UNZIP + UNSPEC_PACK + UNSPEC_PACKH + UNSPEC_PACKW + + ;; ZBKC unspecs + UNSPEC_CLMUL + UNSPEC_CLMULH + + ;; ZBKX unspecs + UNSPEC_XPERM8 + UNSPEC_XPERM4 + + +]) + +;; ZBKB extension +(define_insn "riscv_brev8_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_BREV8))] + "TARGET_ZBKB" + "brev8\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_zip" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_ZIP))] + "TARGET_ZBKB && !TARGET_64BIT" + "zip\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_unzip" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_UNZIP))] + "TARGET_ZBKB && !TARGET_64BIT" + "unzip\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_pack_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:HISI 1 "register_operand" "r") + (match_operand:HISI 2 "register_operand" "r")] + UNSPEC_PACK))] + "TARGET_ZBKB" + "pack\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_packh_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:QI 1 "register_operand" "r") + (match_operand:QI 2 "register_operand" "r")] + UNSPEC_PACKH))] + "TARGET_ZBKB" + "packh\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_packw" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:HI 1 "register_operand" "r") + (match_operand:HI 2 "register_operand" "r")] + UNSPEC_PACKW))] + "TARGET_ZBKB && TARGET_64BIT" + "packw\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +;; ZBKC extension + +(define_insn "riscv_clmul_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMUL))] + "TARGET_ZBKC" + "clmul\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_clmulh_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMULH))] + "TARGET_ZBKC" + "clmulh\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +;; ZBKX extension + +(define_insn "riscv_xperm4_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_XPERM4))] + "TARGET_ZBKX" + "xperm4\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_xperm8_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_XPERM8))] + "TARGET_ZBKX" + "xperm8\t%0,%1,%2" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index ded91e17554..e9c2d92f0d3 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -100,6 +100,12 @@ AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT) AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT) AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) +AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT) +AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT) +AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT) +AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT) +AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT) +AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. @@ -152,6 +158,7 @@ AVAIL (always, (!0)) RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D static const struct riscv_builtin_description riscv_builtins[] = { + #include "riscv-crypto.def" #include "riscv-cmo.def" DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def new file mode 100644 index 00000000000..ebb82629296 --- /dev/null +++ b/gcc/config/riscv/riscv-crypto.def @@ -0,0 +1,45 @@ +/* Builtin functions for RISC-V Scalar Cryptography extensions. + Copyright (C) 2023 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +// ZBKB +RISCV_BUILTIN (pack_sihi, "pack", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_HI_HI, crypto_zbkb32), +RISCV_BUILTIN (pack_disi, "pack", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_SI_SI, crypto_zbkb64), + +RISCV_BUILTIN (packh_si, "packh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_QI_QI, crypto_zbkb32), +RISCV_BUILTIN (packh_di, "packh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_QI_QI, crypto_zbkb64), + +RISCV_BUILTIN (packw, "packw", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_HI_HI, crypto_zbkb64), + +RISCV_BUILTIN (zip, "zip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), +RISCV_BUILTIN (unzip, "unzip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), + +RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), +RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zbkb64), + +// ZBKC +RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32), +RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64), +RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32), +RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64), + +// ZBKX +RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), +RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), +RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), +RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c8adc5af5d2..c424a82dcbd 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -242,6 +242,7 @@ ;; bitmanip bit manipulation instructions ;; rotate rotation instructions ;; atomic atomic instructions +;; crypto cryptography instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read @@ -333,7 +334,7 @@ "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, - atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, + atomic,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, @@ -3092,3 +3093,4 @@ (include "generic.md") (include "sifive-7.md") (include "vector.md") +(include "crypto.md") diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h new file mode 100644 index 00000000000..2e2644fa323 --- /dev/null +++ b/gcc/config/riscv/riscv_scalar_crypto.h @@ -0,0 +1,104 @@ +/* RISC-V Scalar Cryptography Extension intrinsics include file. + Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _RISCV_SCALAR_CRYPTO_H +#define _RISCV_SCALAR_CRYPTO_H +#endif // _RISCV_SCALAR_CRYPTO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(__riscv_xlen) && !defined(RVKINTRIN_EMULATE) +#warning "Target is not RISC-V. Enabling insecure emulation." +#define RVKINTRIN_EMULATE 1 +#endif + +// intrinsics via compiler builtins +#include +#define _RVK_INTRIN_IMPL(s) __builtin_riscv_##s + + +// set type if not already set +#if !defined(RVKINTRIN_RV32) && !defined(RVKINTRIN_RV64) +#if __riscv_xlen == 32 +#define RVKINTRIN_RV32 +#elif __riscv_xlen == 64 +#define RVKINTRIN_RV64 +#else +#error "__riscv_xlen not valid." +#endif +#endif + +// Mappings to implementation + +// === (mapping) Zbkb: Bitmanipulation instructions for Cryptography + +#ifdef RVKINTRIN_RV32 +static inline int32_t __riscv_pack(int16_t rs1, int16_t rs2) + { return _RVK_INTRIN_IMPL(pack)(rs1, rs2); } // PACK + +static inline int32_t __riscv_packh(int8_t rs1, int8_t rs2) + { return _RVK_INTRIN_IMPL(packh)(rs1, rs2); } // PACKH +#endif + +#ifdef RVKINTRIN_RV64 +static inline int64_t __riscv_pack(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(pack)(rs1, rs2); } // PACK + +static inline int64_t __riscv_packh(int8_t rs1, int8_t rs2) + { return _RVK_INTRIN_IMPL(packh)(rs1, rs2); } // PACKH + +static inline int64_t __riscv_packw(int16_t rs1, int16_t rs2) + { return _RVK_INTRIN_IMPL(packw)(rs1, rs2); } // PACKW + +#endif + +static inline long __riscv_brev8(long rs1) + { return _RVK_INTRIN_IMPL(brev8)(rs1); } // BREV8 (GREVI) + +#ifdef RVKINTRIN_RV32 +static inline int32_t __riscv_zip(int32_t rs1) + { return _RVK_INTRIN_IMPL(zip_32)(rs1); } // ZIP (SHFLI) + +static inline int32_t __riscv_unzip(int32_t rs1) + { return _RVK_INTRIN_IMPL(unzip_32)(rs1); } // UNZIP (UNSHFLI) +#endif + +// === (mapping) Zbkc: Carry-less multiply instructions + +static inline long __riscv_clmul(long rs1, long rs2) + { return _RVK_INTRIN_IMPL(clmul)(rs1, rs2); } // CLMUL + +static inline long __riscv_clmulh(long rs1, long rs2) + { return _RVK_INTRIN_IMPL(clmulh)(rs1, rs2); } // CLMULH + +// === (mapping) Zbkx: Crossbar permutation instructions + + +static inline long __riscv_xperm8(long rs1, long rs2) + { return _RVK_INTRIN_IMPL(xperm8_64)(rs1, rs2); } // XPERM8 + +static inline long __riscv_xperm4(long rs1, long rs2) + { return _RVK_INTRIN_IMPL(xperm4_64)(rs1, rs2); } // XPERM4 diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c new file mode 100644 index 00000000000..c37492ae32b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_scalar_crypto.h" + +int32_t foo1(int16_t rs1, int16_t rs2) +{ + return __riscv_pack(rs1, rs2); +} + +int32_t foo2(int8_t rs1, int8_t rs2) +{ + return __riscv_packh(rs1, rs2); +} + +int32_t foo3(int32_t rs1) +{ + return __riscv_brev8(rs1); +} + +int32_t foo4(int32_t rs1) +{ + return __riscv_zip(rs1); +} + +int32_t foo5(int32_t rs1) +{ + return __riscv_unzip(rs1); +} + +/* { dg-final { scan-assembler-times "pack\t" 1 } } */ +/* { dg-final { scan-assembler-times "packh" 1 } } */ +/* { dg-final { scan-assembler-times "brev8" 1 } } */ +/* { dg-final { scan-assembler-times "zip" 2 } } */ +/* { dg-final { scan-assembler-times "unzip" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c new file mode 100644 index 00000000000..e7771f73394 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include "riscv_scalar_crypto.h" + +int64_t foo1(int32_t rs1, int32_t rs2) +{ + return __riscv_pack(rs1, rs2); +} + +int64_t foo2(int8_t rs1, int8_t rs2) +{ + return __riscv_packh(rs1, rs2); +} + +int64_t foo3(int16_t rs1, int16_t rs2) +{ + return __riscv_packw(rs1, rs2); +} + +int64_t foo4(int64_t rs1, int64_t rs2) +{ + return __riscv_brev8(rs1); +} +/* { dg-final { scan-assembler-times "pack\t" 1 } } */ +/* { dg-final { scan-assembler-times "packh" 1 } } */ +/* { dg-final { scan-assembler-times "packw" 1 } } */ +/* { dg-final { scan-assembler-times "brev8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c new file mode 100644 index 00000000000..13b09f2879b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbkc -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include "riscv_scalar_crypto.h" + +int32_t foo1(int32_t rs1, int32_t rs2) +{ + return __riscv_clmul(rs1, rs2); +} + +int32_t foo2(int32_t rs1, int32_t rs2) +{ + return __riscv_clmulh(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c new file mode 100644 index 00000000000..6493a83c57a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkc64.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbkc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include "riscv_scalar_crypto.h" + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __riscv_clmul(rs1, rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __riscv_clmulh(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c new file mode 100644 index 00000000000..426cce88425 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkx32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbkx -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_scalar_crypto.h" + +int32_t foo3(int32_t rs1, int32_t rs2) +{ + return __riscv_xperm8(rs1, rs2); +} + +int32_t foo4(int32_t rs1, int32_t rs2) +{ + return __riscv_xperm4(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "xperm8" 1 } } */ +/* { dg-final { scan-assembler-times "xperm4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c new file mode 100644 index 00000000000..7bc09bd77be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkx64.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbkx -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_scalar_crypto.h" + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __riscv_xperm8(rs1, rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __riscv_xperm4(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "xperm8" 1 } } */ +/* { dg-final { scan-assembler-times "xperm4" 1 } } */ From patchwork Thu Feb 16 07:50:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 57902 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp166200wrn; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id n17-20020a17090673d100b00877a6da8f41si978532ejl.722.2023.02.15.23.52.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 23:52:29 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1B4B8385800A for ; Thu, 16 Feb 2023 07:51:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id D5B6C3858C5F for ; Thu, 16 Feb 2023 07:50:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D5B6C3858C5F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowAAXG0c54O1jP3dbBQ--.9892S5; Thu, 16 Feb 2023 15:50:20 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: jiawei@iscas.ac.cn, kito.cheng@gmail.com, mjos@iki.fi, palmer@dabbelt.com, shiyulong@iscas.ac.cn, ben.marshall@pqshield.com, christoph.muellner@vrull.eu, Liao Shihua Subject: [PATCH V2 3/5] Implement ZKND and ZKNE extensions Date: Thu, 16 Feb 2023 15:50:03 +0800 Message-Id: <20230216075005.2600-4-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230216075005.2600-1-shihua@iscas.ac.cn> References: <20230216075005.2600-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAAXG0c54O1jP3dbBQ--.9892S5 X-Coremail-Antispam: 1UD129KBjvAXoWfXr15Xry7JrW3KF1UAFW7twb_yoW8Xw4UCo ZYgFn5JF4fGF1I9wsI9w4fGr1DXFyvyr45Xa9YgrW5tan5Jrn5Kr1Ykan8uas7twsrXFy8 X3Z7uF4xAFWkC3s3n29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOU7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r1rM28IrcIa0x kI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4UJVW0 owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxVWUtV W8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v2 6r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2 Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_ Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJw CI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUvcSsGvfC2KfnxnUUI43ZEXa7VU1sYFtUU UUU== X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiBwUEEWPt1e4jCQAAsI X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757973262746049554?= X-GMAIL-MSGID: =?utf-8?q?1757973262746049554?= This patch support Zkne and Zknd extension. It includes instruction's machine description, built-in funtion, and intrinsics. gcc/ChangeLog: * config/riscv/constraints.md (D03): New constraints of bs. (DsA):New constraints of rnum. * config/riscv/crypto.md (riscv_aes32dsi):Add ZKND,ZKNE instructions. (riscv_aes32dsmi): Likewise. (riscv_aes64ds): Likewise. (riscv_aes64dsm): Likewise. (riscv_aes64im): Likewise. (riscv_aes64ks1i): Likewise. (riscv_aes64ks2): Likewise. (riscv_aes32esi): Likewise. (riscv_aes32esmi): Likewise. (riscv_aes64es): Likewise. (riscv_aes64esm): Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL. * config/riscv/riscv-crypto.def (DIRECT_BUILTIN):Add ZKND's and ZKNE's built-in functions. * config/riscv/riscv_scalar_crypto.h (__riscv_aes32dsi):Add ZKND's and ZKNE's intrinsics. (__riscv_aes32dsmi): Likewise. (__riscv_aes64ds): Likewise. (__riscv_aes64dsm): Likewise. (__riscv_aes64im): Likewise. (__riscv_aes64ks1i): Likewise. (__riscv_aes64ks2): Likewise. (__riscv_aes32esi): Likewise. (__riscv_aes32esmi): Likewise. (__riscv_aes64es): Likewise. (__riscv_aes64esm): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/zknd32.c: New test. * gcc.target/riscv/zknd64.c: New test. * gcc.target/riscv/zkne32.c: New test. * gcc.target/riscv/zkne64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/constraints.md | 8 ++ gcc/config/riscv/crypto.md | 121 +++++++++++++++++++++++- gcc/config/riscv/riscv-builtins.cc | 5 + gcc/config/riscv/riscv-crypto.def | 15 +++ gcc/config/riscv/riscv_scalar_crypto.h | 46 +++++++++ gcc/testsuite/gcc.target/riscv/zknd32.c | 18 ++++ gcc/testsuite/gcc.target/riscv/zknd64.c | 36 +++++++ gcc/testsuite/gcc.target/riscv/zkne32.c | 18 ++++ gcc/testsuite/gcc.target/riscv/zkne64.c | 30 ++++++ 9 files changed, 296 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 3637380ee47..3f46f14b10f 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -83,6 +83,14 @@ (and (match_code "const_int") (match_test "SINGLE_BIT_MASK_OPERAND (~ival)"))) +(define_constraint "D03" + "0, 1, 2 or 3 immediate" + (match_test "IN_RANGE (ival, 0, 3)")) + +(define_constraint "DsA" + "0 - 10 immediate" + (match_test "IN_RANGE (ival, 0, 10)")) + ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is ;; not available in RV32. (define_constraint "G" diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index 6792f19ed68..d76a872775f 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -34,7 +34,20 @@ UNSPEC_XPERM8 UNSPEC_XPERM4 - + ;; ZKND unspecs + UNSPEC_AES_DSI + UNSPEC_AES_DSMI + UNSPEC_AES_DS + UNSPEC_AES_DSM + UNSPEC_AES_IM + UNSPEC_AES_KS1I + UNSPEC_AES_KS2 + + ;; ZKNE unspecs + UNSPEC_AES_ES + UNSPEC_AES_ESM + UNSPEC_AES_ESI + UNSPEC_AES_ESMI ]) ;; ZBKB extension @@ -128,3 +141,109 @@ "TARGET_ZBKX" "xperm8\t%0,%1,%2" [(set_attr "type" "crypto")]) + +;; ZKND extension + +(define_insn "riscv_aes32dsi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_DSI))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes32dsmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_DSMI))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsmi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64ds" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DS))] + "TARGET_ZKND && TARGET_64BIT" + "aes64ds\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64dsm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DSM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64dsm\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64im" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_AES_IM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64im\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64ks1i" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "DsA")] + UNSPEC_AES_KS1I))] + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" + "aes64ks1i\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64ks2" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_KS2))] + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" + "aes64ks2\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +;; ZKNE extension + +(define_insn "riscv_aes32esi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_ESI))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes32esmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_ESMI))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esmi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64es" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ES))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64es\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64esm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ESM))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64esm\t%0,%1,%2" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index e9c2d92f0d3..b92619f99e4 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -106,6 +106,11 @@ AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT) AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT) AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT) AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT) +AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT) +AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT) +AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT) +AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT) +AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def index ebb82629296..57d031c2e09 100644 --- a/gcc/config/riscv/riscv-crypto.def +++ b/gcc/config/riscv/riscv-crypto.def @@ -43,3 +43,18 @@ RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), + +// ZKND +DIRECT_BUILTIN (aes32dsi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32), +DIRECT_BUILTIN (aes32dsmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32), +DIRECT_BUILTIN (aes64ds, RISCV_DI_FTYPE_DI_DI, crypto_zknd64), +DIRECT_BUILTIN (aes64dsm, RISCV_DI_FTYPE_DI_DI, crypto_zknd64), +DIRECT_BUILTIN (aes64im, RISCV_DI_FTYPE_DI, crypto_zknd64), +DIRECT_BUILTIN (aes64ks1i, RISCV_DI_FTYPE_DI_SI, crypto_zkne_or_zknd), +DIRECT_BUILTIN (aes64ks2, RISCV_DI_FTYPE_DI_DI, crypto_zkne_or_zknd), + +// ZKNE +DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), +DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), +DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), +DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h index 2e2644fa323..3418bcf5774 100644 --- a/gcc/config/riscv/riscv_scalar_crypto.h +++ b/gcc/config/riscv/riscv_scalar_crypto.h @@ -102,3 +102,49 @@ static inline long __riscv_xperm8(long rs1, long rs2) static inline long __riscv_xperm4(long rs1, long rs2) { return _RVK_INTRIN_IMPL(xperm4_64)(rs1, rs2); } // XPERM4 + + +// === (mapping) Zknd: NIST Suite: AES Decryption + +#ifdef RVKINTRIN_RV32 +static inline int32_t __riscv_aes32dsi(int32_t rs1, int32_t rs2, int bs) + { return _RVK_INTRIN_IMPL(aes32dsi)(rs1, rs2, bs); } // AES32DSI + +static inline int32_t __riscv_aes32dsmi(int32_t rs1, int32_t rs2, int bs) + { return _RVK_INTRIN_IMPL(aes32dsmi)(rs1, rs2, bs); } // AES32DSMI +#endif + +#ifdef RVKINTRIN_RV64 +static inline int64_t __riscv_aes64ds(int64_t rs1, int64_t rs2) + { return _RVK_INTRIN_IMPL(aes64ds)(rs1, rs2); } // AES64DS + +static inline int64_t __riscv_aes64dsm(int64_t rs1, int64_t rs2) + { return _RVK_INTRIN_IMPL(aes64dsm)(rs1, rs2); } // AES64DSM + +static inline int64_t __riscv_aes64im(int64_t rs1) + { return _RVK_INTRIN_IMPL(aes64im)(rs1); } // AES64IM + +static inline int64_t __riscv_aes64ks1i(int64_t rs1, int rnum) + { return _RVK_INTRIN_IMPL(aes64ks1i)(rs1, rnum); } // AES64KS1I + +static inline int64_t __riscv_aes64ks2(int64_t rs1, int64_t rs2) + { return _RVK_INTRIN_IMPL(aes64ks2)(rs1, rs2); } // AES64KS2 +#endif + +// === (mapping) Zkne: NIST Suite: AES Encryption + +#ifdef RVKINTRIN_RV32 +static inline int32_t __riscv_aes32esi(int32_t rs1, int32_t rs2, int bs) + { return _RVK_INTRIN_IMPL(aes32esi)(rs1, rs2, bs); } // AES32ESI + +static inline int32_t __riscv_aes32esmi(int32_t rs1, int32_t rs2, int bs) + { return _RVK_INTRIN_IMPL(aes32esmi)(rs1, rs2, bs); } // AES32ESMI +#endif + +#ifdef RVKINTRIN_RV64 +static inline int64_t __riscv_aes64es(int64_t rs1, int64_t rs2) + { return _RVK_INTRIN_IMPL(aes64es)(rs1, rs2); } // AES64ES + +static inline int64_t __riscv_aes64esm(int64_t rs1, int64_t rs2) + { return _RVK_INTRIN_IMPL(aes64esm)(rs1, rs2); } // AES64ESM +#endif diff --git a/gcc/testsuite/gcc.target/riscv/zknd32.c b/gcc/testsuite/gcc.target/riscv/zknd32.c new file mode 100644 index 00000000000..b7bde2bb20d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknd32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zknd -mabi=ilp32d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_scalar_crypto.h" + +int32_t foo1(int32_t rs1, int32_t rs2, int bs) +{ + return __riscv_aes32dsi(rs1,rs2,bs); +} + +int32_t foo2(int32_t rs1, int32_t rs2, int bs) +{ + return __riscv_aes32dsmi(rs1,rs2,bs); +} + +/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */ +/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.target/riscv/zknd64.c new file mode 100644 index 00000000000..8ad3c55341c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknd64.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zknd -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __riscv_aes64ds(rs1,rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __riscv_aes64dsm(rs1,rs2); +} + +int64_t foo3(int64_t rs1, int rnum) +{ + return __riscv_aes64ks1i(rs1,rnum); +} + +int64_t foo4(int64_t rs1, int64_t rs2) +{ + return __riscv_aes64ks2(rs1,rs2); +} + +int64_t foo5(int64_t rs1) +{ + return __riscv_aes64im(rs1); +} + +/* { dg-final { scan-assembler-times "aes64ds\t" 1 } } */ +/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */ +/* { dg-final { scan-assembler-times "aes64im" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zkne32.c b/gcc/testsuite/gcc.target/riscv/zkne32.c new file mode 100644 index 00000000000..48a1dda8a3e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zkne32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zkne -mabi=ilp32d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_scalar_crypto.h" + +int32_t foo1(int32_t rs1, int32_t rs2, int bs) +{ + return __riscv_aes32esi(rs1, rs2, bs); +} + +int32_t foo2(int32_t rs1, int32_t rs2, int bs) +{ + return __riscv_aes32esmi(rs1, rs2, bs); +} + +/* { dg-final { scan-assembler-times "aes32esi" 1 } } */ +/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zkne64.c b/gcc/testsuite/gcc.target/riscv/zkne64.c new file mode 100644 index 00000000000..6d5be92f666 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zkne64.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zkne -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __riscv_aes64es(rs1,rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __riscv_aes64esm(rs1,rs2); +} + +int64_t foo3(int64_t rs1, int rnum) +{ + return __riscv_aes64ks1i(rs1,rnum); +} + +int64_t foo4(int64_t rs1, int64_t rs2) +{ + return __riscv_aes64ks2(rs1,rs2); +} + +/* { dg-final { scan-assembler-times "aes64es\t" 1 } } */ +/* { dg-final { scan-assembler-times "aes64esm" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */ From patchwork Thu Feb 16 07:50:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 57903 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp166500wrn; Wed, 15 Feb 2023 23:53:25 -0800 (PST) X-Google-Smtp-Source: AK7set9F7HpL27vYGpuvbXU4k/XlsWtyfeDFjufT0quqcTZyMxiIMRTqMty1ZCDDJdnHAXP9SRKX X-Received: by 2002:a50:ec90:0:b0:4ac:bda5:5f66 with SMTP id e16-20020a50ec90000000b004acbda55f66mr4581917edr.6.1676534005222; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id by3-20020a0564021b0300b004a2593fcbedsi1484575edb.94.2023.02.15.23.53.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 23:53:25 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 238863882FC6 for ; Thu, 16 Feb 2023 07:51:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 87ABA3858414 for ; Thu, 16 Feb 2023 07:50:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 87ABA3858414 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowAAXG0c54O1jP3dbBQ--.9892S6; Thu, 16 Feb 2023 15:50:20 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: jiawei@iscas.ac.cn, kito.cheng@gmail.com, mjos@iki.fi, palmer@dabbelt.com, shiyulong@iscas.ac.cn, ben.marshall@pqshield.com, christoph.muellner@vrull.eu, Liao Shihua Subject: [PATCH V2 4/5] Implement ZKNH extensions Date: Thu, 16 Feb 2023 15:50:04 +0800 Message-Id: <20230216075005.2600-5-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230216075005.2600-1-shihua@iscas.ac.cn> References: <20230216075005.2600-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAAXG0c54O1jP3dbBQ--.9892S6 X-Coremail-Antispam: 1UD129KBjvAXoWfXr18Kw1kXw17CrW5Gr13XFb_yoW8WrWrCo ZYgrn5XF1fJF1S9FsIkw13K3s8XF1kArn5Xa98tayFyF4rJrn5CrnYkan8Ca4vy3y7JFy5 Zws7uF4xAayUCwn5n29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUO87AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4UJV WxJr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVWx Jr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx 0E2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWU JVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7CjxVAaw2AFwI 0_Jw0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG 67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MI IYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E 14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr 0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUW MKtUUUUU= X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCQwEEWPt2tcTQgAAsC X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757973320828711191?= X-GMAIL-MSGID: =?utf-8?q?1757973320828711191?= This patch support Zknh extension. It includes instruction's machine description, built-in funtion, and intrinsics. gcc/ChangeLog: * config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's instructions. (riscv_sha256sig1_): Likewise. (riscv_sha256sum0_): Likewise. (riscv_sha256sum1_): Likewise. (riscv_sha512sig0h): Likewise. (riscv_sha512sig0l): Likewise. (riscv_sha512sig1h): Likewise. (riscv_sha512sig1l): Likewise. (riscv_sha512sum0r): Likewise. (riscv_sha512sum1r): Likewise. (riscv_sha512sig0): Likewise. (riscv_sha512sig1): Likewise. (riscv_sha512sum0): Likewise. (riscv_sha512sum1): Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Add ZKNH's AVAIL. * config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKNH's built-in functions. (DIRECT_BUILTIN): Likewise. * config/riscv/riscv_scalar_crypto.h (__riscv_sha256sig0): Add ZKNH's intrinsics. (__riscv_sha256sig1): Likewise. (__riscv_sha256sum0): Likewise. (__riscv_sha256sum1): Likewise. (__riscv_sha512sig0h): Likewise. (__riscv_sha512sig0l): Likewise. (__riscv_sha512sig1h): Likewise. (__riscv_sha512sig1l): Likewise. (__riscv_sha512sum0r): Likewise. (__riscv_sha512sum1r): Likewise. (__riscv_sha512sig0): Likewise. (__riscv_sha512sig1): Likewise. (__riscv_sha512sum0): Likewise. (__riscv_sha512sum1): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/zknh-sha256.c: New test. * gcc.target/riscv/zknh-sha512-32.c: New test. * gcc.target/riscv/zknh-sha512-64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/crypto.md | 138 ++++++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 2 + gcc/config/riscv/riscv-crypto.def | 22 +++ gcc/config/riscv/riscv_scalar_crypto.h | 48 ++++++ gcc/testsuite/gcc.target/riscv/zknh-sha256.c | 29 ++++ .../gcc.target/riscv/zknh-sha512-32.c | 43 ++++++ .../gcc.target/riscv/zknh-sha512-64.c | 31 ++++ 7 files changed, 313 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index d76a872775f..063a8025f20 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -48,6 +48,22 @@ UNSPEC_AES_ESM UNSPEC_AES_ESI UNSPEC_AES_ESMI + + ;; ZKNH unspecs + UNSPEC_SHA_256_SIG0 + UNSPEC_SHA_256_SIG1 + UNSPEC_SHA_256_SUM0 + UNSPEC_SHA_256_SUM1 + UNSPEC_SHA_512_SIG0 + UNSPEC_SHA_512_SIG0H + UNSPEC_SHA_512_SIG0L + UNSPEC_SHA_512_SIG1 + UNSPEC_SHA_512_SIG1H + UNSPEC_SHA_512_SIG1L + UNSPEC_SHA_512_SUM0 + UNSPEC_SHA_512_SUM0R + UNSPEC_SHA_512_SUM1 + UNSPEC_SHA_512_SUM1R ]) ;; ZBKB extension @@ -247,3 +263,125 @@ "TARGET_ZKNE && TARGET_64BIT" "aes64esm\t%0,%1,%2" [(set_attr "type" "crypto")]) + +;; ZKNH - SHA256 + +(define_insn "riscv_sha256sig0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG0))] + "TARGET_ZKNH" + "sha256sig0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sig1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG1))] + "TARGET_ZKNH" + "sha256sig1\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM0))] + "TARGET_ZKNH" + "sha256sum0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM1))] + "TARGET_ZKNH" + "sha256sum1\t%0,%1" + [(set_attr "type" "crypto")]) + +;; ZKNH - SHA512 + +(define_insn "riscv_sha512sig0h" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0h\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig0l" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0l\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig1h" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG1H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig1h\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig1l" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG1L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig1l\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum0r" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SUM0R))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sum0r\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum1r" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SUM1R))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sum1r\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig0" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SIG0))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sig0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig1" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SIG1))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sig1\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum0" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SUM0))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sum0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum1" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SUM1))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sum1\t%0,%1" + [(set_attr "type" "crypto")]) \ No newline at end of file diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index b92619f99e4..2a35167e6fb 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -111,6 +111,8 @@ AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT) AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT) AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT) AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT) +AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT) +AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def index 57d031c2e09..831ab8c0d01 100644 --- a/gcc/config/riscv/riscv-crypto.def +++ b/gcc/config/riscv/riscv-crypto.def @@ -58,3 +58,25 @@ DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), + +// ZKNH +RISCV_BUILTIN (sha256sig0_si, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sig0_di, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), +RISCV_BUILTIN (sha256sig1_si, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sig1_di, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), +RISCV_BUILTIN (sha256sum0_si, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sum0_di, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), +RISCV_BUILTIN (sha256sum1_si, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sum1_di, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), + +DIRECT_BUILTIN (sha512sig0h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sig0l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sig1h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sig1l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sum0r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sum1r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), + +DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64), +DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64), +DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64), +DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64), diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h index 3418bcf5774..06e73a0169b 100644 --- a/gcc/config/riscv/riscv_scalar_crypto.h +++ b/gcc/config/riscv/riscv_scalar_crypto.h @@ -148,3 +148,51 @@ static inline int64_t __riscv_aes64es(int64_t rs1, int64_t rs2) static inline int64_t __riscv_aes64esm(int64_t rs1, int64_t rs2) { return _RVK_INTRIN_IMPL(aes64esm)(rs1, rs2); } // AES64ESM #endif + +// === (mapping) Zknh: NIST Suite: Hash Function Instructions + +static inline long __riscv_sha256sig0(long rs1) + { return _RVK_INTRIN_IMPL(sha256sig0)(rs1); } // SHA256SIG0 + +static inline long __riscv_sha256sig1(long rs1) + { return _RVK_INTRIN_IMPL(sha256sig1)(rs1); } // SHA256SIG1 + +static inline long __riscv_sha256sum0(long rs1) + { return _RVK_INTRIN_IMPL(sha256sum0)(rs1); } // SHA256SUM0 + +static inline long __riscv_sha256sum1(long rs1) + { return _RVK_INTRIN_IMPL(sha256sum1)(rs1); } // SHA256SUM1 + +#ifdef RVKINTRIN_RV32 +static inline int32_t __riscv_sha512sig0h(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sig0h)(rs1, rs2); } // SHA512SIG0H + +static inline int32_t __riscv_sha512sig0l(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sig0l)(rs1, rs2); } // SHA512SIG0L + +static inline int32_t __riscv_sha512sig1h(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sig1h)(rs1, rs2); } // SHA512SIG1H + +static inline int32_t __riscv_sha512sig1l(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sig1l)(rs1, rs2); } // SHA512SIG1L + +static inline int32_t __riscv_sha512sum0r(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sum0r)(rs1, rs2); } // SHA512SUM0R + +static inline int32_t __riscv_sha512sum1r(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sum1r)(rs1, rs2); } // SHA512SUM1R +#endif + +#ifdef RVKINTRIN_RV64 +static inline int64_t __riscv_sha512sig0(int64_t rs1) + { return _RVK_INTRIN_IMPL(sha512sig0)(rs1); } // SHA512SIG0 + +static inline int64_t __riscv_sha512sig1(int64_t rs1) + { return _RVK_INTRIN_IMPL(sha512sig1)(rs1); } // SHA512SIG1 + +static inline int64_t __riscv_sha512sum0(int64_t rs1) + { return _RVK_INTRIN_IMPL(sha512sum0)(rs1); } // SHA512SUM0 + +static inline int64_t __riscv_sha512sum1(int64_t rs1) + { return _RVK_INTRIN_IMPL(sha512sum1)(rs1); } // SHA512SUM1 +#endif diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256.c b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c new file mode 100644 index 00000000000..88bf01eb279 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" +long foo1(long rs1) +{ + return __riscv_sha256sig0(rs1); +} + +long foo2(long rs1) +{ + return __riscv_sha256sig1(rs1); +} + +long foo3(long rs1) +{ + return __riscv_sha256sum0(rs1); +} + +long foo4(long rs1) +{ + return __riscv_sha256sum1(rs1); +} + +/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */ +/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */ +/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */ +/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c new file mode 100644 index 00000000000..dcea6ad1536 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zknh -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" + +int32_t foo1(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sig0h(rs1,rs2); +} + +int32_t foo2(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sig0l(rs1,rs2); +} + +int32_t foo3(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sig1h(rs1,rs2); +} + +int32_t foo4(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sig1l(rs1,rs2); +} + +int32_t foo5(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sum0r(rs1,rs2); +} + +int32_t foo6(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sum1r(rs1,rs2); +} + +/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c new file mode 100644 index 00000000000..ed87e1e93bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" + +int64_t foo1(int64_t rs1) +{ + return __riscv_sha512sig0(rs1); +} + +int64_t foo2(int64_t rs1) +{ + return __riscv_sha512sig1(rs1); +} + +int64_t foo3(int64_t rs1) +{ + return __riscv_sha512sum0(rs1); +} + +int64_t foo4(int64_t rs1) +{ + return __riscv_sha512sum1(rs1); +} + + +/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */ From patchwork Thu Feb 16 07:50:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 57901 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp165875wrn; Wed, 15 Feb 2023 23:51:22 -0800 (PST) X-Google-Smtp-Source: AK7set/Xg0qcLRKhLKW8zvjgKp/nle8/qcU5cQX3maQHqMf3ilBK+U/CtJd9afW8cf33b7oaX1FN X-Received: by 2002:a17:906:f151:b0:8aa:c090:a9ef with SMTP id gw17-20020a170906f15100b008aac090a9efmr4537324ejb.55.1676533882422; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ft31-20020a170907801f00b008b12f0f5d04si1158406ejc.276.2023.02.15.23.51.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 23:51:22 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 061CD38432C7 for ; Thu, 16 Feb 2023 07:50:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 3835C3858412 for ; Thu, 16 Feb 2023 07:50:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3835C3858412 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowAAXG0c54O1jP3dbBQ--.9892S7; Thu, 16 Feb 2023 15:50:21 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: jiawei@iscas.ac.cn, kito.cheng@gmail.com, mjos@iki.fi, palmer@dabbelt.com, shiyulong@iscas.ac.cn, ben.marshall@pqshield.com, christoph.muellner@vrull.eu, Liao Shihua Subject: [PATCH V2 5/5] Implement ZKSH and ZKSED extensions Date: Thu, 16 Feb 2023 15:50:05 +0800 Message-Id: <20230216075005.2600-6-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230216075005.2600-1-shihua@iscas.ac.cn> References: <20230216075005.2600-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAAXG0c54O1jP3dbBQ--.9892S7 X-Coremail-Antispam: 1UD129KBjvJXoW3AFW7WF1fGrW3ZF1UJw1kZrb_yoW3CFW7pa 98J3y5AFW8Xrs3Ga4SqF95J345A3s7Ww45ZasxurWDAayUJrZ7tFnFkw1Iv3yDXF15Cr1a kayFkFWj9r4jyw7anT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPI14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4U JVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxV WUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E 14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIx kGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAF wI0_Gr1j6F4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr 0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUW MKtUUUUU= X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCgwEEWPt2n8S7gAAsE X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757973192307961520?= X-GMAIL-MSGID: =?utf-8?q?1757973192307961520?= This patch support Zksh and Zksed extension. It includes instruction's machine description, built-in funtion, and intrinsics. gcc/ChangeLog: * config/riscv/crypto.md (riscv_sm3p0_): Add ZKSH's and ZKSED's instructions. (riscv_sm3p1_): Likewise. (riscv_sm4ed_): Likewise. (riscv_sm4ks_): Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Add ZKSH's and ZKSED's AVAIL. * config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKSH's and ZKSED's built-in functions. * config/riscv/riscv_scalar_crypto.h (__riscv_sm4ks): Add ZKSH's and ZKSED's intrinsics. (__riscv_sm4ed): Likewise. (__riscv_sm3p0): Likewise. (__riscv_sm3p1): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/zksed.c: New test. * gcc.target/riscv/zksh.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/crypto.md | 50 +++++++++++++++++++++++++- gcc/config/riscv/riscv-builtins.cc | 4 +++ gcc/config/riscv/riscv-crypto.def | 12 +++++++ gcc/config/riscv/riscv_scalar_crypto.h | 20 +++++++++++ gcc/testsuite/gcc.target/riscv/zksed.c | 20 +++++++++++ gcc/testsuite/gcc.target/riscv/zksh.c | 19 ++++++++++ 6 files changed, 124 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index 063a8025f20..e28bdd91078 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -64,6 +64,14 @@ UNSPEC_SHA_512_SUM0R UNSPEC_SHA_512_SUM1 UNSPEC_SHA_512_SUM1R + + ;; ZKSH unspecs + UNSPEC_SM3_P0 + UNSPEC_SM3_P1 + + ;; ZKSED unspecs + UNSPEC_SM4_ED + UNSPEC_SM4_KS ]) ;; ZBKB extension @@ -384,4 +392,44 @@ UNSPEC_SHA_512_SUM1))] "TARGET_ZKNH && TARGET_64BIT" "sha512sum1\t%0,%1" - [(set_attr "type" "crypto")]) \ No newline at end of file + [(set_attr "type" "crypto")]) + + ;; ZKSH + +(define_insn "riscv_sm3p0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SM3_P0))] + "TARGET_ZKSH" + "sm3p0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sm3p1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SM3_P1))] + "TARGET_ZKSH" + "sm3p1\t%0,%1" + [(set_attr "type" "crypto")]) + +;; ZKSED + +(define_insn "riscv_sm4ed_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_SM4_ED))] + "TARGET_ZKSED" + "sm4ed\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sm4ks_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_SM4_KS))] + "TARGET_ZKSED" + "sm4ks\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 2a35167e6fb..18c0cce6b8b 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -113,6 +113,10 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT) AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT) AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT) AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT) +AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT) +AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT) +AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT) +AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def index 831ab8c0d01..7774b801aec 100644 --- a/gcc/config/riscv/riscv-crypto.def +++ b/gcc/config/riscv/riscv-crypto.def @@ -80,3 +80,15 @@ DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64), DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64), DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64), DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64), + +// ZKSH +RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32), +RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64), +RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32), +RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64), + +// ZKSED +RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32), +RISCV_BUILTIN (sm4ed_di, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64), +RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32), +RISCV_BUILTIN (sm4ks_di, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64), diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h index 06e73a0169b..ba85483aa4a 100644 --- a/gcc/config/riscv/riscv_scalar_crypto.h +++ b/gcc/config/riscv/riscv_scalar_crypto.h @@ -196,3 +196,23 @@ static inline int64_t __riscv_sha512sum0(int64_t rs1) static inline int64_t __riscv_sha512sum1(int64_t rs1) { return _RVK_INTRIN_IMPL(sha512sum1)(rs1); } // SHA512SUM1 #endif + +// === (mapping) Zksed: ShangMi Suite: SM4 Block Cipher Instructions + +static inline long __riscv_sm4ks(long rs1, long rs2, int bs) + { return _RVK_INTRIN_IMPL(sm4ks)(rs1, rs2, bs); } // SM4KS + +static inline long __riscv_sm4ed(long rs1, long rs2, int bs) + { return _RVK_INTRIN_IMPL(sm4ed)(rs1, rs2, bs); } // SM4ED + +// === (mapping) Zksh: ShangMi Suite: SM3 Hash Function Instructions + +static inline long __riscv_sm3p0(long rs1) + { return _RVK_INTRIN_IMPL(sm3p0)(rs1); } // SM3P0 + +static inline long __riscv_sm3p1(long rs1) + { return _RVK_INTRIN_IMPL(sm3p1)(rs1); } // SM3P1 + +#ifdef __cplusplus +} +#endif diff --git a/gcc/testsuite/gcc.target/riscv/zksed.c b/gcc/testsuite/gcc.target/riscv/zksed.c new file mode 100644 index 00000000000..2c7a6ab4089 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zksed.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zksed -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" + +long foo1(long rs1, long rs2, int bs) +{ + return __riscv_sm4ks(rs1,rs2,bs); +} + +long foo2(long rs1, long rs2, int bs) +{ + return __riscv_sm4ed(rs1,rs2,bs); +} + + +/* { dg-final { scan-assembler-times "sm4ks" 1 } } */ +/* { dg-final { scan-assembler-times "sm4ed" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/zksh.c b/gcc/testsuite/gcc.target/riscv/zksh.c new file mode 100644 index 00000000000..79485c7f3a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zksh.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zksh -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" + +long foo1(long rs1) +{ + return __riscv_sm3p0(rs1); +} + +long foo2(long rs1) +{ + return __riscv_sm3p1(rs1); +} + + +/* { dg-final { scan-assembler-times "sm3p0" 1 } } */ +/* { dg-final { scan-assembler-times "sm3p1" 1 } } */