From patchwork Thu Feb 16 03:36:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 57829 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp84948wrn; Wed, 15 Feb 2023 19:37:24 -0800 (PST) X-Google-Smtp-Source: AK7set8xV/0QA/0BX8C7fuJBGUxnxnnaTOW7hlw8iF5IiC+T5smB+8CNzC/sKoaYV3WFXNNphrbO X-Received: by 2002:a17:906:8596:b0:870:58ae:842e with SMTP id v22-20020a170906859600b0087058ae842emr4915429ejx.24.1676518644294; Wed, 15 Feb 2023 19:37:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676518644; cv=none; d=google.com; s=arc-20160816; b=zKgKh0hJCbcnTqrLE+bbDW93TB/Vrps0Hv6k5nRGEc2/Zp7l89zB2p7cWuhzKjnGP7 bwNluc9Ay9lo/u1j3Ch1eLEAWzio97549cKsyagMsQ2yE+Zwk7Z3GElrjmPwdBz1IIAD UGVtgipEwBuLPJtO6Q2lgTYfR86fzbIKap6Tt4swZK/gzVdU4FmXUuf87Z+CtvhEGS6N MQh+2o9HOPbqTe3FjPoBJJUQFkkxfwmNSopcplbCNKlmAnfwpHwBfTWhr7eCGnu2GkvP EgmpboN8jDnMP/iOsRIVN5LB+Gvnui0nQ1kn4kKfKRiR9RjjARuxccP+x2OzSpu56Qia xg5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=uYfzesR47BxYrpccCgStWSPTEqtm9zLpYowvvPydZ9I=; b=PxSjXGZFnsolY588m9Ynd/y4eUZwVjD2Qzx3NJVaKVWJX9/oFoZybLWg2VEteNXXTG omLBdQ+EWQHaRvVs31Bju8Lkk+Oige7JZyN1WQmA5F7Iyv0EEIk41HXBzkT2zSdrrSqx lpSWxiOVwTKJ6xt3NuD8do1boxS6sti1L7DWx7uDVc6EjQC3d1fTxyloSJIfW3WBmM1Q uXnx5CFO7FOn8N8QgrTyAEydMYNca1ylrujdcLZ96NvoOpgRWTfgJtduDtcYCsQNjYiA MprXdFhCzVrg6hUoBYtI1eaSj7sy0NRMXIEONQHGnHIp4FfYEXAcMDNhelKXELBc3Pd+ Sf8A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id y29-20020a170906519d00b008b158cf675bsi641293ejk.798.2023.02.15.19.37.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 19:37:24 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EE6373857437 for ; Thu, 16 Feb 2023 03:37:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id 7978A3858D33 for ; Thu, 16 Feb 2023 03:36:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7978A3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp63t1676518580tjijlagv Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 16 Feb 2023 11:36:19 +0800 (CST) X-QQ-SSF: 01400000000000E0M000000A0000000 X-QQ-FEAT: vrqOr+ppv0stdMBePqz/3oOOItiBdZBHdwUcgk0Q8RTLoCI5UE3MK6tKMT7dV ymI6lmI6b50IA7RUlc1yd9lJzn8+FesbtQVi+6owg2EMqvV2wp7OoypGH17TWYIjXHWXZ5l XDabm/38enrdXQ8iReHd00H/UU8yIRpCfrf/tJo194q6J+4IwlUFYBIOQzTPeEONwpW0YUY sRmzBG00q1pk+DCvKnxqlI3AQYQnuWmooFpq3IFXK74el4Kcm9hkzyhJLVZ7n2qM/AzLsFU ckO9yqIrEgWSUVS1JSR98g5xVrQfBu2uLQdbt+ebZhQDRO3fZ9uLZ9IKVr1ZSo882Z9d2mC z16mLcVCps4Eg72TqhvT3+5i1fTB7IcwOGLTSi8rbCtg7ic6UK0+hK0q7VyRw== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vm* mask C api tests Date: Thu, 16 Feb 2023 11:36:19 +0800 Message-Id: <20230216033619.16472-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757957214044887874?= X-GMAIL-MSGID: =?utf-8?q?1757957214044887874?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vmand_mm-1.c: New test. * gcc.target/riscv/rvv/base/vmand_mm-2.c: New test. * gcc.target/riscv/rvv/base/vmand_mm-3.c: New test. * gcc.target/riscv/rvv/base/vmandn_mm-1.c: New test. * gcc.target/riscv/rvv/base/vmandn_mm-2.c: New test. * gcc.target/riscv/rvv/base/vmandn_mm-3.c: New test. * gcc.target/riscv/rvv/base/vmclr_m_m-1.c: New test. * gcc.target/riscv/rvv/base/vmclr_m_m-2.c: New test. * gcc.target/riscv/rvv/base/vmclr_m_m-3.c: New test. * gcc.target/riscv/rvv/base/vmmv_m_m-1.c: New test. * gcc.target/riscv/rvv/base/vmmv_m_m-2.c: New test. * gcc.target/riscv/rvv/base/vmmv_m_m-3.c: New test. * gcc.target/riscv/rvv/base/vmnand_mm-1.c: New test. * gcc.target/riscv/rvv/base/vmnand_mm-2.c: New test. * gcc.target/riscv/rvv/base/vmnand_mm-3.c: New test. * gcc.target/riscv/rvv/base/vmnor_mm-1.c: New test. * gcc.target/riscv/rvv/base/vmnor_mm-2.c: New test. * gcc.target/riscv/rvv/base/vmnor_mm-3.c: New test. * gcc.target/riscv/rvv/base/vmnot_m_m-1.c: New test. * gcc.target/riscv/rvv/base/vmnot_m_m-2.c: New test. * gcc.target/riscv/rvv/base/vmnot_m_m-3.c: New test. * gcc.target/riscv/rvv/base/vmor_mm-1.c: New test. * gcc.target/riscv/rvv/base/vmor_mm-2.c: New test. * gcc.target/riscv/rvv/base/vmor_mm-3.c: New test. * gcc.target/riscv/rvv/base/vmorn_mm-1.c: New test. * gcc.target/riscv/rvv/base/vmorn_mm-2.c: New test. * gcc.target/riscv/rvv/base/vmorn_mm-3.c: New test. * gcc.target/riscv/rvv/base/vmsbf_m_m-1.c: New test. * gcc.target/riscv/rvv/base/vmsbf_m_m-2.c: New test. * gcc.target/riscv/rvv/base/vmsbf_m_m-3.c: New test. * gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c: New test. * gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c: New test. * gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c: New test. * gcc.target/riscv/rvv/base/vmset_m_m-1.c: New test. * gcc.target/riscv/rvv/base/vmset_m_m-2.c: New test. * gcc.target/riscv/rvv/base/vmset_m_m-3.c: New test. * gcc.target/riscv/rvv/base/vmsif_m_m-1.c: New test. * gcc.target/riscv/rvv/base/vmsif_m_m-2.c: New test. * gcc.target/riscv/rvv/base/vmsif_m_m-3.c: New test. * gcc.target/riscv/rvv/base/vmsif_m_mu-1.c: New test. * gcc.target/riscv/rvv/base/vmsif_m_mu-2.c: New test. * gcc.target/riscv/rvv/base/vmsif_m_mu-3.c: New test. * gcc.target/riscv/rvv/base/vmsof_m_m-1.c: New test. * gcc.target/riscv/rvv/base/vmsof_m_m-2.c: New test. * gcc.target/riscv/rvv/base/vmsof_m_m-3.c: New test. * gcc.target/riscv/rvv/base/vmsof_m_mu-1.c: New test. * gcc.target/riscv/rvv/base/vmsof_m_mu-2.c: New test. * gcc.target/riscv/rvv/base/vmsof_m_mu-3.c: New test. * gcc.target/riscv/rvv/base/vmxnor_mm-1.c: New test. * gcc.target/riscv/rvv/base/vmxnor_mm-2.c: New test. * gcc.target/riscv/rvv/base/vmxnor_mm-3.c: New test. * gcc.target/riscv/rvv/base/vmxor_mm-1.c: New test. * gcc.target/riscv/rvv/base/vmxor_mm-2.c: New test. * gcc.target/riscv/rvv/base/vmxor_mm-3.c: New test. --- .../gcc.target/riscv/rvv/base/vmand_mm-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmand_mm-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmand_mm-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmandn_mm-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmandn_mm-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmandn_mm-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmclr_m_m-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmclr_m_m-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmclr_m_m-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmmv_m_m-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmmv_m_m-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmmv_m_m-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmnand_mm-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmnand_mm-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmnand_mm-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmnor_mm-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmnor_mm-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmnor_mm-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmnot_m_m-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmnot_m_m-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmnot_m_m-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmor_mm-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmor_mm-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmor_mm-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmorn_mm-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmorn_mm-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmorn_mm-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmsbf_m_m-1.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsbf_m_m-2.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsbf_m_m-3.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmset_m_m-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmset_m_m-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmset_m_m-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmsif_m_m-1.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsif_m_m-2.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsif_m_m-3.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsif_m_mu-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmsif_m_mu-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmsif_m_mu-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmsof_m_m-1.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsof_m_m-2.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsof_m_m-3.c | 104 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsof_m_mu-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmsof_m_mu-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmsof_m_mu-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmxnor_mm-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmxnor_mm-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmxnor_mm-3.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmxor_mm-1.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmxor_mm-2.c | 55 +++++++++ .../gcc.target/riscv/rvv/base/vmxor_mm-3.c | 55 +++++++++ 54 files changed, 3411 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c new file mode 100644 index 00000000000..9f11c8420dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmand_mm_b1(op1,op2,vl); +} + + +vbool2_t test___riscv_vmand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmand_mm_b2(op1,op2,vl); +} + + +vbool4_t test___riscv_vmand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmand_mm_b4(op1,op2,vl); +} + + +vbool8_t test___riscv_vmand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmand_mm_b8(op1,op2,vl); +} + + +vbool16_t test___riscv_vmand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmand_mm_b16(op1,op2,vl); +} + + +vbool32_t test___riscv_vmand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmand_mm_b32(op1,op2,vl); +} + + +vbool64_t test___riscv_vmand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmand_mm_b64(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c new file mode 100644 index 00000000000..81d96b85f0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmand_mm_b1(op1,op2,31); +} + + +vbool2_t test___riscv_vmand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmand_mm_b2(op1,op2,31); +} + + +vbool4_t test___riscv_vmand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmand_mm_b4(op1,op2,31); +} + + +vbool8_t test___riscv_vmand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmand_mm_b8(op1,op2,31); +} + + +vbool16_t test___riscv_vmand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmand_mm_b16(op1,op2,31); +} + + +vbool32_t test___riscv_vmand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmand_mm_b32(op1,op2,31); +} + + +vbool64_t test___riscv_vmand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmand_mm_b64(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c new file mode 100644 index 00000000000..4b5dd50cf80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmand_mm_b1(op1,op2,32); +} + + +vbool2_t test___riscv_vmand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmand_mm_b2(op1,op2,32); +} + + +vbool4_t test___riscv_vmand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmand_mm_b4(op1,op2,32); +} + + +vbool8_t test___riscv_vmand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmand_mm_b8(op1,op2,32); +} + + +vbool16_t test___riscv_vmand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmand_mm_b16(op1,op2,32); +} + + +vbool32_t test___riscv_vmand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmand_mm_b32(op1,op2,32); +} + + +vbool64_t test___riscv_vmand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmand_mm_b64(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c new file mode 100644 index 00000000000..f0ccd9f54f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmandn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b1(op1,op2,vl); +} + + +vbool2_t test___riscv_vmandn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b2(op1,op2,vl); +} + + +vbool4_t test___riscv_vmandn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b4(op1,op2,vl); +} + + +vbool8_t test___riscv_vmandn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b8(op1,op2,vl); +} + + +vbool16_t test___riscv_vmandn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b16(op1,op2,vl); +} + + +vbool32_t test___riscv_vmandn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b32(op1,op2,vl); +} + + +vbool64_t test___riscv_vmandn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b64(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c new file mode 100644 index 00000000000..a6605c4597d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmandn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b1(op1,op2,31); +} + + +vbool2_t test___riscv_vmandn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b2(op1,op2,31); +} + + +vbool4_t test___riscv_vmandn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b4(op1,op2,31); +} + + +vbool8_t test___riscv_vmandn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b8(op1,op2,31); +} + + +vbool16_t test___riscv_vmandn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b16(op1,op2,31); +} + + +vbool32_t test___riscv_vmandn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b32(op1,op2,31); +} + + +vbool64_t test___riscv_vmandn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b64(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c new file mode 100644 index 00000000000..ad48a8547b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmandn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b1(op1,op2,32); +} + + +vbool2_t test___riscv_vmandn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b2(op1,op2,32); +} + + +vbool4_t test___riscv_vmandn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b4(op1,op2,32); +} + + +vbool8_t test___riscv_vmandn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b8(op1,op2,32); +} + + +vbool16_t test___riscv_vmandn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b16(op1,op2,32); +} + + +vbool32_t test___riscv_vmandn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b32(op1,op2,32); +} + + +vbool64_t test___riscv_vmandn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmandn_mm_b64(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c new file mode 100644 index 00000000000..74f89f1a445 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmclr_m_b1(size_t vl) +{ + return __riscv_vmclr_m_b1(vl); +} + + +vbool2_t test___riscv_vmclr_m_b2(size_t vl) +{ + return __riscv_vmclr_m_b2(vl); +} + + +vbool4_t test___riscv_vmclr_m_b4(size_t vl) +{ + return __riscv_vmclr_m_b4(vl); +} + + +vbool8_t test___riscv_vmclr_m_b8(size_t vl) +{ + return __riscv_vmclr_m_b8(vl); +} + + +vbool16_t test___riscv_vmclr_m_b16(size_t vl) +{ + return __riscv_vmclr_m_b16(vl); +} + + +vbool32_t test___riscv_vmclr_m_b32(size_t vl) +{ + return __riscv_vmclr_m_b32(vl); +} + + +vbool64_t test___riscv_vmclr_m_b64(size_t vl) +{ + return __riscv_vmclr_m_b64(vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c new file mode 100644 index 00000000000..e4c91959dd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmclr_m_b1(size_t vl) +{ + return __riscv_vmclr_m_b1(31); +} + + +vbool2_t test___riscv_vmclr_m_b2(size_t vl) +{ + return __riscv_vmclr_m_b2(31); +} + + +vbool4_t test___riscv_vmclr_m_b4(size_t vl) +{ + return __riscv_vmclr_m_b4(31); +} + + +vbool8_t test___riscv_vmclr_m_b8(size_t vl) +{ + return __riscv_vmclr_m_b8(31); +} + + +vbool16_t test___riscv_vmclr_m_b16(size_t vl) +{ + return __riscv_vmclr_m_b16(31); +} + + +vbool32_t test___riscv_vmclr_m_b32(size_t vl) +{ + return __riscv_vmclr_m_b32(31); +} + + +vbool64_t test___riscv_vmclr_m_b64(size_t vl) +{ + return __riscv_vmclr_m_b64(31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c new file mode 100644 index 00000000000..12cd1a5c0fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmclr_m_b1(size_t vl) +{ + return __riscv_vmclr_m_b1(32); +} + + +vbool2_t test___riscv_vmclr_m_b2(size_t vl) +{ + return __riscv_vmclr_m_b2(32); +} + + +vbool4_t test___riscv_vmclr_m_b4(size_t vl) +{ + return __riscv_vmclr_m_b4(32); +} + + +vbool8_t test___riscv_vmclr_m_b8(size_t vl) +{ + return __riscv_vmclr_m_b8(32); +} + + +vbool16_t test___riscv_vmclr_m_b16(size_t vl) +{ + return __riscv_vmclr_m_b16(32); +} + + +vbool32_t test___riscv_vmclr_m_b32(size_t vl) +{ + return __riscv_vmclr_m_b32(32); +} + + +vbool64_t test___riscv_vmclr_m_b64(size_t vl) +{ + return __riscv_vmclr_m_b64(32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c new file mode 100644 index 00000000000..8ebb69128b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmmv_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmmv_m_b1(op1,vl); +} + + +vbool2_t test___riscv_vmmv_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmmv_m_b2(op1,vl); +} + + +vbool4_t test___riscv_vmmv_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmmv_m_b4(op1,vl); +} + + +vbool8_t test___riscv_vmmv_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmmv_m_b8(op1,vl); +} + + +vbool16_t test___riscv_vmmv_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmmv_m_b16(op1,vl); +} + + +vbool32_t test___riscv_vmmv_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmmv_m_b32(op1,vl); +} + + +vbool64_t test___riscv_vmmv_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmmv_m_b64(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c new file mode 100644 index 00000000000..bd97c0daa7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmmv_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmmv_m_b1(op1,31); +} + + +vbool2_t test___riscv_vmmv_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmmv_m_b2(op1,31); +} + + +vbool4_t test___riscv_vmmv_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmmv_m_b4(op1,31); +} + + +vbool8_t test___riscv_vmmv_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmmv_m_b8(op1,31); +} + + +vbool16_t test___riscv_vmmv_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmmv_m_b16(op1,31); +} + + +vbool32_t test___riscv_vmmv_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmmv_m_b32(op1,31); +} + + +vbool64_t test___riscv_vmmv_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmmv_m_b64(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c new file mode 100644 index 00000000000..fa8cb2f6f6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmmv_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmmv_m_b1(op1,32); +} + + +vbool2_t test___riscv_vmmv_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmmv_m_b2(op1,32); +} + + +vbool4_t test___riscv_vmmv_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmmv_m_b4(op1,32); +} + + +vbool8_t test___riscv_vmmv_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmmv_m_b8(op1,32); +} + + +vbool16_t test___riscv_vmmv_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmmv_m_b16(op1,32); +} + + +vbool32_t test___riscv_vmmv_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmmv_m_b32(op1,32); +} + + +vbool64_t test___riscv_vmmv_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmmv_m_b64(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c new file mode 100644 index 00000000000..9c2f38f6194 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b1(op1,op2,vl); +} + + +vbool2_t test___riscv_vmnand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b2(op1,op2,vl); +} + + +vbool4_t test___riscv_vmnand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b4(op1,op2,vl); +} + + +vbool8_t test___riscv_vmnand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b8(op1,op2,vl); +} + + +vbool16_t test___riscv_vmnand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b16(op1,op2,vl); +} + + +vbool32_t test___riscv_vmnand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b32(op1,op2,vl); +} + + +vbool64_t test___riscv_vmnand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b64(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c new file mode 100644 index 00000000000..35eeedb12e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b1(op1,op2,31); +} + + +vbool2_t test___riscv_vmnand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b2(op1,op2,31); +} + + +vbool4_t test___riscv_vmnand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b4(op1,op2,31); +} + + +vbool8_t test___riscv_vmnand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b8(op1,op2,31); +} + + +vbool16_t test___riscv_vmnand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b16(op1,op2,31); +} + + +vbool32_t test___riscv_vmnand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b32(op1,op2,31); +} + + +vbool64_t test___riscv_vmnand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b64(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c new file mode 100644 index 00000000000..69b32ef8111 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b1(op1,op2,32); +} + + +vbool2_t test___riscv_vmnand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b2(op1,op2,32); +} + + +vbool4_t test___riscv_vmnand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b4(op1,op2,32); +} + + +vbool8_t test___riscv_vmnand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b8(op1,op2,32); +} + + +vbool16_t test___riscv_vmnand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b16(op1,op2,32); +} + + +vbool32_t test___riscv_vmnand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b32(op1,op2,32); +} + + +vbool64_t test___riscv_vmnand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnand_mm_b64(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c new file mode 100644 index 00000000000..7724fcb2725 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b1(op1,op2,vl); +} + + +vbool2_t test___riscv_vmnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b2(op1,op2,vl); +} + + +vbool4_t test___riscv_vmnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b4(op1,op2,vl); +} + + +vbool8_t test___riscv_vmnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b8(op1,op2,vl); +} + + +vbool16_t test___riscv_vmnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b16(op1,op2,vl); +} + + +vbool32_t test___riscv_vmnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b32(op1,op2,vl); +} + + +vbool64_t test___riscv_vmnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b64(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c new file mode 100644 index 00000000000..91eabb9a800 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b1(op1,op2,31); +} + + +vbool2_t test___riscv_vmnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b2(op1,op2,31); +} + + +vbool4_t test___riscv_vmnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b4(op1,op2,31); +} + + +vbool8_t test___riscv_vmnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b8(op1,op2,31); +} + + +vbool16_t test___riscv_vmnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b16(op1,op2,31); +} + + +vbool32_t test___riscv_vmnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b32(op1,op2,31); +} + + +vbool64_t test___riscv_vmnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b64(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c new file mode 100644 index 00000000000..2eb333b6f46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b1(op1,op2,32); +} + + +vbool2_t test___riscv_vmnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b2(op1,op2,32); +} + + +vbool4_t test___riscv_vmnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b4(op1,op2,32); +} + + +vbool8_t test___riscv_vmnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b8(op1,op2,32); +} + + +vbool16_t test___riscv_vmnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b16(op1,op2,32); +} + + +vbool32_t test___riscv_vmnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b32(op1,op2,32); +} + + +vbool64_t test___riscv_vmnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnor_mm_b64(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c new file mode 100644 index 00000000000..bba5506cf11 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnot_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmnot_m_b1(op1,vl); +} + + +vbool2_t test___riscv_vmnot_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmnot_m_b2(op1,vl); +} + + +vbool4_t test___riscv_vmnot_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmnot_m_b4(op1,vl); +} + + +vbool8_t test___riscv_vmnot_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmnot_m_b8(op1,vl); +} + + +vbool16_t test___riscv_vmnot_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmnot_m_b16(op1,vl); +} + + +vbool32_t test___riscv_vmnot_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmnot_m_b32(op1,vl); +} + + +vbool64_t test___riscv_vmnot_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmnot_m_b64(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c new file mode 100644 index 00000000000..a7c872372a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnot_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmnot_m_b1(op1,31); +} + + +vbool2_t test___riscv_vmnot_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmnot_m_b2(op1,31); +} + + +vbool4_t test___riscv_vmnot_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmnot_m_b4(op1,31); +} + + +vbool8_t test___riscv_vmnot_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmnot_m_b8(op1,31); +} + + +vbool16_t test___riscv_vmnot_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmnot_m_b16(op1,31); +} + + +vbool32_t test___riscv_vmnot_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmnot_m_b32(op1,31); +} + + +vbool64_t test___riscv_vmnot_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmnot_m_b64(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c new file mode 100644 index 00000000000..8c68be9f870 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnot_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmnot_m_b1(op1,32); +} + + +vbool2_t test___riscv_vmnot_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmnot_m_b2(op1,32); +} + + +vbool4_t test___riscv_vmnot_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmnot_m_b4(op1,32); +} + + +vbool8_t test___riscv_vmnot_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmnot_m_b8(op1,32); +} + + +vbool16_t test___riscv_vmnot_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmnot_m_b16(op1,32); +} + + +vbool32_t test___riscv_vmnot_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmnot_m_b32(op1,32); +} + + +vbool64_t test___riscv_vmnot_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmnot_m_b64(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c new file mode 100644 index 00000000000..638c0b3743f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmor_mm_b1(op1,op2,vl); +} + + +vbool2_t test___riscv_vmor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmor_mm_b2(op1,op2,vl); +} + + +vbool4_t test___riscv_vmor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmor_mm_b4(op1,op2,vl); +} + + +vbool8_t test___riscv_vmor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmor_mm_b8(op1,op2,vl); +} + + +vbool16_t test___riscv_vmor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmor_mm_b16(op1,op2,vl); +} + + +vbool32_t test___riscv_vmor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmor_mm_b32(op1,op2,vl); +} + + +vbool64_t test___riscv_vmor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmor_mm_b64(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c new file mode 100644 index 00000000000..eb8ebc25904 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmor_mm_b1(op1,op2,31); +} + + +vbool2_t test___riscv_vmor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmor_mm_b2(op1,op2,31); +} + + +vbool4_t test___riscv_vmor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmor_mm_b4(op1,op2,31); +} + + +vbool8_t test___riscv_vmor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmor_mm_b8(op1,op2,31); +} + + +vbool16_t test___riscv_vmor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmor_mm_b16(op1,op2,31); +} + + +vbool32_t test___riscv_vmor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmor_mm_b32(op1,op2,31); +} + + +vbool64_t test___riscv_vmor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmor_mm_b64(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c new file mode 100644 index 00000000000..3b6a7e81ef9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmor_mm_b1(op1,op2,32); +} + + +vbool2_t test___riscv_vmor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmor_mm_b2(op1,op2,32); +} + + +vbool4_t test___riscv_vmor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmor_mm_b4(op1,op2,32); +} + + +vbool8_t test___riscv_vmor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmor_mm_b8(op1,op2,32); +} + + +vbool16_t test___riscv_vmor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmor_mm_b16(op1,op2,32); +} + + +vbool32_t test___riscv_vmor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmor_mm_b32(op1,op2,32); +} + + +vbool64_t test___riscv_vmor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmor_mm_b64(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c new file mode 100644 index 00000000000..c8c383dbc78 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmorn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b1(op1,op2,vl); +} + + +vbool2_t test___riscv_vmorn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b2(op1,op2,vl); +} + + +vbool4_t test___riscv_vmorn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b4(op1,op2,vl); +} + + +vbool8_t test___riscv_vmorn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b8(op1,op2,vl); +} + + +vbool16_t test___riscv_vmorn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b16(op1,op2,vl); +} + + +vbool32_t test___riscv_vmorn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b32(op1,op2,vl); +} + + +vbool64_t test___riscv_vmorn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b64(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c new file mode 100644 index 00000000000..d612293066c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmorn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b1(op1,op2,31); +} + + +vbool2_t test___riscv_vmorn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b2(op1,op2,31); +} + + +vbool4_t test___riscv_vmorn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b4(op1,op2,31); +} + + +vbool8_t test___riscv_vmorn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b8(op1,op2,31); +} + + +vbool16_t test___riscv_vmorn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b16(op1,op2,31); +} + + +vbool32_t test___riscv_vmorn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b32(op1,op2,31); +} + + +vbool64_t test___riscv_vmorn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b64(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c new file mode 100644 index 00000000000..d3701ddc453 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmorn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b1(op1,op2,32); +} + + +vbool2_t test___riscv_vmorn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b2(op1,op2,32); +} + + +vbool4_t test___riscv_vmorn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b4(op1,op2,32); +} + + +vbool8_t test___riscv_vmorn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b8(op1,op2,32); +} + + +vbool16_t test___riscv_vmorn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b16(op1,op2,32); +} + + +vbool32_t test___riscv_vmorn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b32(op1,op2,32); +} + + +vbool64_t test___riscv_vmorn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmorn_mm_b64(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c new file mode 100644 index 00000000000..393928d7069 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b1(op1,vl); +} + + +vbool2_t test___riscv_vmsbf_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b2(op1,vl); +} + + +vbool4_t test___riscv_vmsbf_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b4(op1,vl); +} + + +vbool8_t test___riscv_vmsbf_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b8(op1,vl); +} + + +vbool16_t test___riscv_vmsbf_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b16(op1,vl); +} + + +vbool32_t test___riscv_vmsbf_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b32(op1,vl); +} + + +vbool64_t test___riscv_vmsbf_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b64(op1,vl); +} + + +vbool1_t test___riscv_vmsbf_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b1_m(mask,op1,vl); +} + + +vbool2_t test___riscv_vmsbf_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b2_m(mask,op1,vl); +} + + +vbool4_t test___riscv_vmsbf_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b4_m(mask,op1,vl); +} + + +vbool8_t test___riscv_vmsbf_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b8_m(mask,op1,vl); +} + + +vbool16_t test___riscv_vmsbf_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b16_m(mask,op1,vl); +} + + +vbool32_t test___riscv_vmsbf_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b32_m(mask,op1,vl); +} + + +vbool64_t test___riscv_vmsbf_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b64_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c new file mode 100644 index 00000000000..961282f52a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b1(op1,31); +} + + +vbool2_t test___riscv_vmsbf_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b2(op1,31); +} + + +vbool4_t test___riscv_vmsbf_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b4(op1,31); +} + + +vbool8_t test___riscv_vmsbf_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b8(op1,31); +} + + +vbool16_t test___riscv_vmsbf_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b16(op1,31); +} + + +vbool32_t test___riscv_vmsbf_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b32(op1,31); +} + + +vbool64_t test___riscv_vmsbf_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b64(op1,31); +} + + +vbool1_t test___riscv_vmsbf_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b1_m(mask,op1,31); +} + + +vbool2_t test___riscv_vmsbf_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b2_m(mask,op1,31); +} + + +vbool4_t test___riscv_vmsbf_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b4_m(mask,op1,31); +} + + +vbool8_t test___riscv_vmsbf_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b8_m(mask,op1,31); +} + + +vbool16_t test___riscv_vmsbf_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b16_m(mask,op1,31); +} + + +vbool32_t test___riscv_vmsbf_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b32_m(mask,op1,31); +} + + +vbool64_t test___riscv_vmsbf_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b64_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c new file mode 100644 index 00000000000..60802fa81d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b1(op1,32); +} + + +vbool2_t test___riscv_vmsbf_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b2(op1,32); +} + + +vbool4_t test___riscv_vmsbf_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b4(op1,32); +} + + +vbool8_t test___riscv_vmsbf_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b8(op1,32); +} + + +vbool16_t test___riscv_vmsbf_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b16(op1,32); +} + + +vbool32_t test___riscv_vmsbf_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b32(op1,32); +} + + +vbool64_t test___riscv_vmsbf_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b64(op1,32); +} + + +vbool1_t test___riscv_vmsbf_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b1_m(mask,op1,32); +} + + +vbool2_t test___riscv_vmsbf_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b2_m(mask,op1,32); +} + + +vbool4_t test___riscv_vmsbf_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b4_m(mask,op1,32); +} + + +vbool8_t test___riscv_vmsbf_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b8_m(mask,op1,32); +} + + +vbool16_t test___riscv_vmsbf_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b16_m(mask,op1,32); +} + + +vbool32_t test___riscv_vmsbf_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b32_m(mask,op1,32); +} + + +vbool64_t test___riscv_vmsbf_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b64_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c new file mode 100644 index 00000000000..81255e48b63 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b1_mu(mask,maskedoff,op1,vl); +} + + +vbool2_t test___riscv_vmsbf_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b2_mu(mask,maskedoff,op1,vl); +} + + +vbool4_t test___riscv_vmsbf_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b4_mu(mask,maskedoff,op1,vl); +} + + +vbool8_t test___riscv_vmsbf_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b8_mu(mask,maskedoff,op1,vl); +} + + +vbool16_t test___riscv_vmsbf_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b16_mu(mask,maskedoff,op1,vl); +} + + +vbool32_t test___riscv_vmsbf_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b32_mu(mask,maskedoff,op1,vl); +} + + +vbool64_t test___riscv_vmsbf_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b64_mu(mask,maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c new file mode 100644 index 00000000000..377613d89af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b1_mu(mask,maskedoff,op1,31); +} + + +vbool2_t test___riscv_vmsbf_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b2_mu(mask,maskedoff,op1,31); +} + + +vbool4_t test___riscv_vmsbf_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b4_mu(mask,maskedoff,op1,31); +} + + +vbool8_t test___riscv_vmsbf_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b8_mu(mask,maskedoff,op1,31); +} + + +vbool16_t test___riscv_vmsbf_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b16_mu(mask,maskedoff,op1,31); +} + + +vbool32_t test___riscv_vmsbf_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b32_mu(mask,maskedoff,op1,31); +} + + +vbool64_t test___riscv_vmsbf_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b64_mu(mask,maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c new file mode 100644 index 00000000000..16ebb27f67c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b1_mu(mask,maskedoff,op1,32); +} + + +vbool2_t test___riscv_vmsbf_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b2_mu(mask,maskedoff,op1,32); +} + + +vbool4_t test___riscv_vmsbf_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b4_mu(mask,maskedoff,op1,32); +} + + +vbool8_t test___riscv_vmsbf_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b8_mu(mask,maskedoff,op1,32); +} + + +vbool16_t test___riscv_vmsbf_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b16_mu(mask,maskedoff,op1,32); +} + + +vbool32_t test___riscv_vmsbf_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b32_mu(mask,maskedoff,op1,32); +} + + +vbool64_t test___riscv_vmsbf_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_m_b64_mu(mask,maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c new file mode 100644 index 00000000000..3be6e704197 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmset_m_b1(size_t vl) +{ + return __riscv_vmset_m_b1(vl); +} + + +vbool2_t test___riscv_vmset_m_b2(size_t vl) +{ + return __riscv_vmset_m_b2(vl); +} + + +vbool4_t test___riscv_vmset_m_b4(size_t vl) +{ + return __riscv_vmset_m_b4(vl); +} + + +vbool8_t test___riscv_vmset_m_b8(size_t vl) +{ + return __riscv_vmset_m_b8(vl); +} + + +vbool16_t test___riscv_vmset_m_b16(size_t vl) +{ + return __riscv_vmset_m_b16(vl); +} + + +vbool32_t test___riscv_vmset_m_b32(size_t vl) +{ + return __riscv_vmset_m_b32(vl); +} + + +vbool64_t test___riscv_vmset_m_b64(size_t vl) +{ + return __riscv_vmset_m_b64(vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c new file mode 100644 index 00000000000..d020c8decaa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmset_m_b1(size_t vl) +{ + return __riscv_vmset_m_b1(31); +} + + +vbool2_t test___riscv_vmset_m_b2(size_t vl) +{ + return __riscv_vmset_m_b2(31); +} + + +vbool4_t test___riscv_vmset_m_b4(size_t vl) +{ + return __riscv_vmset_m_b4(31); +} + + +vbool8_t test___riscv_vmset_m_b8(size_t vl) +{ + return __riscv_vmset_m_b8(31); +} + + +vbool16_t test___riscv_vmset_m_b16(size_t vl) +{ + return __riscv_vmset_m_b16(31); +} + + +vbool32_t test___riscv_vmset_m_b32(size_t vl) +{ + return __riscv_vmset_m_b32(31); +} + + +vbool64_t test___riscv_vmset_m_b64(size_t vl) +{ + return __riscv_vmset_m_b64(31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c new file mode 100644 index 00000000000..e1761956b0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmset_m_b1(size_t vl) +{ + return __riscv_vmset_m_b1(32); +} + + +vbool2_t test___riscv_vmset_m_b2(size_t vl) +{ + return __riscv_vmset_m_b2(32); +} + + +vbool4_t test___riscv_vmset_m_b4(size_t vl) +{ + return __riscv_vmset_m_b4(32); +} + + +vbool8_t test___riscv_vmset_m_b8(size_t vl) +{ + return __riscv_vmset_m_b8(32); +} + + +vbool16_t test___riscv_vmset_m_b16(size_t vl) +{ + return __riscv_vmset_m_b16(32); +} + + +vbool32_t test___riscv_vmset_m_b32(size_t vl) +{ + return __riscv_vmset_m_b32(32); +} + + +vbool64_t test___riscv_vmset_m_b64(size_t vl) +{ + return __riscv_vmset_m_b64(32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c new file mode 100644 index 00000000000..e22e1772c92 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_m_b1(op1,vl); +} + + +vbool2_t test___riscv_vmsif_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_m_b2(op1,vl); +} + + +vbool4_t test___riscv_vmsif_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_m_b4(op1,vl); +} + + +vbool8_t test___riscv_vmsif_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_m_b8(op1,vl); +} + + +vbool16_t test___riscv_vmsif_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_m_b16(op1,vl); +} + + +vbool32_t test___riscv_vmsif_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_m_b32(op1,vl); +} + + +vbool64_t test___riscv_vmsif_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_m_b64(op1,vl); +} + + +vbool1_t test___riscv_vmsif_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_m_b1_m(mask,op1,vl); +} + + +vbool2_t test___riscv_vmsif_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_m_b2_m(mask,op1,vl); +} + + +vbool4_t test___riscv_vmsif_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_m_b4_m(mask,op1,vl); +} + + +vbool8_t test___riscv_vmsif_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_m_b8_m(mask,op1,vl); +} + + +vbool16_t test___riscv_vmsif_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_m_b16_m(mask,op1,vl); +} + + +vbool32_t test___riscv_vmsif_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_m_b32_m(mask,op1,vl); +} + + +vbool64_t test___riscv_vmsif_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_m_b64_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c new file mode 100644 index 00000000000..cb7ad9faece --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_m_b1(op1,31); +} + + +vbool2_t test___riscv_vmsif_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_m_b2(op1,31); +} + + +vbool4_t test___riscv_vmsif_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_m_b4(op1,31); +} + + +vbool8_t test___riscv_vmsif_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_m_b8(op1,31); +} + + +vbool16_t test___riscv_vmsif_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_m_b16(op1,31); +} + + +vbool32_t test___riscv_vmsif_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_m_b32(op1,31); +} + + +vbool64_t test___riscv_vmsif_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_m_b64(op1,31); +} + + +vbool1_t test___riscv_vmsif_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_m_b1_m(mask,op1,31); +} + + +vbool2_t test___riscv_vmsif_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_m_b2_m(mask,op1,31); +} + + +vbool4_t test___riscv_vmsif_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_m_b4_m(mask,op1,31); +} + + +vbool8_t test___riscv_vmsif_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_m_b8_m(mask,op1,31); +} + + +vbool16_t test___riscv_vmsif_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_m_b16_m(mask,op1,31); +} + + +vbool32_t test___riscv_vmsif_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_m_b32_m(mask,op1,31); +} + + +vbool64_t test___riscv_vmsif_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_m_b64_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c new file mode 100644 index 00000000000..c92b0e9b89a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_m_b1(op1,32); +} + + +vbool2_t test___riscv_vmsif_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_m_b2(op1,32); +} + + +vbool4_t test___riscv_vmsif_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_m_b4(op1,32); +} + + +vbool8_t test___riscv_vmsif_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_m_b8(op1,32); +} + + +vbool16_t test___riscv_vmsif_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_m_b16(op1,32); +} + + +vbool32_t test___riscv_vmsif_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_m_b32(op1,32); +} + + +vbool64_t test___riscv_vmsif_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_m_b64(op1,32); +} + + +vbool1_t test___riscv_vmsif_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_m_b1_m(mask,op1,32); +} + + +vbool2_t test___riscv_vmsif_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_m_b2_m(mask,op1,32); +} + + +vbool4_t test___riscv_vmsif_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_m_b4_m(mask,op1,32); +} + + +vbool8_t test___riscv_vmsif_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_m_b8_m(mask,op1,32); +} + + +vbool16_t test___riscv_vmsif_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_m_b16_m(mask,op1,32); +} + + +vbool32_t test___riscv_vmsif_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_m_b32_m(mask,op1,32); +} + + +vbool64_t test___riscv_vmsif_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_m_b64_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c new file mode 100644 index 00000000000..7a7075e61e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_m_b1_mu(mask,maskedoff,op1,vl); +} + + +vbool2_t test___riscv_vmsif_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_m_b2_mu(mask,maskedoff,op1,vl); +} + + +vbool4_t test___riscv_vmsif_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_m_b4_mu(mask,maskedoff,op1,vl); +} + + +vbool8_t test___riscv_vmsif_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_m_b8_mu(mask,maskedoff,op1,vl); +} + + +vbool16_t test___riscv_vmsif_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_m_b16_mu(mask,maskedoff,op1,vl); +} + + +vbool32_t test___riscv_vmsif_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_m_b32_mu(mask,maskedoff,op1,vl); +} + + +vbool64_t test___riscv_vmsif_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_m_b64_mu(mask,maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c new file mode 100644 index 00000000000..8e8222bd3b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_m_b1_mu(mask,maskedoff,op1,31); +} + + +vbool2_t test___riscv_vmsif_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_m_b2_mu(mask,maskedoff,op1,31); +} + + +vbool4_t test___riscv_vmsif_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_m_b4_mu(mask,maskedoff,op1,31); +} + + +vbool8_t test___riscv_vmsif_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_m_b8_mu(mask,maskedoff,op1,31); +} + + +vbool16_t test___riscv_vmsif_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_m_b16_mu(mask,maskedoff,op1,31); +} + + +vbool32_t test___riscv_vmsif_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_m_b32_mu(mask,maskedoff,op1,31); +} + + +vbool64_t test___riscv_vmsif_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_m_b64_mu(mask,maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c new file mode 100644 index 00000000000..c305562df82 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_m_b1_mu(mask,maskedoff,op1,32); +} + + +vbool2_t test___riscv_vmsif_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_m_b2_mu(mask,maskedoff,op1,32); +} + + +vbool4_t test___riscv_vmsif_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_m_b4_mu(mask,maskedoff,op1,32); +} + + +vbool8_t test___riscv_vmsif_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_m_b8_mu(mask,maskedoff,op1,32); +} + + +vbool16_t test___riscv_vmsif_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_m_b16_mu(mask,maskedoff,op1,32); +} + + +vbool32_t test___riscv_vmsif_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_m_b32_mu(mask,maskedoff,op1,32); +} + + +vbool64_t test___riscv_vmsif_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_m_b64_mu(mask,maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c new file mode 100644 index 00000000000..87202ff62ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_m_b1(op1,vl); +} + + +vbool2_t test___riscv_vmsof_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_m_b2(op1,vl); +} + + +vbool4_t test___riscv_vmsof_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_m_b4(op1,vl); +} + + +vbool8_t test___riscv_vmsof_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_m_b8(op1,vl); +} + + +vbool16_t test___riscv_vmsof_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_m_b16(op1,vl); +} + + +vbool32_t test___riscv_vmsof_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_m_b32(op1,vl); +} + + +vbool64_t test___riscv_vmsof_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_m_b64(op1,vl); +} + + +vbool1_t test___riscv_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_m_b1_m(mask,op1,vl); +} + + +vbool2_t test___riscv_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_m_b2_m(mask,op1,vl); +} + + +vbool4_t test___riscv_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_m_b4_m(mask,op1,vl); +} + + +vbool8_t test___riscv_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_m_b8_m(mask,op1,vl); +} + + +vbool16_t test___riscv_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_m_b16_m(mask,op1,vl); +} + + +vbool32_t test___riscv_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_m_b32_m(mask,op1,vl); +} + + +vbool64_t test___riscv_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_m_b64_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c new file mode 100644 index 00000000000..6e4f3ce1288 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_m_b1(op1,31); +} + + +vbool2_t test___riscv_vmsof_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_m_b2(op1,31); +} + + +vbool4_t test___riscv_vmsof_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_m_b4(op1,31); +} + + +vbool8_t test___riscv_vmsof_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_m_b8(op1,31); +} + + +vbool16_t test___riscv_vmsof_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_m_b16(op1,31); +} + + +vbool32_t test___riscv_vmsof_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_m_b32(op1,31); +} + + +vbool64_t test___riscv_vmsof_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_m_b64(op1,31); +} + + +vbool1_t test___riscv_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_m_b1_m(mask,op1,31); +} + + +vbool2_t test___riscv_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_m_b2_m(mask,op1,31); +} + + +vbool4_t test___riscv_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_m_b4_m(mask,op1,31); +} + + +vbool8_t test___riscv_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_m_b8_m(mask,op1,31); +} + + +vbool16_t test___riscv_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_m_b16_m(mask,op1,31); +} + + +vbool32_t test___riscv_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_m_b32_m(mask,op1,31); +} + + +vbool64_t test___riscv_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_m_b64_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c new file mode 100644 index 00000000000..55cf50d5c9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof_m_b1(vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_m_b1(op1,32); +} + + +vbool2_t test___riscv_vmsof_m_b2(vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_m_b2(op1,32); +} + + +vbool4_t test___riscv_vmsof_m_b4(vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_m_b4(op1,32); +} + + +vbool8_t test___riscv_vmsof_m_b8(vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_m_b8(op1,32); +} + + +vbool16_t test___riscv_vmsof_m_b16(vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_m_b16(op1,32); +} + + +vbool32_t test___riscv_vmsof_m_b32(vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_m_b32(op1,32); +} + + +vbool64_t test___riscv_vmsof_m_b64(vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_m_b64(op1,32); +} + + +vbool1_t test___riscv_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_m_b1_m(mask,op1,32); +} + + +vbool2_t test___riscv_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_m_b2_m(mask,op1,32); +} + + +vbool4_t test___riscv_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_m_b4_m(mask,op1,32); +} + + +vbool8_t test___riscv_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_m_b8_m(mask,op1,32); +} + + +vbool16_t test___riscv_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_m_b16_m(mask,op1,32); +} + + +vbool32_t test___riscv_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_m_b32_m(mask,op1,32); +} + + +vbool64_t test___riscv_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_m_b64_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c new file mode 100644 index 00000000000..4b9d846631e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_m_b1_mu(mask,maskedoff,op1,vl); +} + + +vbool2_t test___riscv_vmsof_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_m_b2_mu(mask,maskedoff,op1,vl); +} + + +vbool4_t test___riscv_vmsof_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_m_b4_mu(mask,maskedoff,op1,vl); +} + + +vbool8_t test___riscv_vmsof_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_m_b8_mu(mask,maskedoff,op1,vl); +} + + +vbool16_t test___riscv_vmsof_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_m_b16_mu(mask,maskedoff,op1,vl); +} + + +vbool32_t test___riscv_vmsof_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_m_b32_mu(mask,maskedoff,op1,vl); +} + + +vbool64_t test___riscv_vmsof_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_m_b64_mu(mask,maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c new file mode 100644 index 00000000000..3f4ea728505 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_m_b1_mu(mask,maskedoff,op1,31); +} + + +vbool2_t test___riscv_vmsof_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_m_b2_mu(mask,maskedoff,op1,31); +} + + +vbool4_t test___riscv_vmsof_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_m_b4_mu(mask,maskedoff,op1,31); +} + + +vbool8_t test___riscv_vmsof_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_m_b8_mu(mask,maskedoff,op1,31); +} + + +vbool16_t test___riscv_vmsof_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_m_b16_mu(mask,maskedoff,op1,31); +} + + +vbool32_t test___riscv_vmsof_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_m_b32_mu(mask,maskedoff,op1,31); +} + + +vbool64_t test___riscv_vmsof_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_m_b64_mu(mask,maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c new file mode 100644 index 00000000000..9c143bfc746 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_m_b1_mu(mask,maskedoff,op1,32); +} + + +vbool2_t test___riscv_vmsof_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_m_b2_mu(mask,maskedoff,op1,32); +} + + +vbool4_t test___riscv_vmsof_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_m_b4_mu(mask,maskedoff,op1,32); +} + + +vbool8_t test___riscv_vmsof_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_m_b8_mu(mask,maskedoff,op1,32); +} + + +vbool16_t test___riscv_vmsof_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_m_b16_mu(mask,maskedoff,op1,32); +} + + +vbool32_t test___riscv_vmsof_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_m_b32_mu(mask,maskedoff,op1,32); +} + + +vbool64_t test___riscv_vmsof_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_m_b64_mu(mask,maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c new file mode 100644 index 00000000000..0d63ea7718e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b1(op1,op2,vl); +} + + +vbool2_t test___riscv_vmxnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b2(op1,op2,vl); +} + + +vbool4_t test___riscv_vmxnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b4(op1,op2,vl); +} + + +vbool8_t test___riscv_vmxnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b8(op1,op2,vl); +} + + +vbool16_t test___riscv_vmxnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b16(op1,op2,vl); +} + + +vbool32_t test___riscv_vmxnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b32(op1,op2,vl); +} + + +vbool64_t test___riscv_vmxnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b64(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c new file mode 100644 index 00000000000..ba39230b2b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b1(op1,op2,31); +} + + +vbool2_t test___riscv_vmxnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b2(op1,op2,31); +} + + +vbool4_t test___riscv_vmxnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b4(op1,op2,31); +} + + +vbool8_t test___riscv_vmxnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b8(op1,op2,31); +} + + +vbool16_t test___riscv_vmxnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b16(op1,op2,31); +} + + +vbool32_t test___riscv_vmxnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b32(op1,op2,31); +} + + +vbool64_t test___riscv_vmxnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b64(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c new file mode 100644 index 00000000000..e74c39b5dde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b1(op1,op2,32); +} + + +vbool2_t test___riscv_vmxnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b2(op1,op2,32); +} + + +vbool4_t test___riscv_vmxnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b4(op1,op2,32); +} + + +vbool8_t test___riscv_vmxnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b8(op1,op2,32); +} + + +vbool16_t test___riscv_vmxnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b16(op1,op2,32); +} + + +vbool32_t test___riscv_vmxnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b32(op1,op2,32); +} + + +vbool64_t test___riscv_vmxnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxnor_mm_b64(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c new file mode 100644 index 00000000000..b7072e492fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b1(op1,op2,vl); +} + + +vbool2_t test___riscv_vmxor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b2(op1,op2,vl); +} + + +vbool4_t test___riscv_vmxor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b4(op1,op2,vl); +} + + +vbool8_t test___riscv_vmxor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b8(op1,op2,vl); +} + + +vbool16_t test___riscv_vmxor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b16(op1,op2,vl); +} + + +vbool32_t test___riscv_vmxor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b32(op1,op2,vl); +} + + +vbool64_t test___riscv_vmxor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b64(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c new file mode 100644 index 00000000000..3222cd2f7bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b1(op1,op2,31); +} + + +vbool2_t test___riscv_vmxor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b2(op1,op2,31); +} + + +vbool4_t test___riscv_vmxor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b4(op1,op2,31); +} + + +vbool8_t test___riscv_vmxor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b8(op1,op2,31); +} + + +vbool16_t test___riscv_vmxor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b16(op1,op2,31); +} + + +vbool32_t test___riscv_vmxor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b32(op1,op2,31); +} + + +vbool64_t test___riscv_vmxor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b64(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c new file mode 100644 index 00000000000..9938dc94151 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b1(op1,op2,32); +} + + +vbool2_t test___riscv_vmxor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b2(op1,op2,32); +} + + +vbool4_t test___riscv_vmxor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b4(op1,op2,32); +} + + +vbool8_t test___riscv_vmxor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b8(op1,op2,32); +} + + +vbool16_t test___riscv_vmxor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b16(op1,op2,32); +} + + +vbool32_t test___riscv_vmxor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b32(op1,op2,32); +} + + +vbool64_t test___riscv_vmxor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxor_mm_b64(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */