From patchwork Tue Feb 14 23:18:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 57272 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp3253935wrn; Tue, 14 Feb 2023 15:19:09 -0800 (PST) X-Google-Smtp-Source: AK7set9qv55lv3mUKYO5wnRxp605UIkgNeLBDFs0w75VvRj4RuUxUk2vyM8/87wHKww3A5KaXxy+ X-Received: by 2002:a05:6402:1856:b0:4aa:a0ed:e373 with SMTP id v22-20020a056402185600b004aaa0ede373mr35291edy.7.1676416749498; Tue, 14 Feb 2023 15:19:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676416749; cv=none; d=google.com; s=arc-20160816; b=aaMZrxyWyh8U2OxIxQ5CNcmu4QLjFT/TE1U/gugTpOJHtKG3yxhxbVokeluvazt5IU Vzw/JHRm9Tlv15WyD3VeOxJ9mwuOiOFjrF00S2u74N6B4j84hS4IqqP7DNtcszm1zPSZ 1brSwxcN9mWwBo94vVArTMSjH6ItdKW2fzqVsZ5WWiwwPHUZEYMlT2rQ3wOwd4oC7me4 a1uSiM062TicKRQxupWDBkr3sixAB5H1OYuDXKDU3WEApEQsvBE7x4K616msdElYfSJx hdpkW8H1wMN6VkTMhvvI7q7IGqGGmt78kaabUgIKMmhZ4AG99CUEDc2IYGcghxjyizpJ /Z8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=YAWB3P2BlaHUvb+5vcY/1so+jz57Zoc9oVKzdm7In4o=; b=VdaJIU8ICfRGmUYSr5vQ0g/VAXdvXGUDtjmPY0xU0qcGtDOFJkPmaB4pRxFc2qj6Dv efonmm85TiD7DyGPhcaIBBmBCkYBM7ONPE/S8bc7rEHvSpjuv8iGFVWnq9+7O2nwb6VE /AdO5ceg8JpDrpd83zFDrlWgJxtw+Njxcvk/xQKbCkZThx3OMP9BkW+B0j0cXJt3ae9d IUb8edDvj16TdSbFVriMMoQRLNVKU4hkCbmkQ9mG8qgDSDW1rmPhFoohC9rhOn+D3oli u2LisCpNYMTdAYiU0e97sgwqeqhow6s1QxWH2HV43GxZgiPCne3mskv4Qyk8ARVeRlkV svMQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m7-20020aa7d347000000b004ab4d025978si13700218edr.245.2023.02.14.15.19.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 15:19:09 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 83A203857835 for ; Tue, 14 Feb 2023 23:19:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by sourceware.org (Postfix) with ESMTPS id 9E75C3858D1E for ; Tue, 14 Feb 2023 23:18:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9E75C3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp91t1676416702t56b4cgi Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 15 Feb 2023 07:18:21 +0800 (CST) X-QQ-SSF: 01400000002000E0L000B00A0000000 X-QQ-FEAT: k0mQ4ihyJQOzHsknVwIumPNYkpCqZpPA0ShTs7U0mDMhR9I8NF1NGAnvyxBAD mbm8LS2nbdHe/1VjB/m4EGLMhFDvdSvpV6dAzy65GjMGSg0WkUifUbIP1BJOHN2ELAY3Y5C Pw2FfZg5RVLVC90mqDGLGuYBX4MJUPU09/tDbZn+QmIsc4NrDHQqVTIQkLXV4f6ednqG9/t f/P4ML/dZAEUpIXQQ9K09+JnJlgGPElyF8qHQW6KLmT5DPvReKa+ExX23Z2P5f9F7yi3W7D 5ECXl6NTdRYHR/ttmpYf/xBGXD58PuYzbhdf02qNmsLdoE3kgGb1tKsMWKKcoXik4/IdiR9 QFfCDNLYGa/Z5K5gq2OWIG9Gwv+wMCQck65AsEvw4qPER9mdJLTAtTl6g4nqg== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Move saturating add/subtract md pattern location [NFC] Date: Wed, 15 Feb 2023 07:18:20 +0800 Message-Id: <20230214231820.283957-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757850369154956905?= X-GMAIL-MSGID: =?utf-8?q?1757850369154956905?= From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/vector.md (@pred_): Rearrange. (@pred__scalar): Ditto. (*pred__scalar): Ditto. (*pred__extended_scalar): Ditto. --- gcc/config/riscv/vector.md | 490 ++++++++++++++++++------------------- 1 file changed, 245 insertions(+), 245 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index b6e67e94f67..764d9316ad9 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1336,7 +1336,6 @@ ;; - 11.9 Vector Integer Min/Max Instructions ;; - 11.10 Vector Single-Width Integer Multiply Instructions ;; - 11.11 Vector Integer Divide Instructions -;; - 12.1 Vector Single-Width Saturating Add and Subtract ;; ------------------------------------------------------------------------------- (define_insn "@pred_" @@ -1728,248 +1727,6 @@ [(set_attr "type" "vialu") (set_attr "mode" "")]) -;; Saturating Add and Subtract -(define_insn "@pred_" - [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr") - (if_then_else:VI - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (any_sat_int_binop:VI - (match_operand:VI 3 "" " vr, vr, vr, vr") - (match_operand:VI 4 "" "")) - (match_operand:VI 2 "vector_merge_operand" "0vu,0vu,0vu,0vu")))] - "TARGET_VECTOR" - "@ - v.vv\t%0,%3,%4%p1 - v.vv\t%0,%3,%4%p1 - v\t%0,%p1 - v\t%0,%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode. -(define_insn "@pred__scalar" - [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr") - (if_then_else:VI_QHS - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_plus_binop:VI_QHS - (vec_duplicate:VI_QHS - (match_operand: 4 "register_operand" " r, r")) - (match_operand:VI_QHS 3 "register_operand" " vr, vr")) - (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_insn "@pred__scalar" - [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr") - (if_then_else:VI_QHS - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_minus_binop:VI_QHS - (match_operand:VI_QHS 3 "register_operand" " vr, vr") - (vec_duplicate:VI_QHS - (match_operand: 4 "register_operand" " r, r"))) - (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_expand "@pred__scalar" - [(set (match_operand:VI_D 0 "register_operand") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 5 "vector_length_operand") - (match_operand 6 "const_int_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_plus_binop:VI_D - (vec_duplicate:VI_D - (match_operand: 4 "reg_or_int_operand")) - (match_operand:VI_D 3 "register_operand")) - (match_operand:VI_D 2 "vector_merge_operand")))] - "TARGET_VECTOR" - { - if (riscv_vector::has_vi_variant_p (, operands[4])) - operands[4] = force_reg (mode, operands[4]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_ (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - operands[4] = force_reg (mode, operands[4]); - }) - -(define_insn "*pred__scalar" - [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_plus_binop:VI_D - (vec_duplicate:VI_D - (match_operand: 4 "register_operand" " r, r")) - (match_operand:VI_D 3 "register_operand" " vr, vr")) - (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_insn "*pred__extended_scalar" - [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_plus_binop:VI_D - (vec_duplicate:VI_D - (sign_extend: - (match_operand: 4 "register_operand" " r, r"))) - (match_operand:VI_D 3 "register_operand" " vr, vr")) - (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_expand "@pred__scalar" - [(set (match_operand:VI_D 0 "register_operand") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand") - (match_operand 5 "vector_length_operand") - (match_operand 6 "const_int_operand") - (match_operand 7 "const_int_operand") - (match_operand 8 "const_int_operand") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_minus_binop:VI_D - (match_operand:VI_D 3 "register_operand") - (vec_duplicate:VI_D - (match_operand: 4 "reg_or_int_operand"))) - (match_operand:VI_D 2 "vector_merge_operand")))] - "TARGET_VECTOR" - { - if (riscv_vector::has_vi_variant_p (, operands[4])) - operands[4] = force_reg (mode, operands[4]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_ (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - operands[4] = force_reg (mode, operands[4]); - }) - -(define_insn "*pred__scalar" - [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_minus_binop:VI_D - (match_operand:VI_D 3 "register_operand" " vr, vr") - (vec_duplicate:VI_D - (match_operand: 4 "register_operand" " r, r"))) - (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - -(define_insn "*pred__extended_scalar" - [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") - (if_then_else:VI_D - (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (sat_int_minus_binop:VI_D - (match_operand:VI_D 3 "register_operand" " vr, vr") - (vec_duplicate:VI_D - (sign_extend: - (match_operand: 4 "register_operand" " r, r")))) - (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] - "TARGET_VECTOR" - "v.vx\t%0,%3,%4%p1" - [(set_attr "type" "") - (set_attr "mode" "")]) - ;; Multiply High instructions. (define_insn "@pred_mulh" [(set (match_operand:VFULLI 0 "register_operand" "=vd, vr") @@ -3220,12 +2977,255 @@ ;; ---- Predicated fixed-point operations ;; ------------------------------------------------------------------------------- ;; Includes: +;; - 12.1 Vector Single-Width Saturating Add and Subtract ;; - 12.2 Vector Single-Width Aaveraging Add and Subtract ;; - 12.3 Vector Single-Width Fractional Multiply with Rounding and Saturation -;; - 12.5 Vector Single-Width Scaling Shift Instructions -;; - 12.6 Vector Narrowing Fixed-Point Clip Instructions +;; - 12.4 Vector Single-Width Scaling Shift Instructions +;; - 12.5 Vector Narrowing Fixed-Point Clip Instructions ;; ------------------------------------------------------------------------------- +;; Saturating Add and Subtract +(define_insn "@pred_" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1, vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (any_sat_int_binop:VI + (match_operand:VI 3 "" " vr, vr, vr, vr") + (match_operand:VI 4 "" "")) + (match_operand:VI 2 "vector_merge_operand" "0vu,0vu,0vu,0vu")))] + "TARGET_VECTOR" + "@ + v.vv\t%0,%3,%4%p1 + v.vv\t%0,%3,%4%p1 + v\t%0,%p1 + v\t%0,%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode. +(define_insn "@pred__scalar" + [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr") + (if_then_else:VI_QHS + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_plus_binop:VI_QHS + (vec_duplicate:VI_QHS + (match_operand: 4 "register_operand" " r, r")) + (match_operand:VI_QHS 3 "register_operand" " vr, vr")) + (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_insn "@pred__scalar" + [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr") + (if_then_else:VI_QHS + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_minus_binop:VI_QHS + (match_operand:VI_QHS 3 "register_operand" " vr, vr") + (vec_duplicate:VI_QHS + (match_operand: 4 "register_operand" " r, r"))) + (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_expand "@pred__scalar" + [(set (match_operand:VI_D 0 "register_operand") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 5 "vector_length_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_plus_binop:VI_D + (vec_duplicate:VI_D + (match_operand: 4 "reg_or_int_operand")) + (match_operand:VI_D 3 "register_operand")) + (match_operand:VI_D 2 "vector_merge_operand")))] + "TARGET_VECTOR" + { + if (riscv_vector::has_vi_variant_p (, operands[4])) + operands[4] = force_reg (mode, operands[4]); + else if (!TARGET_64BIT) + { + rtx v = gen_reg_rtx (mode); + + if (immediate_operand (operands[4], Pmode)) + operands[4] = gen_rtx_SIGN_EXTEND (mode, + force_reg (Pmode, operands[4])); + else + { + if (CONST_INT_P (operands[4])) + operands[4] = force_reg (mode, operands[4]); + + riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), + v, operands[4], operands[5], mode); + emit_insn (gen_pred_ (operands[0], operands[1], + operands[2], operands[3], v, operands[5], + operands[6], operands[7], operands[8])); + DONE; + } + } + else + operands[4] = force_reg (mode, operands[4]); + }) + +(define_insn "*pred__scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_plus_binop:VI_D + (vec_duplicate:VI_D + (match_operand: 4 "register_operand" " r, r")) + (match_operand:VI_D 3 "register_operand" " vr, vr")) + (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_insn "*pred__extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_plus_binop:VI_D + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 4 "register_operand" " r, r"))) + (match_operand:VI_D 3 "register_operand" " vr, vr")) + (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_expand "@pred__scalar" + [(set (match_operand:VI_D 0 "register_operand") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 5 "vector_length_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_minus_binop:VI_D + (match_operand:VI_D 3 "register_operand") + (vec_duplicate:VI_D + (match_operand: 4 "reg_or_int_operand"))) + (match_operand:VI_D 2 "vector_merge_operand")))] + "TARGET_VECTOR" + { + if (riscv_vector::has_vi_variant_p (, operands[4])) + operands[4] = force_reg (mode, operands[4]); + else if (!TARGET_64BIT) + { + rtx v = gen_reg_rtx (mode); + + if (immediate_operand (operands[4], Pmode)) + operands[4] = gen_rtx_SIGN_EXTEND (mode, + force_reg (Pmode, operands[4])); + else + { + if (CONST_INT_P (operands[4])) + operands[4] = force_reg (mode, operands[4]); + + riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), + v, operands[4], operands[5], mode); + emit_insn (gen_pred_ (operands[0], operands[1], + operands[2], operands[3], v, operands[5], + operands[6], operands[7], operands[8])); + DONE; + } + } + else + operands[4] = force_reg (mode, operands[4]); + }) + +(define_insn "*pred__scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_minus_binop:VI_D + (match_operand:VI_D 3 "register_operand" " vr, vr") + (vec_duplicate:VI_D + (match_operand: 4 "register_operand" " r, r"))) + (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + +(define_insn "*pred__extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (sat_int_minus_binop:VI_D + (match_operand:VI_D 3 "register_operand" " vr, vr") + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 4 "register_operand" " r, r")))) + (match_operand:VI_D 2 "vector_merge_operand" "0vu,0vu")))] + "TARGET_VECTOR" + "v.vx\t%0,%3,%4%p1" + [(set_attr "type" "") + (set_attr "mode" "")]) + (define_insn "@pred_" [(set (match_operand:VI 0 "register_operand" "=vd, vr") (if_then_else:VI