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juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vmadd vx c++ api tests Date: Tue, 14 Feb 2023 22:26:52 +0800 Message-Id: <20230214142652.153982-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757816944583919551?= X-GMAIL-MSGID: =?utf-8?q?1757816944583919551?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-3.C: New test. --- .../riscv/rvv/base/vmadd_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_rv32-1.C | 572 ++++++++++++++++++ .../riscv/rvv/base/vmadd_vx_rv32-2.C | 572 ++++++++++++++++++ .../riscv/rvv/base/vmadd_vx_rv32-3.C | 572 ++++++++++++++++++ .../riscv/rvv/base/vmadd_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv32-3.C | 289 +++++++++ 15 files changed, 5184 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-1.C new file mode 100644 index 00000000000..d5ac5bfd7f9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vmadd_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vmadd_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vmadd_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vmadd_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vmadd_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vmadd_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vmadd_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vmadd_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vmadd_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vmadd_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vmadd_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vmadd_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vmadd_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vmadd_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vmadd_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vmadd_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vmadd_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vmadd_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vmadd_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vmadd_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vmadd_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vmadd_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vmadd_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vmadd_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vmadd_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vmadd_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vmadd_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vmadd_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vmadd_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vmadd_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vmadd_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vmadd_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vmadd_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vmadd_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vmadd_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vmadd_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vmadd_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vmadd_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vmadd_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vmadd_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vmadd_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vmadd_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vmadd_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-2.C new file mode 100644 index 00000000000..005d5a0765c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vmadd_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vmadd_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vmadd_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vmadd_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vmadd_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vmadd_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vmadd_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vmadd_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vmadd_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vmadd_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vmadd_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vmadd_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vmadd_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vmadd_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vmadd_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vmadd_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vmadd_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vmadd_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vmadd_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vmadd_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vmadd_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vmadd_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vmadd_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vmadd_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vmadd_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vmadd_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vmadd_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vmadd_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vmadd_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vmadd_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vmadd_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vmadd_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vmadd_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vmadd_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vmadd_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vmadd_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vmadd_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vmadd_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vmadd_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vmadd_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vmadd_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vmadd_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vmadd_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-3.C new file mode 100644 index 00000000000..3c8fa009636 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vmadd_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vmadd_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vmadd_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vmadd_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vmadd_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vmadd_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vmadd_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vmadd_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vmadd_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vmadd_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vmadd_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vmadd_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vmadd_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vmadd_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vmadd_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vmadd_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vmadd_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vmadd_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vmadd_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vmadd_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vmadd_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vmadd_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vmadd_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vmadd_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vmadd_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vmadd_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vmadd_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vmadd_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vmadd_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vmadd_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vmadd_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vmadd_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vmadd_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vmadd_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vmadd_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vmadd_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vmadd_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vmadd_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vmadd_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vmadd_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vmadd_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vmadd_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vmadd_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_mu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-1.C new file mode 100644 index 00000000000..e4935ca23c7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-1.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vmadd(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vmadd(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vmadd(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vmadd(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vmadd(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vmadd(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vmadd(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vmadd(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vmadd(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vmadd(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vmadd(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vmadd(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vmadd(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vmadd(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vmadd(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vmadd(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vmadd(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vmadd(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vmadd(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vmadd(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vmadd(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vmadd(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vmadd(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vmadd(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vmadd(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vmadd(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vmadd(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vmadd(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vmadd(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vmadd(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vmadd(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vmadd(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vmadd(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vmadd(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vmadd(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vmadd(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vmadd(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vmadd(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vmadd(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vmadd(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vmadd(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vmadd(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vmadd(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,vl); +} + + +vint8mf8_t test___riscv_vmadd(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vmadd(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vmadd(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vmadd(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vmadd(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vmadd(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vmadd(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vmadd(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vmadd(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vmadd(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vmadd(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vmadd(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vmadd(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vmadd(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vmadd(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vmadd(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vmadd(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vmadd(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vmadd(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vmadd(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vmadd(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vmadd(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vmadd(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vmadd(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vmadd(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vmadd(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vmadd(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vmadd(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vmadd(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vmadd(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vmadd(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vmadd(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vmadd(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vmadd(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vmadd(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vmadd(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vmadd(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vmadd(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vmadd(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vmadd(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vmadd(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vmadd(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vmadd(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vmadd(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-2.C new file mode 100644 index 00000000000..24bbb7e976b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-2.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vmadd(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vmadd(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vmadd(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vmadd(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vmadd(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vmadd(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vmadd(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vmadd(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vmadd(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vmadd(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vmadd(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vmadd(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vmadd(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vmadd(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vmadd(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vmadd(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vmadd(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vmadd(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vmadd(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vmadd(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vmadd(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vmadd(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vmadd(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vmadd(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vmadd(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vmadd(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vmadd(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vmadd(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vmadd(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vmadd(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vmadd(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vmadd(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vmadd(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vmadd(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vmadd(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vmadd(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vmadd(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vmadd(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vmadd(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vmadd(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vmadd(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vmadd(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vmadd(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,31); +} + + +vint8mf8_t test___riscv_vmadd(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vmadd(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vmadd(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vmadd(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vmadd(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vmadd(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vmadd(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vmadd(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vmadd(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vmadd(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vmadd(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vmadd(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vmadd(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vmadd(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vmadd(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vmadd(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vmadd(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vmadd(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vmadd(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vmadd(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vmadd(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vmadd(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vmadd(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vmadd(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vmadd(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vmadd(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vmadd(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vmadd(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vmadd(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vmadd(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vmadd(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vmadd(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vmadd(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vmadd(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vmadd(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vmadd(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vmadd(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vmadd(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vmadd(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vmadd(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vmadd(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vmadd(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vmadd(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vmadd(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-3.C new file mode 100644 index 00000000000..4b2c8128593 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv32-3.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vmadd(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vmadd(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vmadd(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vmadd(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vmadd(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vmadd(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vmadd(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vmadd(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vmadd(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vmadd(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vmadd(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vmadd(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vmadd(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vmadd(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vmadd(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vmadd(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vmadd(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vmadd(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vmadd(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vmadd(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vmadd(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vmadd(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vmadd(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vmadd(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vmadd(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vmadd(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vmadd(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vmadd(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vmadd(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vmadd(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vmadd(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vmadd(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vmadd(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vmadd(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vmadd(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vmadd(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vmadd(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vmadd(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vmadd(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vmadd(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vmadd(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vmadd(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vmadd(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(vd,rs1,vs2,32); +} + + +vint8mf8_t test___riscv_vmadd(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vmadd(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vmadd(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vmadd(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vmadd(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vmadd(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vmadd(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vmadd(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vmadd(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vmadd(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vmadd(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vmadd(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vmadd(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vmadd(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vmadd(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vmadd(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vmadd(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vmadd(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vmadd(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vmadd(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vmadd(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vmadd(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vmadd(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vmadd(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vmadd(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vmadd(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vmadd(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vmadd(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vmadd(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vmadd(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vmadd(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vmadd(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vmadd(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vmadd(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vmadd(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vmadd(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vmadd(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vmadd(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vmadd(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vmadd(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vmadd(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vmadd(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vmadd(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vmadd(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-1.C new file mode 100644 index 00000000000..7a777bf23f8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vmadd_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vmadd_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vmadd_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vmadd_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vmadd_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vmadd_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vmadd_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vmadd_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vmadd_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vmadd_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vmadd_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vmadd_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vmadd_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vmadd_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vmadd_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vmadd_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vmadd_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vmadd_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vmadd_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vmadd_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vmadd_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vmadd_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vmadd_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vmadd_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vmadd_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vmadd_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vmadd_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vmadd_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vmadd_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vmadd_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vmadd_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vmadd_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vmadd_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vmadd_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vmadd_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vmadd_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vmadd_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vmadd_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vmadd_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vmadd_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vmadd_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vmadd_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vmadd_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-2.C new file mode 100644 index 00000000000..3022fbaef54 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vmadd_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vmadd_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vmadd_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vmadd_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vmadd_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vmadd_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vmadd_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vmadd_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vmadd_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vmadd_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vmadd_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vmadd_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vmadd_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vmadd_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vmadd_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vmadd_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vmadd_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vmadd_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vmadd_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vmadd_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vmadd_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vmadd_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vmadd_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vmadd_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vmadd_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vmadd_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vmadd_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vmadd_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vmadd_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vmadd_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vmadd_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vmadd_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vmadd_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vmadd_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vmadd_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vmadd_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vmadd_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vmadd_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vmadd_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vmadd_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vmadd_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vmadd_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vmadd_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-3.C new file mode 100644 index 00000000000..a7efe2630c6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vmadd_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vmadd_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vmadd_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vmadd_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vmadd_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vmadd_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vmadd_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vmadd_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vmadd_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vmadd_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vmadd_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vmadd_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vmadd_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vmadd_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vmadd_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vmadd_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vmadd_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vmadd_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vmadd_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vmadd_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vmadd_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vmadd_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vmadd_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vmadd_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vmadd_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vmadd_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vmadd_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vmadd_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vmadd_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vmadd_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vmadd_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vmadd_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vmadd_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vmadd_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vmadd_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vmadd_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vmadd_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vmadd_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vmadd_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vmadd_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vmadd_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vmadd_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vmadd_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tu(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-1.C new file mode 100644 index 00000000000..36fd97e9f56 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vmadd_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vmadd_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vmadd_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vmadd_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vmadd_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vmadd_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vmadd_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vmadd_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vmadd_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vmadd_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vmadd_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vmadd_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vmadd_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vmadd_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vmadd_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vmadd_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vmadd_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vmadd_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vmadd_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vmadd_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vmadd_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vmadd_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vmadd_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vmadd_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vmadd_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vmadd_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vmadd_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vmadd_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vmadd_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vmadd_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vmadd_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vmadd_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vmadd_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vmadd_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vmadd_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vmadd_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vmadd_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vmadd_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vmadd_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vmadd_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vmadd_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vmadd_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vmadd_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-2.C new file mode 100644 index 00000000000..a41dfd29bec --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vmadd_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vmadd_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vmadd_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vmadd_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vmadd_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vmadd_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vmadd_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vmadd_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vmadd_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vmadd_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vmadd_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vmadd_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vmadd_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vmadd_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vmadd_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vmadd_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vmadd_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vmadd_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vmadd_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vmadd_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vmadd_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vmadd_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vmadd_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vmadd_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vmadd_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vmadd_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vmadd_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vmadd_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vmadd_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vmadd_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vmadd_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vmadd_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vmadd_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vmadd_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vmadd_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vmadd_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vmadd_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vmadd_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vmadd_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vmadd_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vmadd_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vmadd_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vmadd_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-3.C new file mode 100644 index 00000000000..de46d6c91be --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vmadd_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vmadd_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vmadd_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vmadd_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vmadd_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vmadd_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vmadd_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vmadd_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vmadd_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vmadd_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vmadd_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vmadd_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vmadd_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vmadd_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vmadd_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vmadd_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vmadd_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vmadd_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vmadd_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vmadd_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vmadd_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vmadd_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vmadd_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vmadd_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vmadd_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vmadd_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vmadd_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vmadd_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vmadd_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vmadd_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vmadd_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vmadd_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vmadd_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vmadd_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vmadd_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vmadd_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vmadd_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vmadd_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vmadd_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vmadd_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vmadd_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vmadd_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vmadd_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tum(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-1.C new file mode 100644 index 00000000000..582d92bdf09 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vmadd_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vmadd_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vmadd_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vmadd_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vmadd_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vmadd_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vmadd_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vmadd_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vmadd_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vmadd_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vmadd_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vmadd_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vmadd_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vmadd_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vmadd_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vmadd_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vmadd_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vmadd_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vmadd_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vmadd_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vmadd_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vmadd_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vmadd_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vmadd_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vmadd_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vmadd_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vmadd_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vmadd_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vmadd_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vmadd_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vmadd_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vmadd_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vmadd_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vmadd_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vmadd_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vmadd_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vmadd_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vmadd_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vmadd_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vmadd_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vmadd_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vmadd_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vmadd_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-2.C new file mode 100644 index 00000000000..9957fe19c2a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vmadd_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vmadd_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vmadd_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vmadd_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vmadd_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vmadd_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vmadd_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vmadd_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vmadd_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vmadd_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vmadd_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vmadd_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vmadd_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vmadd_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vmadd_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vmadd_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vmadd_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vmadd_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vmadd_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vmadd_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vmadd_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vmadd_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vmadd_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vmadd_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vmadd_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vmadd_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vmadd_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vmadd_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vmadd_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vmadd_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vmadd_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vmadd_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vmadd_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vmadd_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vmadd_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vmadd_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vmadd_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vmadd_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vmadd_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vmadd_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vmadd_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vmadd_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vmadd_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-3.C new file mode 100644 index 00000000000..b550c161c57 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmadd_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vmadd_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vmadd_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vmadd_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vmadd_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vmadd_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vmadd_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vmadd_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vmadd_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vmadd_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vmadd_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vmadd_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vmadd_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vmadd_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vmadd_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vmadd_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vmadd_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vmadd_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vmadd_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vmadd_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vmadd_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vmadd_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vmadd_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vmadd_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vmadd_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vmadd_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vmadd_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vmadd_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vmadd_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vmadd_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vmadd_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vmadd_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vmadd_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vmadd_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vmadd_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vmadd_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vmadd_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vmadd_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vmadd_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vmadd_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vmadd_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vmadd_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vmadd_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vmadd_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vmadd_tumu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */