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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f14-20020aa7d84e000000b004acc76bcbcesi3924012eds.347.2023.02.13.10.31.03; Mon, 13 Feb 2023 10:31:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=W3erahJv; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231365AbjBMS1H (ORCPT + 99 others); Mon, 13 Feb 2023 13:27:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230290AbjBMS03 (ORCPT ); Mon, 13 Feb 2023 13:26:29 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A0731BE1; Mon, 13 Feb 2023 10:26:28 -0800 (PST) Date: Mon, 13 Feb 2023 18:26:25 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1676312785; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aCeIpvBuI/KuD1iDI3eiTg1JWPXNIEngQeFvUSbgV2A=; b=W3erahJvO+obxIy4G4ruF7MqOfHcN1qTGEdBISglzre7SNDP0kIUzvK1+zrSVn7kXu+tBI t7qwCvMAS26nU0Z9vbuCXjevIoM+eQQz7XaqMK73R9jXY5FOazxJ/yJUJ289G0v1PLxe/2 SnncoOe3TZHEdcGp8ju3NgkBeiuJh7OAd2uUeOu2zgLlsLTFqVanhqTz5BzapWlZ0eD47J t251UCbdgFvJppcM4yMp8DQU42qS/ndOHddV5BSENMMrLUsdsM0WLID7iq9+2+QaBlIvXY orWlwsZfzA9fnYAnckq3r0r4jV85S5gDL6fO7gsnxFaqD0zNBksnGUZZiHUEjQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1676312785; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aCeIpvBuI/KuD1iDI3eiTg1JWPXNIEngQeFvUSbgV2A=; b=XCf6XYKkuxGmpHXEGsBau9GQV1pkIF9/j8qy16g5DOeWhdoxV9hAYfk2pacKsA/h8WU9fj TeJoH3C5eU1MjkCw== From: "tip-bot2 for Anup Patel" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/core] dt-bindings: timer: Add bindings for the RISC-V timer device Cc: Anup Patel , Conor Dooley , Rob Herring , Palmer Dabbelt , Daniel Lezcano , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230103141102.772228-3-apatel@ventanamicro.com> References: <20230103141102.772228-3-apatel@ventanamicro.com> MIME-Version: 1.0 Message-ID: <167631278506.4906.15498041035078946448.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754010890220942694?= X-GMAIL-MSGID: =?utf-8?q?1757741671097990466?= The following commit has been merged into the timers/core branch of tip: Commit-ID: e2bcf2d876fd7ca6ecca09794ac58d7e3a544794 Gitweb: https://git.kernel.org/tip/e2bcf2d876fd7ca6ecca09794ac58d7e3a544794 Author: Anup Patel AuthorDate: Tue, 03 Jan 2023 19:41:01 +05:30 Committer: Daniel Lezcano CommitterDate: Mon, 13 Feb 2023 13:10:16 +01:00 dt-bindings: timer: Add bindings for the RISC-V timer device We add DT bindings for a separate RISC-V timer DT node which can be used to describe implementation specific behaviour (such as timer interrupt not triggered during non-retentive suspend). Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20230103141102.772228-3-apatel@ventanamicro.com Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/riscv,timer.yaml | 52 +++++++- 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml new file mode 100644 index 0000000..38d67e1 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V timer + +maintainers: + - Anup Patel + +description: |+ + RISC-V platforms always have a RISC-V timer device for the supervisor-mode + based on the time CSR defined by the RISC-V privileged specification. The + timer interrupts of this device are configured using the RISC-V SBI Time + extension or the RISC-V Sstc extension. + + The clock frequency of RISC-V timer device is specified via the + "timebase-frequency" DT property of "/cpus" DT node which is described + in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + enum: + - riscv,timer + + interrupts-extended: + minItems: 1 + maxItems: 4096 # Should be enough? + + riscv,timer-cannot-wake-cpu: + type: boolean + description: + If present, the timer interrupt cannot wake up the CPU from one or + more suspend/idle states. + +additionalProperties: false + +required: + - compatible + - interrupts-extended + +examples: + - | + timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu1intc 5>, + <&cpu2intc 5>, + <&cpu3intc 5>, + <&cpu4intc 5>; + }; +...