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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id b11-20020aa7c6cb000000b004acc84ce543si1943050eds.432.2023.02.12.23.46.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Feb 2023 23:46:17 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 28F9D385B50D for ; Mon, 13 Feb 2023 07:46:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id DC2503858D33 for ; Mon, 13 Feb 2023 07:45:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC2503858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp70t1676274327tvwd2846 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 13 Feb 2023 15:45:26 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: XX3wW3LoJSD2XmT4Mf+H/cTXjBlohnt6q0oaJAW8Fz3uPy2Y43sPKr3+iOUaL Ck3WfyV+ppvrvjS2DUb286NcAFpIaF8ue93D8FUff394S99qjlWANGKujrS8NEbAJjujeX1 vhVAfCqmZGlkoLVD5Xhv9xUCwhyt29VwVTy+G0ROAzFZ89EtXLq2SmKPHRq/1YW3wfshNlw up+3yHkundAWnYzqnJu5zjcFBSgIDYPRj9VPH8/REUyQEVG2KgIONJ9f9qtL9QNIKnDy/+t JaXD4/EEubAiF683lEAGd/5jYOt7SAyKEU1t77oC5XR7nCFTGWDLRHRWnpW7ufXoaj5f5Am C4lIq4ldbWxWd7wKbNh9w0VsrIdBb343rEV7i4loPA/dfE8chJIN71pIusCEw== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vmsne vv C api tests Date: Mon, 13 Feb 2023 15:45:25 +0800 Message-Id: <20230213074525.268358-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757701082041546487?= X-GMAIL-MSGID: =?utf-8?q?1757701082041546487?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vmsne_vv-1.c: New test. * gcc.target/riscv/rvv/base/vmsne_vv-2.c: New test. * gcc.target/riscv/rvv/base/vmsne_vv-3.c: New test. * gcc.target/riscv/rvv/base/vmsne_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vmsne_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vmsne_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vmsne_vv-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv-3.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_m-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_m-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_m-3.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c | 292 ++++++++++++++++++ 9 files changed, 2628 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-1.c new file mode 100644 index 00000000000..b0599b34ea8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsne_vv_i8mf8_b64(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf8_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i8mf4_b32(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf4_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i8mf2_b16(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i8m1_b8(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m1_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_i8m2_b4(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m2_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_i8m4_b2(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m4_b2(op1,op2,vl); +} + + +vbool1_t test___riscv_vmsne_vv_i8m8_b1(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m8_b1(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_i16mf4_b64(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf4_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i16mf2_b32(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i16m1_b16(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m1_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i16m2_b8(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m2_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_i16m4_b4(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m4_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_i16m8_b2(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m8_b2(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_i32mf2_b64(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32mf2_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i32m1_b32(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m1_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i32m2_b16(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i32m4_b8(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m4_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_i32m8_b4(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m8_b4(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_i64m1_b64(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m1_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i64m2_b32(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i64m4_b16(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m4_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i64m8_b8(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m8_b8(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u8mf8_b64(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf8_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u8mf4_b32(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf4_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u8mf2_b16(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u8m1_b8(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m1_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_u8m2_b4(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m2_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_u8m4_b2(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m4_b2(op1,op2,vl); +} + + +vbool1_t test___riscv_vmsne_vv_u8m8_b1(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m8_b1(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u16mf4_b64(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf4_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u16mf2_b32(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u16m1_b16(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m1_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u16m2_b8(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m2_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_u16m4_b4(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m4_b4(op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_u16m8_b2(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m8_b2(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u32mf2_b64(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32mf2_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u32m1_b32(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m1_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u32m2_b16(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m2_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u32m4_b8(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m4_b8(op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_u32m8_b4(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m8_b4(op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u64m1_b64(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m1_b64(op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u64m2_b32(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m2_b32(op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u64m4_b16(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m4_b16(op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u64m8_b8(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m8_b8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-2.c new file mode 100644 index 00000000000..e0566ff34e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsne_vv_i8mf8_b64(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf8_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i8mf4_b32(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf4_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i8mf2_b16(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i8m1_b8(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m1_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_i8m2_b4(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m2_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_i8m4_b2(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m4_b2(op1,op2,31); +} + + +vbool1_t test___riscv_vmsne_vv_i8m8_b1(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m8_b1(op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_i16mf4_b64(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf4_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i16mf2_b32(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i16m1_b16(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m1_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i16m2_b8(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m2_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_i16m4_b4(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m4_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_i16m8_b2(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m8_b2(op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_i32mf2_b64(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32mf2_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i32m1_b32(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m1_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i32m2_b16(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i32m4_b8(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m4_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_i32m8_b4(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m8_b4(op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_i64m1_b64(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m1_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i64m2_b32(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i64m4_b16(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m4_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i64m8_b8(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m8_b8(op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u8mf8_b64(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf8_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u8mf4_b32(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf4_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u8mf2_b16(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u8m1_b8(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m1_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_u8m2_b4(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m2_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_u8m4_b2(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m4_b2(op1,op2,31); +} + + +vbool1_t test___riscv_vmsne_vv_u8m8_b1(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m8_b1(op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u16mf4_b64(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf4_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u16mf2_b32(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u16m1_b16(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m1_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u16m2_b8(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m2_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_u16m4_b4(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m4_b4(op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_u16m8_b2(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m8_b2(op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u32mf2_b64(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32mf2_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u32m1_b32(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m1_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u32m2_b16(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m2_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u32m4_b8(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m4_b8(op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_u32m8_b4(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m8_b4(op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u64m1_b64(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m1_b64(op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u64m2_b32(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m2_b32(op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u64m4_b16(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m4_b16(op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u64m8_b8(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m8_b8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-3.c new file mode 100644 index 00000000000..36d315178a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsne_vv_i8mf8_b64(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf8_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i8mf4_b32(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf4_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i8mf2_b16(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i8m1_b8(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m1_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_i8m2_b4(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m2_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_i8m4_b2(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m4_b2(op1,op2,32); +} + + +vbool1_t test___riscv_vmsne_vv_i8m8_b1(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m8_b1(op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_i16mf4_b64(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf4_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i16mf2_b32(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i16m1_b16(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m1_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i16m2_b8(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m2_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_i16m4_b4(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m4_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_i16m8_b2(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m8_b2(op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_i32mf2_b64(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32mf2_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i32m1_b32(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m1_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i32m2_b16(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i32m4_b8(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m4_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_i32m8_b4(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m8_b4(op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_i64m1_b64(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m1_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i64m2_b32(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i64m4_b16(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m4_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i64m8_b8(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m8_b8(op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u8mf8_b64(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf8_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u8mf4_b32(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf4_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u8mf2_b16(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u8m1_b8(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m1_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_u8m2_b4(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m2_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_u8m4_b2(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m4_b2(op1,op2,32); +} + + +vbool1_t test___riscv_vmsne_vv_u8m8_b1(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m8_b1(op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u16mf4_b64(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf4_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u16mf2_b32(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u16m1_b16(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m1_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u16m2_b8(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m2_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_u16m4_b4(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m4_b4(op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_u16m8_b2(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m8_b2(op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u32mf2_b64(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32mf2_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u32m1_b32(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m1_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u32m2_b16(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m2_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u32m4_b8(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m4_b8(op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_u32m8_b4(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m8_b4(op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u64m1_b64(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m1_b64(op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u64m2_b32(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m2_b32(op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u64m4_b16(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m4_b16(op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u64m8_b8(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m8_b8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-1.c new file mode 100644 index 00000000000..113fbe72215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsne_vv_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf8_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf4_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m1_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m2_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m4_b2_m(mask,op1,op2,vl); +} + + +vbool1_t test___riscv_vmsne_vv_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m8_b1_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf4_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m1_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m2_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m4_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m8_b2_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32mf2_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m1_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m4_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m8_b4_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m1_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m4_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m8_b8_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf8_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf4_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m1_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m2_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m4_b2_m(mask,op1,op2,vl); +} + + +vbool1_t test___riscv_vmsne_vv_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m8_b1_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf4_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m1_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m2_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m4_b4_m(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m8_b2_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32mf2_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m1_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m2_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m4_b8_m(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m8_b4_m(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m1_b64_m(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m2_b32_m(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m4_b16_m(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m8_b8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-2.c new file mode 100644 index 00000000000..dd7ccad63d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsne_vv_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf8_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf4_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m1_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m2_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m4_b2_m(mask,op1,op2,31); +} + + +vbool1_t test___riscv_vmsne_vv_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m8_b1_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf4_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m1_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m2_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m4_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m8_b2_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32mf2_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m1_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m4_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m8_b4_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m1_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m4_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m8_b8_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf8_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf4_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m1_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m2_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m4_b2_m(mask,op1,op2,31); +} + + +vbool1_t test___riscv_vmsne_vv_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m8_b1_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf4_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m1_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m2_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m4_b4_m(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m8_b2_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32mf2_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m1_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m2_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m4_b8_m(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m8_b4_m(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m1_b64_m(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m2_b32_m(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m4_b16_m(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m8_b8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-3.c new file mode 100644 index 00000000000..73ec33aa141 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsne_vv_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf8_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf4_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m1_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m2_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m4_b2_m(mask,op1,op2,32); +} + + +vbool1_t test___riscv_vmsne_vv_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m8_b1_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf4_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m1_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m2_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m4_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m8_b2_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32mf2_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m1_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m4_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m8_b4_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m1_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m4_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m8_b8_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf8_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf4_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m1_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m2_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m4_b2_m(mask,op1,op2,32); +} + + +vbool1_t test___riscv_vmsne_vv_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m8_b1_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf4_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m1_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m2_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m4_b4_m(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m8_b2_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32mf2_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m1_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m2_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m4_b8_m(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m8_b4_m(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m1_b64_m(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m2_b32_m(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m4_b16_m(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m8_b8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c new file mode 100644 index 00000000000..337f52dcbf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsne_vv_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf8_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf4_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m1_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m2_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m4_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool1_t test___riscv_vmsne_vv_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m8_b1_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf4_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m1_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m2_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m4_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m8_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32mf2_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m1_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m4_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m8_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m1_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m4_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m8_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf8_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf4_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m1_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m2_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m4_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool1_t test___riscv_vmsne_vv_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m8_b1_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf4_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m1_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m2_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m4_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmsne_vv_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m8_b2_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32mf2_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m1_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m2_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m4_b8_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmsne_vv_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m8_b4_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmsne_vv_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m1_b64_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmsne_vv_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m2_b32_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmsne_vv_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m4_b16_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmsne_vv_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m8_b8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c new file mode 100644 index 00000000000..8467d4dd4c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsne_vv_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf8_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf4_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m1_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m2_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m4_b2_mu(mask,merge,op1,op2,31); +} + + +vbool1_t test___riscv_vmsne_vv_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m8_b1_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf4_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m1_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m2_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m4_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m8_b2_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32mf2_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m1_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m4_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m8_b4_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m1_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m4_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m8_b8_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf8_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf4_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m1_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m2_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m4_b2_mu(mask,merge,op1,op2,31); +} + + +vbool1_t test___riscv_vmsne_vv_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m8_b1_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf4_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m1_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m2_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m4_b4_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmsne_vv_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m8_b2_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32mf2_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m1_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m2_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m4_b8_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmsne_vv_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m8_b4_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmsne_vv_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m1_b64_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmsne_vv_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m2_b32_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmsne_vv_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m4_b16_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmsne_vv_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m8_b8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c new file mode 100644 index 00000000000..c43619e49d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmsne_vv_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf8_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf4_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8mf2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m1_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m2_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m4_b2_mu(mask,merge,op1,op2,32); +} + + +vbool1_t test___riscv_vmsne_vv_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i8m8_b1_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf4_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16mf2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m1_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m2_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m4_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i16m8_b2_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32mf2_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m1_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m4_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i32m8_b4_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m1_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m4_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_i64m8_b8_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf8_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf4_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8mf2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m1_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m2_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m4_b2_mu(mask,merge,op1,op2,32); +} + + +vbool1_t test___riscv_vmsne_vv_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u8m8_b1_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf4_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16mf2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m1_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m2_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m4_b4_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmsne_vv_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u16m8_b2_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32mf2_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m1_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m2_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m4_b8_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmsne_vv_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u32m8_b4_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmsne_vv_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m1_b64_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmsne_vv_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m2_b32_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmsne_vv_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m4_b16_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmsne_vv_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmsne_vv_u64m8_b8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsne\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */