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[2620:137:e000::1:20]) by mx.google.com with ESMTP id k23-20020aa7d8d7000000b004ab25429876si5838034eds.240.2023.02.11.03.04.41; Sat, 11 Feb 2023 03:05:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KmkdO2o7; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229535AbjBKKi1 (ORCPT + 99 others); Sat, 11 Feb 2023 05:38:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229457AbjBKKi0 (ORCPT ); Sat, 11 Feb 2023 05:38:26 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD3641F93A; Sat, 11 Feb 2023 02:38:24 -0800 (PST) Date: Sat, 11 Feb 2023 10:38:22 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1676111903; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=QSrG8FFwfsx4nvntDnzdp1Gs9dEYdlpmf7UcE2p/kGg=; b=KmkdO2o7DWqtmTs/CfwvasJJuKEU0N8CLznRDJYnbMnWQq9S8T9dQBe8Ipw0c+PimgSdtX SnvGSDT/qqq/3wqmKO6yeDFT6G0f7Bku1gDamPSGJr+NgFUwgbyfZirbNdBZ3UhYrf+jDJ 211TWJRMamal1WRs/lc3wZ0iB9JL95La8XpC7bD3Lf21VCwGiiDPuBSiAEImAw181P4cA/ /40SbjcisCTKZXd+mkjRvCX4cEDAPHpkPW+sVh0WfAtvxVim1ya+xpTealflyh+tnFYYZs Roh5Q3QD5nq11Oa6Hi0lEAOIZLMFB4+YB41U7GgIoVnQNi4c/JCxZ0JToHRMOQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1676111903; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=QSrG8FFwfsx4nvntDnzdp1Gs9dEYdlpmf7UcE2p/kGg=; b=6HBBZ1g/eJggwOniAeVvuJv6bkIJUdZtq2oaGsdWZ3iF7RtSpI7uvyJ7gN2iC3FC0/7gGH yQqNQmfUxoRngGBg== From: "tip-bot2 for silviazhao" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] x86/perf/zhaoxin: Add stepping check for ZXC Cc: Arjan <8vvbbqzo567a@nospam.xutrox.com>, Kevin Brace , silviazhao , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Message-ID: <167611190278.4906.4557467380127146450.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757532394669223943?= X-GMAIL-MSGID: =?utf-8?q?1757532394669223943?= The following commit has been merged into the perf/core branch of tip: Commit-ID: fd636b6a9bc6034f2e5bb869658898a2b472c037 Gitweb: https://git.kernel.org/tip/fd636b6a9bc6034f2e5bb869658898a2b472c037 Author: silviazhao AuthorDate: Wed, 08 Feb 2023 16:27:22 +08:00 Committer: Peter Zijlstra CommitterDate: Sat, 11 Feb 2023 11:18:12 +01:00 x86/perf/zhaoxin: Add stepping check for ZXC Some of Nano series processors will lead GP when accessing PMC fixed counter. Meanwhile, their hardware support for PMC has not announced externally. So exclude Nano CPUs from ZXC by checking stepping information. This is an unambiguous way to differentiate between ZXC and Nano CPUs. Following are Nano and ZXC FMS information: Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D] ZXC FMS: Family=6, Model=F, Stepping=E-F OR Family=6, Model=0x19, Stepping=0-3 Fixes: 3a4ac121c2ca ("x86/perf: Add hardware performance events support for Zhaoxin CPU.") Reported-by: Arjan <8vvbbqzo567a@nospam.xutrox.com> Reported-by: Kevin Brace Signed-off-by: silviazhao Signed-off-by: Peter Zijlstra (Intel) Link: https://bugzilla.kernel.org/show_bug.cgi?id=212389 --- arch/x86/events/zhaoxin/core.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c index 949d845..3e9acda 100644 --- a/arch/x86/events/zhaoxin/core.c +++ b/arch/x86/events/zhaoxin/core.c @@ -541,7 +541,13 @@ __init int zhaoxin_pmu_init(void) switch (boot_cpu_data.x86) { case 0x06: - if (boot_cpu_data.x86_model == 0x0f || boot_cpu_data.x86_model == 0x19) { + /* + * Support Zhaoxin CPU from ZXC series, exclude Nano series through FMS. + * Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D] + * ZXC FMS: Family=6, Model=F, Stepping=E-F OR Family=6, Model=0x19, Stepping=0-3 + */ + if ((boot_cpu_data.x86_model == 0x0f && boot_cpu_data.x86_stepping >= 0x0e) || + boot_cpu_data.x86_model == 0x19) { x86_pmu.max_period = x86_pmu.cntval_mask >> 1;