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Outside of 64-bit mode all 4 insns can have the data size prefix dropped in certain cases. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4362,6 +4362,42 @@ optimize_encoding (void) */ i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); } + else if (i.tm.base_opcode == 0xba + && i.tm.opcode_space == SPACE_0F + && i.reg_operands == 1 + && i.op[0].imms->X_op == O_constant + && i.op[0].imms->X_add_number >= 0) + { + /* Optimize: -O: + btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16) + btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8) + btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) + + With one of bts, btr, and bts also: + w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16) + l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) + */ + switch (flag_code) + { + case CODE_64BIT: + if (i.tm.extension_opcode != 4) + break; + if (i.types[1].bitfield.qword + && i.op[0].imms->X_add_number < 32 + && !(i.op[1].regs->reg_flags & RegRex)) + i.tm.opcode_modifier.size = SIZE32; + /* Fall through. */ + case CODE_32BIT: + if (i.types[1].bitfield.word + && i.op[0].imms->X_add_number < 16) + i.tm.opcode_modifier.size = SIZE32; + break; + case CODE_16BIT: + if (i.op[0].imms->X_add_number < 16) + i.tm.opcode_modifier.size = SIZE16; + break; + } + } else if (i.reg_operands == 3 && i.op[0].regs == i.op[1].regs && !i.types[2].bitfield.xmmword --- a/gas/testsuite/gas/i386/optimize-1.d +++ b/gas/testsuite/gas/i386/optimize-1.d @@ -147,4 +147,14 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax + +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax + +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax + +[a-f0-9]+: 0f ba f0 0f btr \$0xf,%eax + +[a-f0-9]+: 0f ba e8 0f bts \$0xf,%eax + +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax + +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax + +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax + +[a-f0-9]+: 0f ba f0 0f btr \$0xf,%eax + +[a-f0-9]+: 0f ba e8 0f bts \$0xf,%eax #pass --- a/gas/testsuite/gas/i386/optimize-1.s +++ b/gas/testsuite/gas/i386/optimize-1.s @@ -170,3 +170,16 @@ _start: vporq 128(%eax), %ymm2, %ymm3 vpxord 128(%eax), %ymm2, %ymm3 vpxorq 128(%eax), %ymm2, %ymm3 + + bt $15, %ax + bt $16, %ax + btc $15, %ax + btr $15, %ax + bts $15, %ax + + .code16 + bt $15, %eax + bt $16, %eax + btc $15, %eax + btr $15, %eax + bts $15, %eax --- a/gas/testsuite/gas/i386/optimize-1a.d +++ b/gas/testsuite/gas/i386/optimize-1a.d @@ -148,4 +148,14 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax + +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax + +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax + +[a-f0-9]+: 0f ba f0 0f btr \$0xf,%eax + +[a-f0-9]+: 0f ba e8 0f bts \$0xf,%eax + +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax + +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax + +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax + +[a-f0-9]+: 0f ba f0 0f btr \$0xf,%eax + +[a-f0-9]+: 0f ba e8 0f bts \$0xf,%eax #pass --- a/gas/testsuite/gas/i386/optimize-4.d +++ b/gas/testsuite/gas/i386/optimize-4.d @@ -147,6 +147,16 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax + +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax + +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax + +[a-f0-9]+: 0f ba f0 0f btr \$0xf,%eax + +[a-f0-9]+: 0f ba e8 0f bts \$0xf,%eax + +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax + +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax + +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax + +[a-f0-9]+: 0f ba f0 0f btr \$0xf,%eax + +[a-f0-9]+: 0f ba e8 0f bts \$0xf,%eax +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5 +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5 #pass --- a/gas/testsuite/gas/i386/optimize-5.d +++ b/gas/testsuite/gas/i386/optimize-5.d @@ -147,6 +147,16 @@ Disassembly of section .text: +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3 + +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax + +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax + +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax + +[a-f0-9]+: 0f ba f0 0f btr \$0xf,%eax + +[a-f0-9]+: 0f ba e8 0f bts \$0xf,%eax + +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax + +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax + +[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax + +[a-f0-9]+: 0f ba f0 0f btr \$0xf,%eax + +[a-f0-9]+: 0f ba e8 0f bts \$0xf,%eax +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5 +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5 +[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2 --- a/gas/testsuite/gas/i386/x86-64-optimize-1.d +++ b/gas/testsuite/gas/i386/x86-64-optimize-1.d @@ -58,4 +58,17 @@ Disassembly of section .text: +[a-f0-9]+: 48 b8 00 00 00 00 01 00 00 00 movabs \$0x100000000,%rax +[a-f0-9]+: 31 c0 xor %eax,%eax +[a-f0-9]+: 45 31 f6 xor %r14d,%r14d + +[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax + +[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax + +[a-f0-9]+: 41 0f ba e0 0f bt \$0xf,%r8d + +[a-f0-9]+: 66 41 0f ba e0 10 bt \$0x10,%r8w + +[a-f0-9]+: 0f ba e0 1f bt \$0x1f,%eax + +[a-f0-9]+: 48 0f ba e0 20 bt \$0x20,%rax + +[a-f0-9]+: 49 0f ba e0 1f bt \$0x1f,%r8 + +[a-f0-9]+: 66 0f ba f8 0f btc \$0xf,%ax + +[a-f0-9]+: 48 0f ba f8 1f btc \$0x1f,%rax + +[a-f0-9]+: 66 0f ba f0 0f btr \$0xf,%ax + +[a-f0-9]+: 48 0f ba f0 1f btr \$0x1f,%rax + +[a-f0-9]+: 66 0f ba e8 0f bts \$0xf,%ax + +[a-f0-9]+: 48 0f ba e8 1f bts \$0x1f,%rax #pass --- a/gas/testsuite/gas/i386/x86-64-optimize-1.s +++ b/gas/testsuite/gas/i386/x86-64-optimize-1.s @@ -53,3 +53,16 @@ _start: movq $0x100000000,%rax clrq %rax clrq %r14 + bt $15, %ax + bt $16, %ax + bt $15, %r8w + bt $16, %r8w + bt $31, %rax + bt $32, %rax + bt $31, %r8 + btc $15, %ax + btc $31, %rax + btr $15, %ax + btr $31, %rax + bts $15, %ax + bts $31, %rax --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -536,13 +536,13 @@ xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|N bsf, 0xfbc, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } bsr, 0xfbd, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } bt, 0xfa3, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -bt, 0xfba/4, i386, Modrm|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bt, 0xfba/4, i386, Modrm|No_bSuf|No_sSuf|Optimize, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } btc, 0xfbb, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btc, 0xfba/7, i386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btc, 0xfba/7, i386, Modrm|No_bSuf|No_sSuf|Optimize|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } btr, 0xfb3, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -btr, 0xfba/6, i386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +btr, 0xfba/6, i386, Modrm|No_bSuf|No_sSuf|Optimize|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } bts, 0xfab, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } -bts, 0xfba/5, i386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +bts, 0xfba/5, i386, Modrm|No_bSuf|No_sSuf|Optimize|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Unspecified|BaseIndex } // Interrupts & op. sys insns. // See gas/config/tc-i386.c for conversion of 'int $3' into the special From patchwork Fri Feb 10 08:36:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 55315 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp831383wrn; Fri, 10 Feb 2023 00:37:04 -0800 (PST) X-Google-Smtp-Source: AK7set9cSSA1CHJxJMZBsvSZjCR8tHCuZnfN/LcQgseUee0JffYH/Gm+QQdOVvB3rBGvt+juiqJu X-Received: by 2002:a17:907:6e17:b0:8af:2af5:1191 with SMTP id sd23-20020a1709076e1700b008af2af51191mr8647095ejc.18.1676018224201; Fri, 10 Feb 2023 00:37:04 -0800 (PST) Received: from sourceware.org (server2.sourceware.org. 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An extreme example would be the two rotate-through-carry insns, where a negative value would _not_ mean rotating the corresponding number of bits in the other direction. To refuse such, give meaning to the combination of Imm8 and Imm8S in templates (so far these weren't used together anywhere). The issue was with smallest_imm_type() blindly setting .imm8 for signed numbers determined to fit in a byte. VPROT{B,W,D,Q} is a little special: The rotate count there is a signed quantity, so Imm8 is replaced by Imm8S. Adjust affected testcases accordingly as well. Another small adjustment to the testsuite is necessary: AAM and AAD were never sensible to use with 0xffffff90 operands. This should have been an error. --- Questionable: {,V}CMP{P,S}{S,D,H}, VPCMP{,U}{B,W,D,Q}, VPCOM{,U}{B,W,D,Q}, {,V}ROUND{P,S}{S,D}, {,V}PCMP{E,I}STR{I,M}, {,V}AESKEYGENASSIST, {,V}GF2P8AFFINE{,INV}QB, VCVTPS2PH, XABORT, HRESET, VGETMANT{P,S}{S,D,H}, and VRANGE{P,S}{S,D}. I've left these alone for now. Yet even beyond those I'm up for being convinced to permit negative immediates for further insns, just as long as RCL/RCR don't. (VPERMIL2P{S,D} obviously shouldn't, as they're really restricted to unsigned 4-bit immediates.) --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2373,7 +2373,8 @@ smallest_imm_type (offsetT num) } else if (fits_in_signed_byte (num)) { - t.bitfield.imm8 = 1; + if (fits_in_unsigned_byte (num)) + t.bitfield.imm8 = 1; t.bitfield.imm8s = 1; t.bitfield.imm16 = 1; t.bitfield.imm32 = 1; @@ -7829,6 +7830,18 @@ static int update_imm (unsigned int j) { i386_operand_type overlap = i.types[j]; + + if (i.tm.operand_types[j].bitfield.imm8 + && i.tm.operand_types[j].bitfield.imm8s + && overlap.bitfield.imm8 && overlap.bitfield.imm8s) + { + /* This combination is used on 8-bit immediates where e.g. $~0 is + desirable to permit. We're past operand type matching, so simply + put things back in the shape they were before introducing the + distinction between Imm8, Imm8S, and Imm8|Imm8S. */ + overlap.bitfield.imm8s = 0; + } + if (overlap.bitfield.imm8 + overlap.bitfield.imm8s + overlap.bitfield.imm16 @@ -8318,6 +8331,7 @@ build_modrm_byte (void) || (i.tm.opcode_modifier.vexvvvv == VEXXDS && i.imm_operands == 1 && (i.types[0].bitfield.imm8 + || i.types[0].bitfield.imm8s || i.types[i.operands - 1].bitfield.imm8))); if (i.imm_operands == 2) source = 2; --- a/gas/testsuite/gas/i386/intel.s +++ b/gas/testsuite/gas/i386/intel.s @@ -205,8 +205,8 @@ foo: rcl dword ptr 0x90909090[eax] rcl byte ptr 0x90909090[eax], cl rcl dword ptr 0x90909090[eax], cl - aam 0xffffff90 - aad 0xffffff90 + aam 0x90 + aad 0x90 xlat byte ptr ds:[ebx] fcom dword ptr 0x90909090[eax] fst dword ptr 0x90909090[eax] --- a/gas/testsuite/gas/i386/opcode.s +++ b/gas/testsuite/gas/i386/opcode.s @@ -202,8 +202,8 @@ foo: rcll 0x90909090(%eax) rclb %cl,0x90909090(%eax) rcll %cl,0x90909090(%eax) - aam $0xffffff90 - aad $0xffffff90 + aam $0x90 + aad $0x90 xlat %ds:(%ebx) fcoms 0x90909090(%eax) fsts 0x90909090(%eax) --- a/gas/testsuite/gas/i386/x86-64-xop.s +++ b/gas/testsuite/gas/i386/x86-64-xop.s @@ -911,20 +911,20 @@ _start: VPROTB %xmm15,%xmm15,%xmm15 # Tests for op VPROTB imm8, xmm2, xmm1 (at&t syntax) VPROTB $0x3,%xmm11,%xmm15 - VPROTB $0xFF,%xmm0,%xmm0 - VPROTB $0xFF,%xmm11,%xmm4 + VPROTB $-1,%xmm0,%xmm0 + VPROTB $-1,%xmm11,%xmm4 VPROTB $0x0,%xmm11,%xmm4 VPROTB $0x0,%xmm15,%xmm4 VPROTB $0x0,%xmm0,%xmm15 - VPROTB $0xFF,%xmm11,%xmm0 + VPROTB $-1,%xmm11,%xmm0 VPROTB $0x3,%xmm0,%xmm0 VPROTB $0x3,%xmm11,%xmm0 VPROTB $0x0,%xmm0,%xmm4 - VPROTB $0xFF,%xmm15,%xmm0 - VPROTB $0xFF,%xmm0,%xmm15 - VPROTB $0xFF,%xmm15,%xmm15 + VPROTB $-1,%xmm15,%xmm0 + VPROTB $-1,%xmm0,%xmm15 + VPROTB $-1,%xmm15,%xmm15 VPROTB $0x3,%xmm15,%xmm4 - VPROTB $0xFF,%xmm11,%xmm15 + VPROTB $-1,%xmm11,%xmm15 VPROTB $0x3,%xmm0,%xmm15 # Tests for op VPROTD xmm3, xmm2/mem128, xmm1 (at&t syntax) VPROTD %xmm2,%xmm0,%xmm15 @@ -964,17 +964,17 @@ _start: VPROTD $0x0,%xmm15,%xmm15 VPROTD $0x0,(%rsi),%xmm15 VPROTD $0x0,%xmm0,%xmm11 - VPROTD $0xFF,%xmm15,%xmm0 + VPROTD $-1,%xmm15,%xmm0 VPROTD $0x3,%xmm0,%xmm0 VPROTD $0x3,%xmm15,%xmm0 VPROTD $0x0,%xmm11,%xmm11 VPROTD $0x0,%xmm0,%xmm15 VPROTD $0x3,(%rcx),%xmm0 - VPROTD $0xFF,(%rsi),%xmm0 + VPROTD $-1,(%rsi),%xmm0 VPROTD $0x0,(%rdi),%xmm15 - VPROTD $0xFF,%xmm15,%xmm15 - VPROTD $0xFF,%xmm11,%xmm11 - VPROTD $0xFF,(%rsi),%xmm11 + VPROTD $-1,%xmm15,%xmm15 + VPROTD $-1,%xmm11,%xmm11 + VPROTD $-1,(%rsi),%xmm11 VPROTD $0x3,(%rdi),%xmm15 VPROTD $0x3,%xmm15,%xmm11 # Tests for op VPROTQ xmm3, xmm2/mem128, xmm1 (at&t syntax) @@ -1015,17 +1015,17 @@ _start: VPROTQ $0x0,%xmm15,%xmm15 VPROTQ $0x0,(%rsi),%xmm15 VPROTQ $0x0,%xmm0,%xmm11 - VPROTQ $0xFF,%xmm15,%xmm0 + VPROTQ $-1,%xmm15,%xmm0 VPROTQ $0x3,%xmm0,%xmm0 VPROTQ $0x3,%xmm15,%xmm0 VPROTQ $0x0,%xmm11,%xmm11 VPROTQ $0x0,%xmm0,%xmm15 VPROTQ $0x3,(%rcx),%xmm0 - VPROTQ $0xFF,(%rsi),%xmm0 + VPROTQ $-1,(%rsi),%xmm0 VPROTQ $0x0,(%rdi),%xmm15 - VPROTQ $0xFF,%xmm15,%xmm15 - VPROTQ $0xFF,%xmm11,%xmm11 - VPROTQ $0xFF,(%rsi),%xmm11 + VPROTQ $-1,%xmm15,%xmm15 + VPROTQ $-1,%xmm11,%xmm11 + VPROTQ $-1,(%rsi),%xmm11 VPROTQ $0x3,(%rdi),%xmm15 VPROTQ $0x3,%xmm15,%xmm11 # Tests for op VPROTW xmm3, xmm2/mem128, xmm1 (at&t syntax) @@ -1066,17 +1066,17 @@ _start: VPROTW $0x0,%xmm15,%xmm15 VPROTW $0x0,(%rsi),%xmm15 VPROTW $0x0,%xmm0,%xmm11 - VPROTW $0xFF,%xmm15,%xmm0 + VPROTW $-1,%xmm15,%xmm0 VPROTW $0x3,%xmm0,%xmm0 VPROTW $0x3,%xmm15,%xmm0 VPROTW $0x0,%xmm11,%xmm11 VPROTW $0x0,%xmm0,%xmm15 VPROTW $0x3,(%rcx),%xmm0 - VPROTW $0xFF,(%rsi),%xmm0 + VPROTW $-1,(%rsi),%xmm0 VPROTW $0x0,(%rdi),%xmm15 - VPROTW $0xFF,%xmm15,%xmm15 - VPROTW $0xFF,%xmm11,%xmm11 - VPROTW $0xFF,(%rsi),%xmm11 + VPROTW $-1,%xmm15,%xmm15 + VPROTW $-1,%xmm11,%xmm11 + VPROTW $-1,(%rsi),%xmm11 VPROTW $0x3,(%rdi),%xmm15 VPROTW $0x3,%xmm15,%xmm11 # Tests for op VPSHAB xmm3, xmm2/mem128, xmm1 (at&t syntax) --- a/gas/testsuite/gas/i386/xop.s +++ b/gas/testsuite/gas/i386/xop.s @@ -911,20 +911,20 @@ _start: VPROTB %xmm1,%xmm7,%xmm3 # Tests for op VPROTB imm8, xmm2, xmm1 (at&t syntax) VPROTB $0x3,%xmm5,%xmm2 - VPROTB $0xFF,%xmm0,%xmm0 - VPROTB $0xFF,%xmm5,%xmm7 + VPROTB $-1,%xmm0,%xmm0 + VPROTB $-1,%xmm5,%xmm7 VPROTB $0x0,%xmm5,%xmm7 VPROTB $0x0,%xmm7,%xmm7 VPROTB $0x0,%xmm0,%xmm2 - VPROTB $0xFF,%xmm5,%xmm0 + VPROTB $-1,%xmm5,%xmm0 VPROTB $0x3,%xmm0,%xmm0 VPROTB $0x3,%xmm5,%xmm0 VPROTB $0x0,%xmm0,%xmm7 - VPROTB $0xFF,%xmm7,%xmm0 - VPROTB $0xFF,%xmm0,%xmm2 - VPROTB $0xFF,%xmm7,%xmm2 + VPROTB $-1,%xmm7,%xmm0 + VPROTB $-1,%xmm0,%xmm2 + VPROTB $-1,%xmm7,%xmm2 VPROTB $0x3,%xmm7,%xmm7 - VPROTB $0xFF,%xmm5,%xmm2 + VPROTB $-1,%xmm5,%xmm2 VPROTB $0x3,%xmm0,%xmm2 # Tests for op VPROTD xmm3, xmm2/mem128, xmm1 (at&t syntax) VPROTD %xmm7,%xmm0,%xmm3 @@ -964,18 +964,18 @@ _start: VPROTD $0x0,%xmm7,%xmm7 VPROTD $0x0,(%ebx),%xmm7 VPROTD $0x0,%xmm0,%xmm5 - VPROTD $0xFF,%xmm5,%xmm0 + VPROTD $-1,%xmm5,%xmm0 VPROTD $0x3,%xmm0,%xmm0 VPROTD $0x3,%xmm7,%xmm0 VPROTD $0x0,%xmm5,%xmm5 VPROTD $0x0,%xmm0,%xmm7 VPROTD $0x3,(%eax),%xmm0 - VPROTD $0xFF,(%ebx),%xmm0 + VPROTD $-1,(%ebx),%xmm0 VPROTD $0x0,(%eax),%xmm7 - VPROTD $0xFF,%xmm7,%xmm7 - VPROTD $0xFF,%xmm5,%xmm5 - VPROTD $0xFF,(%ebx),%xmm5 - VPROTD $0xFF,%xmm7,%xmm0 + VPROTD $-1,%xmm7,%xmm7 + VPROTD $-1,%xmm5,%xmm5 + VPROTD $-1,(%ebx),%xmm5 + VPROTD $-1,%xmm7,%xmm0 VPROTD $0x3,(%eax),%xmm7 # Tests for op VPROTQ xmm3, xmm2/mem128, xmm1 (at&t syntax) VPROTQ %xmm7,%xmm0,%xmm3 @@ -1015,18 +1015,18 @@ _start: VPROTQ $0x0,%xmm7,%xmm7 VPROTQ $0x0,(%ebx),%xmm7 VPROTQ $0x0,%xmm0,%xmm5 - VPROTQ $0xFF,%xmm5,%xmm0 + VPROTQ $-1,%xmm5,%xmm0 VPROTQ $0x3,%xmm0,%xmm0 VPROTQ $0x3,%xmm7,%xmm0 VPROTQ $0x0,%xmm5,%xmm5 VPROTQ $0x0,%xmm0,%xmm7 VPROTQ $0x3,(%eax),%xmm0 - VPROTQ $0xFF,(%ebx),%xmm0 + VPROTQ $-1,(%ebx),%xmm0 VPROTQ $0x0,(%eax),%xmm7 - VPROTQ $0xFF,%xmm7,%xmm7 - VPROTQ $0xFF,%xmm5,%xmm5 - VPROTQ $0xFF,(%ebx),%xmm5 - VPROTQ $0xFF,%xmm7,%xmm0 + VPROTQ $-1,%xmm7,%xmm7 + VPROTQ $-1,%xmm5,%xmm5 + VPROTQ $-1,(%ebx),%xmm5 + VPROTQ $-1,%xmm7,%xmm0 VPROTQ $0x3,(%eax),%xmm7 # Tests for op VPROTW xmm3, xmm2/mem128, xmm1 (at&t syntax) VPROTW %xmm7,%xmm0,%xmm3 @@ -1066,18 +1066,18 @@ _start: VPROTW $0x0,%xmm7,%xmm7 VPROTW $0x0,(%ebx),%xmm7 VPROTW $0x0,%xmm0,%xmm5 - VPROTW $0xFF,%xmm5,%xmm0 + VPROTW $-1,%xmm5,%xmm0 VPROTW $0x3,%xmm0,%xmm0 VPROTW $0x3,%xmm7,%xmm0 VPROTW $0x0,%xmm5,%xmm5 VPROTW $0x0,%xmm0,%xmm7 VPROTW $0x3,(%eax),%xmm0 - VPROTW $0xFF,(%ebx),%xmm0 + VPROTW $-1,(%ebx),%xmm0 VPROTW $0x0,(%eax),%xmm7 - VPROTW $0xFF,%xmm7,%xmm7 - VPROTW $0xFF,%xmm5,%xmm5 - VPROTW $0xFF,(%ebx),%xmm5 - VPROTW $0xFF,%xmm7,%xmm0 + VPROTW $-1,%xmm7,%xmm7 + VPROTW $-1,%xmm5,%xmm5 + VPROTW $-1,(%ebx),%xmm5 + VPROTW $-1,%xmm7,%xmm0 VPROTW $0x3,(%eax),%xmm7 # Tests for op VPSHAB xmm3, xmm2/mem128, xmm1 (at&t syntax) VPSHAB %xmm7,%xmm0,%xmm3 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -377,12 +377,12 @@ idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8 idiv, 0xf6/7, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword } rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } -ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } @@ -1135,13 +1135,13 @@ prefetcht1, 0xf18/2, SSE|3dnowA, Modrm|A prefetcht2, 0xf18/3, SSE|3dnowA, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } psadbw, 0xff6, SSE|3dnowA, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } psadbw, 0x660ff6, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pshufw, 0xf70, SSE|3dnowA, Modrm|NoSuf, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, RegMMX } +pshufw, 0xf70, SSE|3dnowA, Modrm|NoSuf, { Imm8|Imm8S, Qword|Unspecified|BaseIndex|RegMMX, RegMMX } rcpps, 0x0f53, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } rcpss, 0xf30f53, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } rsqrtps, 0x0f52, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } rsqrtss, 0xf30f52, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } sfence, 0xfaef8, SSE|3dnowA, NoSuf, {} -shufps, 0x0fc6, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +shufps, 0x0fc6, , Modrm|||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } sqrtps, 0x0f51, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } sqrtss, 0xf30f51, , Modrm|||NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } stmxcsr, 0x0fae/3, , Modrm||NoSuf, { Dword|Unspecified|BaseIndex } @@ -1193,7 +1193,7 @@ movupd, 0x660f10, , D|Mo mulpd, 0x660f59, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } mulsd, 0xf20f59, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } orpd, 0x660f56, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -shufpd, 0x660fc6, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +shufpd, 0x660fc6, , Modrm|||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } sqrtpd, 0x660f51, , Modrm||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } sqrtsd, 0xf20f51, , Modrm|||NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } subpd, 0x660f5c, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1226,9 +1226,9 @@ movdq2q, 0xf20fd6, SSE2, Modrm|NoSuf, { movq2dq, 0xf30fd6, SSE2, Modrm|NoSuf, { RegMMX, RegXMM } pmuludq, 0x660ff4, , Modrm|||C|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pmuludq, 0xff4, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } -pshufd, 0x660f70, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pshufhw, 0xf30f70, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -pshuflw, 0xf20f70, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pshufd, 0x660f70, , Modrm||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } +pshufhw, 0xf30f70, , Modrm||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } +pshuflw, 0xf20f70, , Modrm||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } pslldq, 0x660f73/7, , Modrm||NoSuf, { Imm8, RegXMM } psrldq, 0x660f73/3, , Modrm||NoSuf, { Imm8, RegXMM } punpckhqdq, 0x660f6d, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1337,25 +1337,25 @@ pabsd, 0x0f381e, -blendp, 0x660f3a0c | , , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +blendp, 0x660f3a0c | , , Modrm|||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } blendvp, 0x664a | , AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } blendvp, 0x664a | , AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } blendvp, 0x660f3814 | , SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } blendvp, 0x660f3814 | , SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -dpp, 0x660f3a40 | , , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +dpp, 0x660f3a40 | , , Modrm|||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } extractps, 0x6617, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } extractps, 0x6617, AVX|x64, RegMem|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } extractps, 0x660f3a17, SSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } extractps, 0x660f3a17, SSE4_1|x64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 } insertps, 0x660f3a21, , Modrm|||NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM } movntdqa, 0x660f382a, , Modrm||NoSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } -mpsadbw, 0x660f3a42, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +mpsadbw, 0x660f3a42, , Modrm|||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } packusdw, 0x660f382b, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pblendvb, 0x664c, AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } pblendvb, 0x664c, AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } pblendvb, 0x660f3810, SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pblendw, 0x660f3a0e, , Modrm|||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pblendw, 0x660f3a0e, , Modrm|||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } pcmpeqq, 0x660f3829, , Modrm|||NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pextr, 0x660f3a14 | , , RegMem||NoSuf|IgnoreSize|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } pextr, 0x660f3a14 | , , Modrm||NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } @@ -1445,7 +1445,7 @@ vaesenclast, 0x66dd, VAES, Modrm|Vex=2|S -pclmulqdq, 0x660f3a44, PCLMUL, Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +pclmulqdq, 0x660f3a44, PCLMUL, Modrm||NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } pclmullqlqdq, 0x660f3a44/0x00, PCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } pclmulhqlqdq, 0x660f3a44/0x01, PCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } pclmullqhqdq, 0x660f3a44/0x10, PCLMUL, Modrm||NoSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1484,7 +1484,7 @@ vaddsubpd, 0x66d0, AVX, Modrm|Vex|Space0 vaddsubps, 0xf2d0, AVX, Modrm|Vex|Space0F|VexVVVV=1|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vandnp, 0x55, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vandp, 0x54, AVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendp, 0x660c | , AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vblendp, 0x660c | , AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vblendvp, 0x664a | , AVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vbroadcastf128, 0x661a, AVX, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } vbroadcastsd, 0x6619, AVX, Modrm|Vex256|Space0F38|VexW0|NoSuf, { Qword|Unspecified|BaseIndex, RegYMM } @@ -1512,8 +1512,8 @@ vcvttps2dq, 0xf35b, AVX, Modrm|Vex|Space vcvtts2si, 0x2c, AVX, Modrm|VexLIG|Space0F|No_bSuf|No_wSuf|No_sSuf, { |Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } vdivp, 0x5e, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vdivs, 0x5e, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vdppd, 0x6641, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vdpps, 0x6640, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vdppd, 0x6641, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vdpps, 0x6640, AVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vextractf128, 0x6619, AVX, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } vextractps, 0x6617, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } vextractps, 0x6617, AVX|x64, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } @@ -1562,7 +1562,7 @@ vmovs, 0x10, AVX, D|Modrm|V vmovshdup, 0xf316, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vmovsldup, 0xf312, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vmovup, 0x10, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vmpsadbw, 0x6642, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmpsadbw, 0x6642, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vmulp, 0x59, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vmuls, 0x59, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vorp, 0x56, AVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } @@ -1582,7 +1582,7 @@ vpand, 0x66db, AVX|AVX2, Modrm|C|Vex|Spa vpandn, 0x66df, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpavg, 0x66e0 | (3 * ), AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpblendvb, 0x664c, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpblendw, 0x660e, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpblendw, 0x660e, AVX|AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmpeq, 0x6674 | , AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmpeqd, 0x6676, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmpeqq, 0x6629, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } @@ -1595,9 +1595,9 @@ vpcmpgtd, 0x6666, AVX|AVX2, Modrm|Vex|Sp vpcmpgtq, 0x6637, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmpistri, 0x6663, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } vpcmpistrm, 0x6662, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM } -vperm2f128, 0x6606, AVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vperm2f128, 0x6606, AVX, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } vpermilp, 0x660c | , AVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpermilp, 0x6604 | , AVX, Modrm|Vex|Space0F3A|VexW0|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpermilp, 0x6604 | , AVX, Modrm|Vex|Space0F3A|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vpextr, 0x6616, AVX|, Modrm|Vex|Space0F3A||NoSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } vpextrw, 0x66c5, AVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM, Reg32|Reg64 } vpextr, 0x6614 | , AVX, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 } @@ -1651,9 +1651,9 @@ vpmuludq, 0x66f4, AVX|AVX2, Modrm|C|Vex| vpor, 0x66eb, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsadbw, 0x66f6, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|C|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpshufb, 0x6600, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpshufd, 0x6670, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpshufhw, 0xf370, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } -vpshuflw, 0xf270, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpshufd, 0x6670, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpshufhw, 0xf370, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vpshuflw, 0xf270, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vpsign, 0x6608 | , AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsignd, 0x660a, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsll, 0x6672 | /6, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV=2|VexWIG|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } @@ -1690,7 +1690,7 @@ vroundp, 0x6608 | , AVX, Mod vrounds, 0x660a | , AVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vrsqrtps, 0x52, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vrsqrtss, 0xf352, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vshufp, 0xc6, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vshufp, 0xc6, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vsqrtp, 0x51, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vsqrts, 0x51, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vstmxcsr, 0xae/3, AVX, Modrm|Vex128|Space0F|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex } @@ -1725,14 +1725,14 @@ vpmovzxwq, 0x6634, AVX2, Modrm|Vex=2|Spa vbroadcasti128, 0x665A, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } vbroadcastsd, 0x6619, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM } vbroadcastss, 0x6618, AVX2, Modrm|Vex|Space0F38|VexW=1|NoSuf, { RegXMM, RegXMM|RegYMM } -vpblendd, 0x6602, AVX2, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpblendd, 0x6602, AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpbroadcast, 0x6678 | , AVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } vpbroadcast, 0x6658 | , AVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM } -vperm2i128, 0x6646, AVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vperm2i128, 0x6646, AVX2, Modrm|Vex=2|Space0F3A|VexVVVV|VexW0|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } vpermd, 0x6636, AVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermpd, 0x6601, AVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } +vpermpd, 0x6601, AVX2, Modrm|Vex=2|Space0F3A|VexW1|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM } vpermps, 0x6616, AVX2, Modrm|Vex=2|Space0F38|VexVVVV=1|VexW=1|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } -vpermq, 0x6600, AVX2, Modrm|Vex=2|Space0F3A|VexW=2|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM } +vpermq, 0x6600, AVX2, Modrm|Vex=2|Space0F3A|VexW1|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM } vextracti128, 0x6639, AVX2, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM } vinserti128, 0x6638, AVX2, Modrm|Vex=2|Space0F3A|VexVVVV=1|VexW=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM } vpmaskmov, 0x668e, AVX2, Modrm|Vex|Space0F38|VexVVVV||CheckOperandSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } @@ -1766,7 +1766,7 @@ vaeskeygenassist, 0x66df, AVX|AES, Modrm // PCLMUL + AVX -vpclmulqdq, 0x6644, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vpclmulqdq, 0x6644, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vpclmullqlqdq, 0x6644/0x00, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vpclmulhqlqdq, 0x6644/0x01, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vpclmullqhqdq, 0x6644/0x10, AVX|PCLMUL, Modrm|Vex|Space0F3A|VexVVVV=1|VexWIG|NoSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } @@ -1821,7 +1821,7 @@ bzhi, 0xf5, BMI2, Modrm|CheckOperandSize mulx, 0xf2f6, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } pdep, 0xf2f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } pext, 0xf3f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } -rorx, 0xf2f0, BMI2, Modrm|CheckOperandSize|Vex128|Space0F3A|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +rorx, 0xf2f0, BMI2, Modrm|CheckOperandSize|Vex128|Space0F3A|No_bSuf|No_wSuf|No_sSuf, { Imm8|Imm8S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } sarx, 0xf3f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } shlx, 0x66f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } shrx, 0xf2f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } @@ -1877,7 +1877,7 @@ vpmadcsswd, 0xa6, XOP, Modrm|Vex128|Spac vpmadcswd, 0xb6, XOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vpperm, 0xa3, XOP, D|Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vprot, 0x90 | , XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } -vprot, 0xc0 | , XOP, Modrm|Vex128|SpaceXOP08|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +vprot, 0xc0 | , XOP, Modrm|Vex128|SpaceXOP08|VexW0|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } vpsha, 0x98 | , XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } vpshl, 0x94 | , XOP, D|Modrm|Vex128|SpaceXOP09|VexVVVV|SwapSources|VexW0|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } @@ -2025,7 +2025,7 @@ bndstx, 0x0f1b, MPX, Modrm|Anysize|Ignor bndldx, 0x0f1a, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } // SHA instructions. -sha1rnds4, 0xf3acc, SHA, Modrm|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +sha1rnds4, 0xf3acc, SHA, Modrm|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } sha1nexte, 0xf38c8, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } sha1msg1, 0xf38c9, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } sha1msg2, 0xf38ca, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -2036,7 +2036,7 @@ sha256msg2, 0xf38cd, SHA, Modrm|NoSuf, { // VPCLMULQDQ instructions -vpclmulqdq, 0x6644, VPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } +vpclmulqdq, 0x6644, VPCLMULQDQ, Modrm|Vex256|Space0F3A|VexWIG|VexVVVV|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } vpclmullqlqdq, 0x6644/0x00, VPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } vpclmulhqlqdq, 0x6644/0x01, VPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } vpclmullqhqdq, 0x6644/0x10, VPCLMULQDQ, Modrm|Vex=2|Space0F3A|VexWIG|VexVVVV=1|NoSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM } @@ -2110,7 +2110,7 @@ vprorv, 0x6614, AVX512F, Modrm|Maski vpsllv, 0x6647, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpsrav, 0x6646, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpsrlv, 0x6645, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpternlog, 0x6625, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpternlog, 0x6625, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vbroadcastf32x4, 0x661A, AVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } vbroadcasti32x4, 0x665A, AVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } @@ -2214,8 +2214,8 @@ vextracti64x4, 0x663B, AVX512F, Modrm|EV vextractps, 0x6617, AVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } vextractps, 0x6617, AVX512F|x64, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 } -vfixupimmp, 0x6654, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfixupimms, 0x6655, AVX512F, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfixupimmp, 0x6654, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfixupimms, 0x6655, AVX512F, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8|Imm8S, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } vgetmantp, 0x26, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vgetmants, 0x27, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } @@ -2328,12 +2328,12 @@ vptestnm, 0xf327, AVX512F, Modrm|Mas vpermd, 0x6636, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } vpermps, 0x6616, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermilp, 0x6604 | , AVX512F, Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpermilp, 0x6604 | , AVX512F, Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vpermilp, 0x660C | , AVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermpd, 0x6601, AVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vpermpd, 0x6601, AVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } vpermpd, 0x6616, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermq, 0x6600, AVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vpermq, 0x6600, AVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } vpermq, 0x6636, AVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } vpmovdb, 0xF331, AVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } @@ -2371,10 +2371,10 @@ vpmovzxwd, 0x6633, AVX512F, Modrm|EVex=1 vpmovsxwq, 0x6624, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } vpmovzxwq, 0x6634, AVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vprol, 0x6672/1, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpror, 0x6672/0, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vprol, 0x6672/1, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpror, 0x6672/0, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshufd, 0x6670, AVX512F, Modrm|Masking=3|Space0F|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshufd, 0x6670, AVX512F, Modrm|Masking=3|Space0F|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vpsll, 0x66f2 | , AVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpsll, 0x6672 | /6, AVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } @@ -2389,13 +2389,13 @@ vrcp14s, 0x664D, AVX512F, Modrm|EVex vrsqrt14p, 0x664E, AVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vrsqrt14s, 0x664F, AVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vshuff32x4, 0x6623, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi32x4, 0x6643, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff32x4, 0x6623, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi32x4, 0x6643, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshuff64x2, 0x6623, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi64x2, 0x6643, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff64x2, 0x6623, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi64x2, 0x6643, AVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufp, 0xC6, AVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vshufp, 0xC6, AVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vunpckhp, 0x15, AVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vunpcklp, 0x14, AVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } @@ -2604,7 +2604,7 @@ kunpckwd, 0x4B, AVX512BW, Modrm|Vex=2|Sp kshiftl, 0x6633, AVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } kshiftr, 0x6631, AVX512BW, Modrm|Vex128|Space0F3A||NoSuf, { Imm8, RegMask, RegMask } -vdbpsadbw, 0x6642, AVX512BW, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vdbpsadbw, 0x6642, AVX512BW, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vmovdqu8, 0xF26F, AVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vmovdqu16, 0xF26F, AVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } @@ -2708,8 +2708,8 @@ vpmovzxbw, 0x6630, AVX512BW|AVX512VL, Mo vpsadbw, 0x66F6, AVX512BW, Modrm|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshufhw, 0xF370, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshuflw, 0xF270, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshufhw, 0xF370, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshuflw, 0xF270, AVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vptestm, 0x6626, AVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } vptestnm, 0xf326, AVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } @@ -2781,12 +2781,12 @@ vextracti64x2, 0x6639, AVX512DQ, Modrm|M vinsertf64x2, 0x6618, AVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } vinserti64x2, 0x6638, AVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vfpclassp, 0x6666, AVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegMask } -vfpclassp, 0x6666, AVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM||BaseIndex, RegMask } -vfpclasspz, 0x6666, AVX512DQ, Modrm|EVex512|Masking=2|Space0F3A||Broadcast|Disp8MemShift=6|NoSuf, { Imm8, RegZMM||Unspecified|BaseIndex, RegMask } -vfpclasspx, 0x6666, AVX512DQ|AVX512VL, Modrm|EVex128|Masking=2|Space0F3A||Broadcast|Disp8MemShift=4|NoSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } -vfpclasspy, 0x6666, AVX512DQ|AVX512VL, Modrm|EVex256|Masking=2|Space0F3A||Broadcast|Disp8MemShift=5|NoSuf, { Imm8, RegYMM||Unspecified|BaseIndex, RegMask } -vfpclasss, 0x67, , Modrm|EVexLIG|Masking=2|Space0F3A||Disp8MemShift|NoSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } +vfpclassp, 0x6666, AVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegMask } +vfpclassp, 0x6666, AVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM||BaseIndex, RegMask } +vfpclasspz, 0x6666, AVX512DQ, Modrm|EVex512|Masking=2|Space0F3A||Broadcast|Disp8MemShift=6|NoSuf, { Imm8|Imm8S, RegZMM||Unspecified|BaseIndex, RegMask } +vfpclasspx, 0x6666, AVX512DQ|AVX512VL, Modrm|EVex128|Masking=2|Space0F3A||Broadcast|Disp8MemShift=4|NoSuf, { Imm8|Imm8S, RegXMM||Unspecified|BaseIndex, RegMask } +vfpclasspy, 0x6666, AVX512DQ|AVX512VL, Modrm|EVex256|Masking=2|Space0F3A||Broadcast|Disp8MemShift=5|NoSuf, { Imm8|Imm8S, RegYMM||Unspecified|BaseIndex, RegMask } +vfpclasss, 0x67, , Modrm|EVexLIG|Masking=2|Space0F3A||Disp8MemShift|NoSuf, { Imm8|Imm8S, RegXMM||Unspecified|BaseIndex, RegMask } vpmov2m, 0xf339, AVX512DQ, Modrm|EVexDYN|Space0F38||NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } vpmovm2, 0xf338, AVX512DQ, Modrm|EVexDYN|Space0F38||NoSuf, { RegMask, RegXMM|RegYMM|RegZMM } @@ -2929,7 +2929,7 @@ vaesenclast, 0x66dd, VAES|AVX512F, Modrm // AVX512 + VPCLMULQDQ instructions -vpclmulqdq, 0x6644, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpclmulqdq, 0x6644, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpclmullqlqdq, 0x6644/0x00, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpclmulhqlqdq, 0x6644/0x01, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpclmullqhqdq, 0x6644/0x10, VPCLMULQDQ|AVX512F, Modrm|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } @@ -3290,7 +3290,7 @@ vcvttph2uw, 0x7c, AVX512_FP16, Modrm|Mas vcvttsh2si, 0xf32c, AVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|NoSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } -vfpclassph, 0x66, AVX512_FP16|, Modrm||Masking=2|Space0F3A|VexW0|Broadcast|NoSuf|, { Imm8, |Word, RegMask } +vfpclassph, 0x66, AVX512_FP16|, Modrm||Masking=2|Space0F3A|VexW0|Broadcast|NoSuf|, { Imm8|Imm8S, |Word, RegMask } vmovw, 0x666e, AVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|NoSuf, { Word|Unspecified|BaseIndex, RegXMM } vmovw, 0x667e, AVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|NoSuf, { RegXMM, Reg32 }