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[88.10.60.23]) by smtp.gmail.com with ESMTPSA id p13-20020a05600c468d00b003e001afa274sm4385612wmo.2.2023.02.09.22.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 22:56:23 -0800 (PST) From: Sergio Paracuellos To: linux-watchdog@vger.kernel.org Cc: wim@linux-watchdog.org, linux@roeck-us.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, arinc.unal@arinc9.com, tsbogend@alpha.franken.de, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: watchdog: mt7621-wdt: add phandle to access system controller registers Date: Fri, 10 Feb 2023 07:56:19 +0100 Message-Id: <20230210065621.598120-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230210065621.598120-1-sergio.paracuellos@gmail.com> References: <20230210065621.598120-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757426204514763492?= X-GMAIL-MSGID: =?utf-8?q?1757426204514763492?= MT7621 SoC provides a system controller node for accessing to some registers. Add a phandle to this node to avoid using MIPS related arch operations and includes in watchdog driver code. Signed-off-by: Sergio Paracuellos --- .../bindings/watchdog/mediatek,mt7621-wdt.yaml | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml index b2b17fdf4..3c545065f 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml @@ -14,11 +14,18 @@ allOf: properties: compatible: - const: mediatek,mt7621-wdt + items: + - const: mediatek,mt7621-wdt + - const: syscon reg: maxItems: 1 + ralink,sysctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of syscon used to control system registers + required: - compatible - reg @@ -28,6 +35,7 @@ additionalProperties: false examples: - | watchdog@100 { - compatible = "mediatek,mt7621-wdt"; + compatible = "mediatek,mt7621-wdt", "syscon"; reg = <0x100 0x100>; + ralink,sysctl = <&sysc>; }; From patchwork Fri Feb 10 06:56:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 55269 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp797349wrn; Thu, 9 Feb 2023 22:58:51 -0800 (PST) X-Google-Smtp-Source: AK7set/No0niUPn4IhQzDC8c4MOqKOANMtwa3RQsBqbLH+TnTK5vY3macCRnfyqIOUU/x7bMzwaA X-Received: by 2002:a05:6a20:160e:b0:be:afe7:ce5 with SMTP id l14-20020a056a20160e00b000beafe70ce5mr17576125pzj.51.1676012330856; Thu, 09 Feb 2023 22:58:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676012330; cv=none; d=google.com; s=arc-20160816; b=t0AeCRiwT2DE4yokAuUH8td58rPb9yGxA2G85jWOOdOU4e9bBYnMxEepJx/jZsGtz3 5xCgxjlWWHH98J0QTqTBP56vGJ5Xz+hfHf0nTQw4nhtUfEl7w970FSIsPdK+pChE/Tzd GufII0YbWrglH4v/G27YCIoqL8im8NqJpQ/PHSviVt4sUUEDvip6FWAN517Xwk3QMkk2 BviRQYI1zKTBpVor3V37EzXdaHlpIUjd11ohmMEA2Bw1ZOtYBOWiNOvqpZjWpgatMv0T Vhx/QxnDiY7GOzJP5a1uji9GLhNq8agvPEawIKAsnIeC4Tw1ImdNd3TurBjnps8eIQaf yXdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tQlG6AWGDGiaVCyhcczhUxKcndm2ZWR4D2LQqdn5yiE=; b=A0eZ0kqPAYVROHlrtMdTKZbP9aBKgcY9V88UMrqDwx8EwlDrYt/uxvbKzZovhTl8a5 jm3Ol816Y4ikpylBoYqdQ2uGcaJvU+Bu5P6ydujtO9Df/Yy9Ics/SPWsRdDT1wJ7eYk/ jy8fBeMJc7UO5t94q9JbYWb36GDdjgGJItmRv1QKISpSXdCFSZakO6WP0b+YHVJ+KYk6 ogqgMpFuKptiMYN0FXqB6BVRXy5vsijPUeBNV46bUms7NwN+AaUvWRNvZHrsaWBe6ZWG vV30j0GOQVopshiwILMGkAWnuTkA9VqL8l71CtqWStqTYzcx144QSWHfkkvIpINebWO4 VXfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=lclAAgSw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.10.60.23]) by smtp.gmail.com with ESMTPSA id p13-20020a05600c468d00b003e001afa274sm4385612wmo.2.2023.02.09.22.56.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 22:56:25 -0800 (PST) From: Sergio Paracuellos To: linux-watchdog@vger.kernel.org Cc: wim@linux-watchdog.org, linux@roeck-us.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, arinc.unal@arinc9.com, tsbogend@alpha.franken.de, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 2/3] mips: dts: ralink: mt7621: add phandle to system controller node for watchdog Date: Fri, 10 Feb 2023 07:56:20 +0100 Message-Id: <20230210065621.598120-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230210065621.598120-1-sergio.paracuellos@gmail.com> References: <20230210065621.598120-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757426305630918878?= X-GMAIL-MSGID: =?utf-8?q?1757426305630918878?= To allow to access system controller registers from watchdog driver code add a phandle in the watchdog 'wdt' node. This avoid using arch dependent operations in driver code. Signed-off-by: Sergio Paracuellos --- arch/mips/boot/dts/ralink/mt7621.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 5ca40fd21..ebee23a2b 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -71,8 +71,9 @@ sysc: syscon@0 { }; wdt: wdt@100 { - compatible = "mediatek,mt7621-wdt"; + compatible = "mediatek,mt7621-wdt", "syscon"; reg = <0x100 0x100>; + ralink,sysctl = <&sysc>; }; gpio: gpio@600 { From patchwork Fri Feb 10 06:56:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergio Paracuellos X-Patchwork-Id: 55268 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp797242wrn; Thu, 9 Feb 2023 22:58:33 -0800 (PST) X-Google-Smtp-Source: AK7set+PJ3KqI4p9rvCFvD4jxW8Q8XZzTFr+zmZ42lN8M7cfZD84d+GMVtBaF/8jIziGlDILtGGB X-Received: by 2002:aa7:8f0b:0:b0:5a8:46b0:8269 with SMTP id x11-20020aa78f0b000000b005a846b08269mr7708851pfr.31.1676012313289; Thu, 09 Feb 2023 22:58:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676012313; cv=none; d=google.com; s=arc-20160816; b=nqLOtqsTpt3dAJMEF2gO6x8GtuHiQVBzV6/LEalxfKx2cKQzyNLMZ33wlmajgVu0TX hxXHqJ9Tmgmmfy21Rau4HsbFyX6qwnGNGICoRWUS06FMpE7w8Un8oMJ8PyMaoq5A7z8b Qu6I4RiHUcGmijLFRM/uJkaanNWIYyQTNuqIPN9v5qH2hM4rtw9k7EppxBVt/aW3uARb hQl+ZLLp9tqc68toH3p8kTCGe8w/GoUnW1XwerbYMisr63SmE2GRQOmIU06DFlOKiLB4 IurHbfKw+F/WTnG8ytmi5e1OtXfzRgb/MHyzEPFH2jK82aDjI9WTmeOI6Tg8Cu44mX4W oFMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qf+2ZhY+893e36Ug2b5UjMaC8ljMGgprsHyghDRy1Sg=; b=er5x/Uge2nX28q4Gtcjr8pSjnKUjSiA0/L2C4vGEFcKleU0LCO2pqnhKr5K8pFerlj U3abbP6ovGu384NqDqUrNg1RjDmNLDGuuEmifz0sqpfwR/vCemEJHPyXL33QR09iF9gH n33g8hDBh7AiNbtbRs8EmGFK8HfEPlIAmMkrWFc6QKXgDmRJnE9lv2M9+KDPUSamQya9 7E2bVpX0S2q4hi0pI9Q8HT3Z641zosN0DG4jOkyy1hdpPckf/cxY6dTIx5AIlrBN2IUN v5l06qw9kc6IK4pjPw2w8dV5Kgnphw/n7Dd2wETP5mdTxPzanj/RuX4yDtferp63Qkp8 ghiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=QFQGPb20; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[88.10.60.23]) by smtp.gmail.com with ESMTPSA id p13-20020a05600c468d00b003e001afa274sm4385612wmo.2.2023.02.09.22.56.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 22:56:26 -0800 (PST) From: Sergio Paracuellos To: linux-watchdog@vger.kernel.org Cc: wim@linux-watchdog.org, linux@roeck-us.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, arinc.unal@arinc9.com, tsbogend@alpha.franken.de, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 3/3] watchdog: mt7621-wdt: avoid globals and arch dependencies Date: Fri, 10 Feb 2023 07:56:21 +0100 Message-Id: <20230210065621.598120-4-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230210065621.598120-1-sergio.paracuellos@gmail.com> References: <20230210065621.598120-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757426202843727289?= X-GMAIL-MSGID: =?utf-8?q?1757426287635347509?= MT7621 SoC has a system controller node. Watchdog need to access to reset status register. Ralink architecture and related driver are old and from the beggining they ar providing some architecture dependent operations for accessing this shared registers through 'asm/mach-ralink/ralink_regs.h' header file. However this is not ideal from a driver perspective which can just access to the system controller registers in am arch independent way using regmap syscon APIs. Hence, add a new structure for driver data and use it along the code. This way architecture dependencies and global vars are not needed anymore. Update Kconfig accordingly to select new added dependencies and allow driver to be compile tested. Signed-off-by: Sergio Paracuellos --- drivers/watchdog/Kconfig | 4 +- drivers/watchdog/mt7621_wdt.c | 121 ++++++++++++++++++++++------------ 2 files changed, 83 insertions(+), 42 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b64bc49c7..cf752ad64 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1865,7 +1865,9 @@ config GXP_WATCHDOG config MT7621_WDT tristate "Mediatek SoC watchdog" select WATCHDOG_CORE - depends on SOC_MT7620 || SOC_MT7621 + select REGMAP_MMIO + select MFD_SYSCON + depends on SOC_MT7620 || SOC_MT7621 || COMPILE_TEST help Hardware driver for the Mediatek/Ralink MT7621/8 SoC Watchdog Timer. diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c index a8aa3522c..a7480fd2b 100644 --- a/drivers/watchdog/mt7621_wdt.c +++ b/drivers/watchdog/mt7621_wdt.c @@ -15,8 +15,8 @@ #include #include #include - -#include +#include +#include #define SYSC_RSTSTAT 0x38 #define WDT_RST_CAUSE BIT(1) @@ -31,8 +31,12 @@ #define TMR1CTL_RESTART BIT(9) #define TMR1CTL_PRESCALE_SHIFT 16 -static void __iomem *mt7621_wdt_base; -static struct reset_control *mt7621_wdt_reset; +struct mt7621_wdt_data { + void __iomem *base; + struct reset_control *rst; + struct regmap *sysc; + struct watchdog_device wdt; +}; static bool nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, bool, 0); @@ -40,27 +44,31 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -static inline void rt_wdt_w32(unsigned reg, u32 val) +static inline void rt_wdt_w32(void __iomem *base, unsigned reg, u32 val) { - iowrite32(val, mt7621_wdt_base + reg); + iowrite32(val, base + reg); } -static inline u32 rt_wdt_r32(unsigned reg) +static inline u32 rt_wdt_r32(void __iomem *base, unsigned reg) { - return ioread32(mt7621_wdt_base + reg); + return ioread32(base + reg); } static int mt7621_wdt_ping(struct watchdog_device *w) { - rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART); + struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); + + rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART); return 0; } static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t) { + struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); + w->timeout = t; - rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000); + rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000); mt7621_wdt_ping(w); return 0; @@ -68,36 +76,41 @@ static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t) static int mt7621_wdt_start(struct watchdog_device *w) { + struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); u32 t; /* set the prescaler to 1ms == 1000us */ - rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); + rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); mt7621_wdt_set_timeout(w, w->timeout); - t = rt_wdt_r32(TIMER_REG_TMR1CTL); + t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL); t |= TMR1CTL_ENABLE; - rt_wdt_w32(TIMER_REG_TMR1CTL, t); + rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t); return 0; } static int mt7621_wdt_stop(struct watchdog_device *w) { + struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); u32 t; mt7621_wdt_ping(w); - t = rt_wdt_r32(TIMER_REG_TMR1CTL); + t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL); t &= ~TMR1CTL_ENABLE; - rt_wdt_w32(TIMER_REG_TMR1CTL, t); + rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t); return 0; } -static int mt7621_wdt_bootcause(void) +static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d) { - if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) + u32 val; + + regmap_read(d->sysc, SYSC_RSTSTAT, &val); + if (val & WDT_RST_CAUSE) return WDIOF_CARDRESET; return 0; @@ -105,7 +118,9 @@ static int mt7621_wdt_bootcause(void) static int mt7621_wdt_is_running(struct watchdog_device *w) { - return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE); + struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); + + return !!(rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE); } static const struct watchdog_info mt7621_wdt_info = { @@ -121,30 +136,44 @@ static const struct watchdog_ops mt7621_wdt_ops = { .set_timeout = mt7621_wdt_set_timeout, }; -static struct watchdog_device mt7621_wdt_dev = { - .info = &mt7621_wdt_info, - .ops = &mt7621_wdt_ops, - .min_timeout = 1, - .max_timeout = 0xfffful / 1000, -}; - static int mt7621_wdt_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; - mt7621_wdt_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(mt7621_wdt_base)) - return PTR_ERR(mt7621_wdt_base); + struct watchdog_device *mt7621_wdt; + struct mt7621_wdt_data *drvdata; + int err; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; - mt7621_wdt_reset = devm_reset_control_get_exclusive(dev, NULL); - if (!IS_ERR(mt7621_wdt_reset)) - reset_control_deassert(mt7621_wdt_reset); + drvdata->sysc = syscon_regmap_lookup_by_phandle(np, "ralink,sysctl"); + if (IS_ERR(drvdata->sysc)) + return PTR_ERR(drvdata->sysc); - mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause(); + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(drvdata->base)) + return PTR_ERR(drvdata->base); - watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout, - dev); - watchdog_set_nowayout(&mt7621_wdt_dev, nowayout); - if (mt7621_wdt_is_running(&mt7621_wdt_dev)) { + drvdata->rst = devm_reset_control_get_exclusive(dev, NULL); + if (!IS_ERR(drvdata->rst)) + reset_control_deassert(drvdata->rst); + + mt7621_wdt = &drvdata->wdt; + mt7621_wdt->info = &mt7621_wdt_info; + mt7621_wdt->ops = &mt7621_wdt_ops; + mt7621_wdt->min_timeout = 1; + mt7621_wdt->max_timeout = 0xfffful / 1000; + mt7621_wdt->parent = dev; + + mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata); + + watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev); + watchdog_set_nowayout(mt7621_wdt, nowayout); + watchdog_set_drvdata(mt7621_wdt, drvdata); + + if (mt7621_wdt_is_running(mt7621_wdt)) { /* * Make sure to apply timeout from watchdog core, taking * the prescaler of this driver here into account (the @@ -154,17 +183,27 @@ static int mt7621_wdt_probe(struct platform_device *pdev) * we first disable the watchdog, set the new prescaler * and timeout, and then re-enable the watchdog. */ - mt7621_wdt_stop(&mt7621_wdt_dev); - mt7621_wdt_start(&mt7621_wdt_dev); - set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status); + mt7621_wdt_stop(mt7621_wdt); + mt7621_wdt_start(mt7621_wdt); + set_bit(WDOG_HW_RUNNING, &mt7621_wdt->status); } - return devm_watchdog_register_device(dev, &mt7621_wdt_dev); + err = devm_watchdog_register_device(dev, &drvdata->wdt); + if (err) { + dev_err(dev, "Error registering watchdog device\n"); + return err; + } + + platform_set_drvdata(pdev, drvdata); + + return 0; } static void mt7621_wdt_shutdown(struct platform_device *pdev) { - mt7621_wdt_stop(&mt7621_wdt_dev); + struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev); + + mt7621_wdt_stop(&drvdata->wdt); } static const struct of_device_id mt7621_wdt_match[] = {