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RISC-V: Add vnsrl C++ API tests Date: Fri, 10 Feb 2023 05:58:35 +0800 Message-Id: <20230209215835.27124-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757392374947565391?= X-GMAIL-MSGID: =?utf-8?q?1757392374947565391?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vnsrl_vv-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv-3.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx-3.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vnsrl_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnsrl_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnsrl_vv-3.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnsrl_vx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnsrl_vx-3.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vnsrl_vx_tumu-3.C | 111 +++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-1.C new file mode 100644 index 00000000000..d1ff9826009 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl(vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl(vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl(vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl(vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl(vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl(vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl(vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl(vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl(vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl(vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl(vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl(vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vnsrl(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-2.C new file mode 100644 index 00000000000..a78e3d3f98a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl(vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl(vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl(vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl(vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl(vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl(vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl(vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl(vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl(vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl(vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl(vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl(vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8mf8_t test___riscv_vnsrl(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-3.C new file mode 100644 index 00000000000..95530232250 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl(vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl(vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl(vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl(vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl(vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl(vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl(vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl(vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl(vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl(vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl(vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl(vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl(vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl(vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl(vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8mf8_t test___riscv_vnsrl(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl(vbool8_t mask,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl(vbool4_t mask,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl(vbool2_t mask,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl(vbool16_t mask,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl(vbool8_t mask,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl(vbool4_t mask,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl(vbool32_t mask,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl(vbool16_t mask,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl(vbool8_t mask,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C new file mode 100644 index 00000000000..9b4504623dd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C new file mode 100644 index 00000000000..f772dd7fd06 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C new file mode 100644 index 00000000000..525f012bfd7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C new file mode 100644 index 00000000000..081c438decf --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C new file mode 100644 index 00000000000..5b3ce209c21 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C new file mode 100644 index 00000000000..b0fbd0ca215 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tu(vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_tu(vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_tu(vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_tu(vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_tu(vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_tu(vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_tu(vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_tu(vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_tu(vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_tu(vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_tu(vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_tu(vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_tu(vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_tu(vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_tu(vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C new file mode 100644 index 00000000000..82197f6667e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C new file mode 100644 index 00000000000..955e07b7968 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C new file mode 100644 index 00000000000..11707147523 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C new file mode 100644 index 00000000000..be166919138 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C new file mode 100644 index 00000000000..52d2ce5a0c0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C new file mode 100644 index 00000000000..c4be22c8792 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-1.C new file mode 100644 index 00000000000..c82b9be83c5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vnsrl(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-2.C new file mode 100644 index 00000000000..db585a8ea21 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,31); +} + + +vuint8mf8_t test___riscv_vnsrl(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-3.C new file mode 100644 index 00000000000..b980a5e7cdf --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(op1,shift,32); +} + + +vuint8mf8_t test___riscv_vnsrl(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C new file mode 100644 index 00000000000..2ae2e714567 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C new file mode 100644 index 00000000000..282c25be25c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C new file mode 100644 index 00000000000..cff5a0a63d5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C new file mode 100644 index 00000000000..c1a2a596136 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C new file mode 100644 index 00000000000..51fd7bc052d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C new file mode 100644 index 00000000000..678dd38750f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tu(vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_tu(vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_tu(vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_tu(vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_tu(vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_tu(vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_tu(vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_tu(vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_tu(vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_tu(vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_tu(vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_tu(vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_tu(vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_tu(vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_tu(vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C new file mode 100644 index 00000000000..9154ee12200 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C new file mode 100644 index 00000000000..b1908e8ed07 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C new file mode 100644 index 00000000000..f2178b615d7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C new file mode 100644 index 00000000000..cfc444dcd9a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vnsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C new file mode 100644 index 00000000000..36e9b9a3db3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vnsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C new file mode 100644 index 00000000000..08b859d8077 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vnsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vnsrl_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */