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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id fh22-20020a1709073a9600b0089c2387faf6si4174787ejc.232.2023.02.09.13.55.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 13:55:47 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A78A7385B513 for ; Thu, 9 Feb 2023 21:55:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id 2E2833858C50 for ; Thu, 9 Feb 2023 21:55:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2E2833858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp63t1675979704trx0ncxl Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 10 Feb 2023 05:55:03 +0800 (CST) X-QQ-SSF: 01400000002000E0L000B00A0000000 X-QQ-FEAT: LpuzoIPF5utDCXgBhFdKlV8i2FGi2a1LESEtwP5HHzxC8HYZxNfW9gB61Lmea EKySpFFQE+49TL+TC1ivyccmjtiviIYqrnOu6xoaWhMMMPDDArqBH94FlBNMl6LM6LH0sWc Qpxv3WiZwLkdDxhEgxXKiYnKq6PPbJvcO/J1Llt7eP5pUqgbmiIEvArUURVu/DCF9RXMoRi vZTeX0c8a2+ogf8J3LlLQf3+dEOe79wCI7qjAYty+UP2lv+ZAhJCnbDFmA8o+IWe77WHOJE IId5hg4Hjb1zYmCHWkjjjyL/YhXmwozMHqzu+IRcPbcJSPz0OlTbfppNYrJ5AsH1IOQltyR pK7TX1FRDhkz+uc2zHkDJim3+LlmWfXaptMWQtQNR+RCWcWDjuQWucDeJOGgA== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vmv C API tests Date: Fri, 10 Feb 2023 05:55:02 +0800 Message-Id: <20230209215502.25158-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757392139727803498?= X-GMAIL-MSGID: =?utf-8?q?1757392139727803498?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vmv_v_v-1.c: New test. * gcc.target/riscv/rvv/base/vmv_v_v-2.c: New test. * gcc.target/riscv/rvv/base/vmv_v_v-3.c: New test. * gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c: New test. * gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c: New test. * gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vmv_v_v-1.c | 276 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v-2.c | 276 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v-3.c | 276 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c | 276 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c | 276 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c | 276 ++++++++++++++++++ 6 files changed, 1656 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c new file mode 100644 index 00000000000..c485b1df458 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c @@ -0,0 +1,276 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_v_i8mf8(vint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf8(src,vl); +} + + +vint8mf4_t test___riscv_vmv_v_v_i8mf4(vint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf4(src,vl); +} + + +vint8mf2_t test___riscv_vmv_v_v_i8mf2(vint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf2(src,vl); +} + + +vint8m1_t test___riscv_vmv_v_v_i8m1(vint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m1(src,vl); +} + + +vint8m2_t test___riscv_vmv_v_v_i8m2(vint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m2(src,vl); +} + + +vint8m4_t test___riscv_vmv_v_v_i8m4(vint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m4(src,vl); +} + + +vint8m8_t test___riscv_vmv_v_v_i8m8(vint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m8(src,vl); +} + + +vint16mf4_t test___riscv_vmv_v_v_i16mf4(vint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf4(src,vl); +} + + +vint16mf2_t test___riscv_vmv_v_v_i16mf2(vint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf2(src,vl); +} + + +vint16m1_t test___riscv_vmv_v_v_i16m1(vint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m1(src,vl); +} + + +vint16m2_t test___riscv_vmv_v_v_i16m2(vint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m2(src,vl); +} + + +vint16m4_t test___riscv_vmv_v_v_i16m4(vint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m4(src,vl); +} + + +vint16m8_t test___riscv_vmv_v_v_i16m8(vint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m8(src,vl); +} + + +vint32mf2_t test___riscv_vmv_v_v_i32mf2(vint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32mf2(src,vl); +} + + +vint32m1_t test___riscv_vmv_v_v_i32m1(vint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m1(src,vl); +} + + +vint32m2_t test___riscv_vmv_v_v_i32m2(vint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m2(src,vl); +} + + +vint32m4_t test___riscv_vmv_v_v_i32m4(vint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m4(src,vl); +} + + +vint32m8_t test___riscv_vmv_v_v_i32m8(vint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m8(src,vl); +} + + +vint64m1_t test___riscv_vmv_v_v_i64m1(vint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m1(src,vl); +} + + +vint64m2_t test___riscv_vmv_v_v_i64m2(vint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m2(src,vl); +} + + +vint64m4_t test___riscv_vmv_v_v_i64m4(vint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m4(src,vl); +} + + +vint64m8_t test___riscv_vmv_v_v_i64m8(vint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m8(src,vl); +} + + +vuint8mf8_t test___riscv_vmv_v_v_u8mf8(vuint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf8(src,vl); +} + + +vuint8mf4_t test___riscv_vmv_v_v_u8mf4(vuint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf4(src,vl); +} + + +vuint8mf2_t test___riscv_vmv_v_v_u8mf2(vuint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf2(src,vl); +} + + +vuint8m1_t test___riscv_vmv_v_v_u8m1(vuint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m1(src,vl); +} + + +vuint8m2_t test___riscv_vmv_v_v_u8m2(vuint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m2(src,vl); +} + + +vuint8m4_t test___riscv_vmv_v_v_u8m4(vuint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m4(src,vl); +} + + +vuint8m8_t test___riscv_vmv_v_v_u8m8(vuint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m8(src,vl); +} + + +vuint16mf4_t test___riscv_vmv_v_v_u16mf4(vuint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf4(src,vl); +} + + +vuint16mf2_t test___riscv_vmv_v_v_u16mf2(vuint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf2(src,vl); +} + + +vuint16m1_t test___riscv_vmv_v_v_u16m1(vuint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m1(src,vl); +} + + +vuint16m2_t test___riscv_vmv_v_v_u16m2(vuint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m2(src,vl); +} + + +vuint16m4_t test___riscv_vmv_v_v_u16m4(vuint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m4(src,vl); +} + + +vuint16m8_t test___riscv_vmv_v_v_u16m8(vuint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m8(src,vl); +} + + +vuint32mf2_t test___riscv_vmv_v_v_u32mf2(vuint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32mf2(src,vl); +} + + +vuint32m1_t test___riscv_vmv_v_v_u32m1(vuint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m1(src,vl); +} + + +vuint32m2_t test___riscv_vmv_v_v_u32m2(vuint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m2(src,vl); +} + + +vuint32m4_t test___riscv_vmv_v_v_u32m4(vuint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m4(src,vl); +} + + +vuint32m8_t test___riscv_vmv_v_v_u32m8(vuint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m8(src,vl); +} + + +vuint64m1_t test___riscv_vmv_v_v_u64m1(vuint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m1(src,vl); +} + + +vuint64m2_t test___riscv_vmv_v_v_u64m2(vuint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m2(src,vl); +} + + +vuint64m4_t test___riscv_vmv_v_v_u64m4(vuint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m4(src,vl); +} + + +vuint64m8_t test___riscv_vmv_v_v_u64m8(vuint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m8(src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c new file mode 100644 index 00000000000..f276d78ecb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c @@ -0,0 +1,276 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_v_i8mf8(vint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf8(src,31); +} + + +vint8mf4_t test___riscv_vmv_v_v_i8mf4(vint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf4(src,31); +} + + +vint8mf2_t test___riscv_vmv_v_v_i8mf2(vint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf2(src,31); +} + + +vint8m1_t test___riscv_vmv_v_v_i8m1(vint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m1(src,31); +} + + +vint8m2_t test___riscv_vmv_v_v_i8m2(vint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m2(src,31); +} + + +vint8m4_t test___riscv_vmv_v_v_i8m4(vint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m4(src,31); +} + + +vint8m8_t test___riscv_vmv_v_v_i8m8(vint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m8(src,31); +} + + +vint16mf4_t test___riscv_vmv_v_v_i16mf4(vint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf4(src,31); +} + + +vint16mf2_t test___riscv_vmv_v_v_i16mf2(vint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf2(src,31); +} + + +vint16m1_t test___riscv_vmv_v_v_i16m1(vint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m1(src,31); +} + + +vint16m2_t test___riscv_vmv_v_v_i16m2(vint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m2(src,31); +} + + +vint16m4_t test___riscv_vmv_v_v_i16m4(vint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m4(src,31); +} + + +vint16m8_t test___riscv_vmv_v_v_i16m8(vint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m8(src,31); +} + + +vint32mf2_t test___riscv_vmv_v_v_i32mf2(vint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32mf2(src,31); +} + + +vint32m1_t test___riscv_vmv_v_v_i32m1(vint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m1(src,31); +} + + +vint32m2_t test___riscv_vmv_v_v_i32m2(vint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m2(src,31); +} + + +vint32m4_t test___riscv_vmv_v_v_i32m4(vint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m4(src,31); +} + + +vint32m8_t test___riscv_vmv_v_v_i32m8(vint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m8(src,31); +} + + +vint64m1_t test___riscv_vmv_v_v_i64m1(vint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m1(src,31); +} + + +vint64m2_t test___riscv_vmv_v_v_i64m2(vint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m2(src,31); +} + + +vint64m4_t test___riscv_vmv_v_v_i64m4(vint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m4(src,31); +} + + +vint64m8_t test___riscv_vmv_v_v_i64m8(vint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m8(src,31); +} + + +vuint8mf8_t test___riscv_vmv_v_v_u8mf8(vuint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf8(src,31); +} + + +vuint8mf4_t test___riscv_vmv_v_v_u8mf4(vuint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf4(src,31); +} + + +vuint8mf2_t test___riscv_vmv_v_v_u8mf2(vuint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf2(src,31); +} + + +vuint8m1_t test___riscv_vmv_v_v_u8m1(vuint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m1(src,31); +} + + +vuint8m2_t test___riscv_vmv_v_v_u8m2(vuint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m2(src,31); +} + + +vuint8m4_t test___riscv_vmv_v_v_u8m4(vuint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m4(src,31); +} + + +vuint8m8_t test___riscv_vmv_v_v_u8m8(vuint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m8(src,31); +} + + +vuint16mf4_t test___riscv_vmv_v_v_u16mf4(vuint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf4(src,31); +} + + +vuint16mf2_t test___riscv_vmv_v_v_u16mf2(vuint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf2(src,31); +} + + +vuint16m1_t test___riscv_vmv_v_v_u16m1(vuint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m1(src,31); +} + + +vuint16m2_t test___riscv_vmv_v_v_u16m2(vuint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m2(src,31); +} + + +vuint16m4_t test___riscv_vmv_v_v_u16m4(vuint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m4(src,31); +} + + +vuint16m8_t test___riscv_vmv_v_v_u16m8(vuint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m8(src,31); +} + + +vuint32mf2_t test___riscv_vmv_v_v_u32mf2(vuint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32mf2(src,31); +} + + +vuint32m1_t test___riscv_vmv_v_v_u32m1(vuint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m1(src,31); +} + + +vuint32m2_t test___riscv_vmv_v_v_u32m2(vuint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m2(src,31); +} + + +vuint32m4_t test___riscv_vmv_v_v_u32m4(vuint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m4(src,31); +} + + +vuint32m8_t test___riscv_vmv_v_v_u32m8(vuint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m8(src,31); +} + + +vuint64m1_t test___riscv_vmv_v_v_u64m1(vuint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m1(src,31); +} + + +vuint64m2_t test___riscv_vmv_v_v_u64m2(vuint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m2(src,31); +} + + +vuint64m4_t test___riscv_vmv_v_v_u64m4(vuint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m4(src,31); +} + + +vuint64m8_t test___riscv_vmv_v_v_u64m8(vuint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m8(src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c new file mode 100644 index 00000000000..7ce80d3efe4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c @@ -0,0 +1,276 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_v_i8mf8(vint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf8(src,32); +} + + +vint8mf4_t test___riscv_vmv_v_v_i8mf4(vint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf4(src,32); +} + + +vint8mf2_t test___riscv_vmv_v_v_i8mf2(vint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf2(src,32); +} + + +vint8m1_t test___riscv_vmv_v_v_i8m1(vint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m1(src,32); +} + + +vint8m2_t test___riscv_vmv_v_v_i8m2(vint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m2(src,32); +} + + +vint8m4_t test___riscv_vmv_v_v_i8m4(vint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m4(src,32); +} + + +vint8m8_t test___riscv_vmv_v_v_i8m8(vint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m8(src,32); +} + + +vint16mf4_t test___riscv_vmv_v_v_i16mf4(vint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf4(src,32); +} + + +vint16mf2_t test___riscv_vmv_v_v_i16mf2(vint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf2(src,32); +} + + +vint16m1_t test___riscv_vmv_v_v_i16m1(vint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m1(src,32); +} + + +vint16m2_t test___riscv_vmv_v_v_i16m2(vint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m2(src,32); +} + + +vint16m4_t test___riscv_vmv_v_v_i16m4(vint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m4(src,32); +} + + +vint16m8_t test___riscv_vmv_v_v_i16m8(vint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m8(src,32); +} + + +vint32mf2_t test___riscv_vmv_v_v_i32mf2(vint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32mf2(src,32); +} + + +vint32m1_t test___riscv_vmv_v_v_i32m1(vint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m1(src,32); +} + + +vint32m2_t test___riscv_vmv_v_v_i32m2(vint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m2(src,32); +} + + +vint32m4_t test___riscv_vmv_v_v_i32m4(vint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m4(src,32); +} + + +vint32m8_t test___riscv_vmv_v_v_i32m8(vint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m8(src,32); +} + + +vint64m1_t test___riscv_vmv_v_v_i64m1(vint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m1(src,32); +} + + +vint64m2_t test___riscv_vmv_v_v_i64m2(vint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m2(src,32); +} + + +vint64m4_t test___riscv_vmv_v_v_i64m4(vint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m4(src,32); +} + + +vint64m8_t test___riscv_vmv_v_v_i64m8(vint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m8(src,32); +} + + +vuint8mf8_t test___riscv_vmv_v_v_u8mf8(vuint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf8(src,32); +} + + +vuint8mf4_t test___riscv_vmv_v_v_u8mf4(vuint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf4(src,32); +} + + +vuint8mf2_t test___riscv_vmv_v_v_u8mf2(vuint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf2(src,32); +} + + +vuint8m1_t test___riscv_vmv_v_v_u8m1(vuint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m1(src,32); +} + + +vuint8m2_t test___riscv_vmv_v_v_u8m2(vuint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m2(src,32); +} + + +vuint8m4_t test___riscv_vmv_v_v_u8m4(vuint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m4(src,32); +} + + +vuint8m8_t test___riscv_vmv_v_v_u8m8(vuint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m8(src,32); +} + + +vuint16mf4_t test___riscv_vmv_v_v_u16mf4(vuint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf4(src,32); +} + + +vuint16mf2_t test___riscv_vmv_v_v_u16mf2(vuint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf2(src,32); +} + + +vuint16m1_t test___riscv_vmv_v_v_u16m1(vuint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m1(src,32); +} + + +vuint16m2_t test___riscv_vmv_v_v_u16m2(vuint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m2(src,32); +} + + +vuint16m4_t test___riscv_vmv_v_v_u16m4(vuint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m4(src,32); +} + + +vuint16m8_t test___riscv_vmv_v_v_u16m8(vuint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m8(src,32); +} + + +vuint32mf2_t test___riscv_vmv_v_v_u32mf2(vuint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32mf2(src,32); +} + + +vuint32m1_t test___riscv_vmv_v_v_u32m1(vuint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m1(src,32); +} + + +vuint32m2_t test___riscv_vmv_v_v_u32m2(vuint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m2(src,32); +} + + +vuint32m4_t test___riscv_vmv_v_v_u32m4(vuint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m4(src,32); +} + + +vuint32m8_t test___riscv_vmv_v_v_u32m8(vuint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m8(src,32); +} + + +vuint64m1_t test___riscv_vmv_v_v_u64m1(vuint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m1(src,32); +} + + +vuint64m2_t test___riscv_vmv_v_v_u64m2(vuint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m2(src,32); +} + + +vuint64m4_t test___riscv_vmv_v_v_u64m4(vuint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m4(src,32); +} + + +vuint64m8_t test___riscv_vmv_v_v_u64m8(vuint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m8(src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c new file mode 100644 index 00000000000..fdd76c1b586 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c @@ -0,0 +1,276 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf8_tu(merge,src,vl); +} + + +vint8mf4_t test___riscv_vmv_v_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf4_tu(merge,src,vl); +} + + +vint8mf2_t test___riscv_vmv_v_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf2_tu(merge,src,vl); +} + + +vint8m1_t test___riscv_vmv_v_v_i8m1_tu(vint8m1_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m1_tu(merge,src,vl); +} + + +vint8m2_t test___riscv_vmv_v_v_i8m2_tu(vint8m2_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m2_tu(merge,src,vl); +} + + +vint8m4_t test___riscv_vmv_v_v_i8m4_tu(vint8m4_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m4_tu(merge,src,vl); +} + + +vint8m8_t test___riscv_vmv_v_v_i8m8_tu(vint8m8_t merge,vint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m8_tu(merge,src,vl); +} + + +vint16mf4_t test___riscv_vmv_v_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf4_tu(merge,src,vl); +} + + +vint16mf2_t test___riscv_vmv_v_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf2_tu(merge,src,vl); +} + + +vint16m1_t test___riscv_vmv_v_v_i16m1_tu(vint16m1_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m1_tu(merge,src,vl); +} + + +vint16m2_t test___riscv_vmv_v_v_i16m2_tu(vint16m2_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m2_tu(merge,src,vl); +} + + +vint16m4_t test___riscv_vmv_v_v_i16m4_tu(vint16m4_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m4_tu(merge,src,vl); +} + + +vint16m8_t test___riscv_vmv_v_v_i16m8_tu(vint16m8_t merge,vint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m8_tu(merge,src,vl); +} + + +vint32mf2_t test___riscv_vmv_v_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32mf2_tu(merge,src,vl); +} + + +vint32m1_t test___riscv_vmv_v_v_i32m1_tu(vint32m1_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m1_tu(merge,src,vl); +} + + +vint32m2_t test___riscv_vmv_v_v_i32m2_tu(vint32m2_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m2_tu(merge,src,vl); +} + + +vint32m4_t test___riscv_vmv_v_v_i32m4_tu(vint32m4_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m4_tu(merge,src,vl); +} + + +vint32m8_t test___riscv_vmv_v_v_i32m8_tu(vint32m8_t merge,vint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m8_tu(merge,src,vl); +} + + +vint64m1_t test___riscv_vmv_v_v_i64m1_tu(vint64m1_t merge,vint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m1_tu(merge,src,vl); +} + + +vint64m2_t test___riscv_vmv_v_v_i64m2_tu(vint64m2_t merge,vint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m2_tu(merge,src,vl); +} + + +vint64m4_t test___riscv_vmv_v_v_i64m4_tu(vint64m4_t merge,vint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m4_tu(merge,src,vl); +} + + +vint64m8_t test___riscv_vmv_v_v_i64m8_tu(vint64m8_t merge,vint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m8_tu(merge,src,vl); +} + + +vuint8mf8_t test___riscv_vmv_v_v_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf8_tu(merge,src,vl); +} + + +vuint8mf4_t test___riscv_vmv_v_v_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf4_tu(merge,src,vl); +} + + +vuint8mf2_t test___riscv_vmv_v_v_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf2_tu(merge,src,vl); +} + + +vuint8m1_t test___riscv_vmv_v_v_u8m1_tu(vuint8m1_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m1_tu(merge,src,vl); +} + + +vuint8m2_t test___riscv_vmv_v_v_u8m2_tu(vuint8m2_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m2_tu(merge,src,vl); +} + + +vuint8m4_t test___riscv_vmv_v_v_u8m4_tu(vuint8m4_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m4_tu(merge,src,vl); +} + + +vuint8m8_t test___riscv_vmv_v_v_u8m8_tu(vuint8m8_t merge,vuint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m8_tu(merge,src,vl); +} + + +vuint16mf4_t test___riscv_vmv_v_v_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf4_tu(merge,src,vl); +} + + +vuint16mf2_t test___riscv_vmv_v_v_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf2_tu(merge,src,vl); +} + + +vuint16m1_t test___riscv_vmv_v_v_u16m1_tu(vuint16m1_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m1_tu(merge,src,vl); +} + + +vuint16m2_t test___riscv_vmv_v_v_u16m2_tu(vuint16m2_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m2_tu(merge,src,vl); +} + + +vuint16m4_t test___riscv_vmv_v_v_u16m4_tu(vuint16m4_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m4_tu(merge,src,vl); +} + + +vuint16m8_t test___riscv_vmv_v_v_u16m8_tu(vuint16m8_t merge,vuint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m8_tu(merge,src,vl); +} + + +vuint32mf2_t test___riscv_vmv_v_v_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32mf2_tu(merge,src,vl); +} + + +vuint32m1_t test___riscv_vmv_v_v_u32m1_tu(vuint32m1_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m1_tu(merge,src,vl); +} + + +vuint32m2_t test___riscv_vmv_v_v_u32m2_tu(vuint32m2_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m2_tu(merge,src,vl); +} + + +vuint32m4_t test___riscv_vmv_v_v_u32m4_tu(vuint32m4_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m4_tu(merge,src,vl); +} + + +vuint32m8_t test___riscv_vmv_v_v_u32m8_tu(vuint32m8_t merge,vuint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m8_tu(merge,src,vl); +} + + +vuint64m1_t test___riscv_vmv_v_v_u64m1_tu(vuint64m1_t merge,vuint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m1_tu(merge,src,vl); +} + + +vuint64m2_t test___riscv_vmv_v_v_u64m2_tu(vuint64m2_t merge,vuint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m2_tu(merge,src,vl); +} + + +vuint64m4_t test___riscv_vmv_v_v_u64m4_tu(vuint64m4_t merge,vuint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m4_tu(merge,src,vl); +} + + +vuint64m8_t test___riscv_vmv_v_v_u64m8_tu(vuint64m8_t merge,vuint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m8_tu(merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c new file mode 100644 index 00000000000..74e3453bcb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c @@ -0,0 +1,276 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf8_tu(merge,src,31); +} + + +vint8mf4_t test___riscv_vmv_v_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf4_tu(merge,src,31); +} + + +vint8mf2_t test___riscv_vmv_v_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf2_tu(merge,src,31); +} + + +vint8m1_t test___riscv_vmv_v_v_i8m1_tu(vint8m1_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m1_tu(merge,src,31); +} + + +vint8m2_t test___riscv_vmv_v_v_i8m2_tu(vint8m2_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m2_tu(merge,src,31); +} + + +vint8m4_t test___riscv_vmv_v_v_i8m4_tu(vint8m4_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m4_tu(merge,src,31); +} + + +vint8m8_t test___riscv_vmv_v_v_i8m8_tu(vint8m8_t merge,vint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m8_tu(merge,src,31); +} + + +vint16mf4_t test___riscv_vmv_v_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf4_tu(merge,src,31); +} + + +vint16mf2_t test___riscv_vmv_v_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf2_tu(merge,src,31); +} + + +vint16m1_t test___riscv_vmv_v_v_i16m1_tu(vint16m1_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m1_tu(merge,src,31); +} + + +vint16m2_t test___riscv_vmv_v_v_i16m2_tu(vint16m2_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m2_tu(merge,src,31); +} + + +vint16m4_t test___riscv_vmv_v_v_i16m4_tu(vint16m4_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m4_tu(merge,src,31); +} + + +vint16m8_t test___riscv_vmv_v_v_i16m8_tu(vint16m8_t merge,vint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m8_tu(merge,src,31); +} + + +vint32mf2_t test___riscv_vmv_v_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32mf2_tu(merge,src,31); +} + + +vint32m1_t test___riscv_vmv_v_v_i32m1_tu(vint32m1_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m1_tu(merge,src,31); +} + + +vint32m2_t test___riscv_vmv_v_v_i32m2_tu(vint32m2_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m2_tu(merge,src,31); +} + + +vint32m4_t test___riscv_vmv_v_v_i32m4_tu(vint32m4_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m4_tu(merge,src,31); +} + + +vint32m8_t test___riscv_vmv_v_v_i32m8_tu(vint32m8_t merge,vint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m8_tu(merge,src,31); +} + + +vint64m1_t test___riscv_vmv_v_v_i64m1_tu(vint64m1_t merge,vint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m1_tu(merge,src,31); +} + + +vint64m2_t test___riscv_vmv_v_v_i64m2_tu(vint64m2_t merge,vint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m2_tu(merge,src,31); +} + + +vint64m4_t test___riscv_vmv_v_v_i64m4_tu(vint64m4_t merge,vint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m4_tu(merge,src,31); +} + + +vint64m8_t test___riscv_vmv_v_v_i64m8_tu(vint64m8_t merge,vint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m8_tu(merge,src,31); +} + + +vuint8mf8_t test___riscv_vmv_v_v_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf8_tu(merge,src,31); +} + + +vuint8mf4_t test___riscv_vmv_v_v_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf4_tu(merge,src,31); +} + + +vuint8mf2_t test___riscv_vmv_v_v_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf2_tu(merge,src,31); +} + + +vuint8m1_t test___riscv_vmv_v_v_u8m1_tu(vuint8m1_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m1_tu(merge,src,31); +} + + +vuint8m2_t test___riscv_vmv_v_v_u8m2_tu(vuint8m2_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m2_tu(merge,src,31); +} + + +vuint8m4_t test___riscv_vmv_v_v_u8m4_tu(vuint8m4_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m4_tu(merge,src,31); +} + + +vuint8m8_t test___riscv_vmv_v_v_u8m8_tu(vuint8m8_t merge,vuint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m8_tu(merge,src,31); +} + + +vuint16mf4_t test___riscv_vmv_v_v_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf4_tu(merge,src,31); +} + + +vuint16mf2_t test___riscv_vmv_v_v_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf2_tu(merge,src,31); +} + + +vuint16m1_t test___riscv_vmv_v_v_u16m1_tu(vuint16m1_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m1_tu(merge,src,31); +} + + +vuint16m2_t test___riscv_vmv_v_v_u16m2_tu(vuint16m2_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m2_tu(merge,src,31); +} + + +vuint16m4_t test___riscv_vmv_v_v_u16m4_tu(vuint16m4_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m4_tu(merge,src,31); +} + + +vuint16m8_t test___riscv_vmv_v_v_u16m8_tu(vuint16m8_t merge,vuint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m8_tu(merge,src,31); +} + + +vuint32mf2_t test___riscv_vmv_v_v_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32mf2_tu(merge,src,31); +} + + +vuint32m1_t test___riscv_vmv_v_v_u32m1_tu(vuint32m1_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m1_tu(merge,src,31); +} + + +vuint32m2_t test___riscv_vmv_v_v_u32m2_tu(vuint32m2_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m2_tu(merge,src,31); +} + + +vuint32m4_t test___riscv_vmv_v_v_u32m4_tu(vuint32m4_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m4_tu(merge,src,31); +} + + +vuint32m8_t test___riscv_vmv_v_v_u32m8_tu(vuint32m8_t merge,vuint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m8_tu(merge,src,31); +} + + +vuint64m1_t test___riscv_vmv_v_v_u64m1_tu(vuint64m1_t merge,vuint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m1_tu(merge,src,31); +} + + +vuint64m2_t test___riscv_vmv_v_v_u64m2_tu(vuint64m2_t merge,vuint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m2_tu(merge,src,31); +} + + +vuint64m4_t test___riscv_vmv_v_v_u64m4_tu(vuint64m4_t merge,vuint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m4_tu(merge,src,31); +} + + +vuint64m8_t test___riscv_vmv_v_v_u64m8_tu(vuint64m8_t merge,vuint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m8_tu(merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c new file mode 100644 index 00000000000..9ff1d6eee18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c @@ -0,0 +1,276 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmv_v_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf8_tu(merge,src,32); +} + + +vint8mf4_t test___riscv_vmv_v_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf4_tu(merge,src,32); +} + + +vint8mf2_t test___riscv_vmv_v_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8mf2_tu(merge,src,32); +} + + +vint8m1_t test___riscv_vmv_v_v_i8m1_tu(vint8m1_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m1_tu(merge,src,32); +} + + +vint8m2_t test___riscv_vmv_v_v_i8m2_tu(vint8m2_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m2_tu(merge,src,32); +} + + +vint8m4_t test___riscv_vmv_v_v_i8m4_tu(vint8m4_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m4_tu(merge,src,32); +} + + +vint8m8_t test___riscv_vmv_v_v_i8m8_tu(vint8m8_t merge,vint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i8m8_tu(merge,src,32); +} + + +vint16mf4_t test___riscv_vmv_v_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf4_tu(merge,src,32); +} + + +vint16mf2_t test___riscv_vmv_v_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16mf2_tu(merge,src,32); +} + + +vint16m1_t test___riscv_vmv_v_v_i16m1_tu(vint16m1_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m1_tu(merge,src,32); +} + + +vint16m2_t test___riscv_vmv_v_v_i16m2_tu(vint16m2_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m2_tu(merge,src,32); +} + + +vint16m4_t test___riscv_vmv_v_v_i16m4_tu(vint16m4_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m4_tu(merge,src,32); +} + + +vint16m8_t test___riscv_vmv_v_v_i16m8_tu(vint16m8_t merge,vint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i16m8_tu(merge,src,32); +} + + +vint32mf2_t test___riscv_vmv_v_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32mf2_tu(merge,src,32); +} + + +vint32m1_t test___riscv_vmv_v_v_i32m1_tu(vint32m1_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m1_tu(merge,src,32); +} + + +vint32m2_t test___riscv_vmv_v_v_i32m2_tu(vint32m2_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m2_tu(merge,src,32); +} + + +vint32m4_t test___riscv_vmv_v_v_i32m4_tu(vint32m4_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m4_tu(merge,src,32); +} + + +vint32m8_t test___riscv_vmv_v_v_i32m8_tu(vint32m8_t merge,vint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i32m8_tu(merge,src,32); +} + + +vint64m1_t test___riscv_vmv_v_v_i64m1_tu(vint64m1_t merge,vint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m1_tu(merge,src,32); +} + + +vint64m2_t test___riscv_vmv_v_v_i64m2_tu(vint64m2_t merge,vint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m2_tu(merge,src,32); +} + + +vint64m4_t test___riscv_vmv_v_v_i64m4_tu(vint64m4_t merge,vint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m4_tu(merge,src,32); +} + + +vint64m8_t test___riscv_vmv_v_v_i64m8_tu(vint64m8_t merge,vint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_i64m8_tu(merge,src,32); +} + + +vuint8mf8_t test___riscv_vmv_v_v_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf8_tu(merge,src,32); +} + + +vuint8mf4_t test___riscv_vmv_v_v_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf4_tu(merge,src,32); +} + + +vuint8mf2_t test___riscv_vmv_v_v_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8mf2_tu(merge,src,32); +} + + +vuint8m1_t test___riscv_vmv_v_v_u8m1_tu(vuint8m1_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m1_tu(merge,src,32); +} + + +vuint8m2_t test___riscv_vmv_v_v_u8m2_tu(vuint8m2_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m2_tu(merge,src,32); +} + + +vuint8m4_t test___riscv_vmv_v_v_u8m4_tu(vuint8m4_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m4_tu(merge,src,32); +} + + +vuint8m8_t test___riscv_vmv_v_v_u8m8_tu(vuint8m8_t merge,vuint8m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u8m8_tu(merge,src,32); +} + + +vuint16mf4_t test___riscv_vmv_v_v_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf4_tu(merge,src,32); +} + + +vuint16mf2_t test___riscv_vmv_v_v_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16mf2_tu(merge,src,32); +} + + +vuint16m1_t test___riscv_vmv_v_v_u16m1_tu(vuint16m1_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m1_tu(merge,src,32); +} + + +vuint16m2_t test___riscv_vmv_v_v_u16m2_tu(vuint16m2_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m2_tu(merge,src,32); +} + + +vuint16m4_t test___riscv_vmv_v_v_u16m4_tu(vuint16m4_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m4_tu(merge,src,32); +} + + +vuint16m8_t test___riscv_vmv_v_v_u16m8_tu(vuint16m8_t merge,vuint16m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u16m8_tu(merge,src,32); +} + + +vuint32mf2_t test___riscv_vmv_v_v_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32mf2_tu(merge,src,32); +} + + +vuint32m1_t test___riscv_vmv_v_v_u32m1_tu(vuint32m1_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m1_tu(merge,src,32); +} + + +vuint32m2_t test___riscv_vmv_v_v_u32m2_tu(vuint32m2_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m2_tu(merge,src,32); +} + + +vuint32m4_t test___riscv_vmv_v_v_u32m4_tu(vuint32m4_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m4_tu(merge,src,32); +} + + +vuint32m8_t test___riscv_vmv_v_v_u32m8_tu(vuint32m8_t merge,vuint32m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u32m8_tu(merge,src,32); +} + + +vuint64m1_t test___riscv_vmv_v_v_u64m1_tu(vuint64m1_t merge,vuint64m1_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m1_tu(merge,src,32); +} + + +vuint64m2_t test___riscv_vmv_v_v_u64m2_tu(vuint64m2_t merge,vuint64m2_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m2_tu(merge,src,32); +} + + +vuint64m4_t test___riscv_vmv_v_v_u64m4_tu(vuint64m4_t merge,vuint64m4_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m4_tu(merge,src,32); +} + + +vuint64m8_t test___riscv_vmv_v_v_u64m8_tu(vuint64m8_t merge,vuint64m8_t src,size_t vl) +{ + return __riscv_vmv_v_v_u64m8_tu(merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmv\.v\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */