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Fixes: 2016e2113d35 ("perf/amlogic: Add support for Amlogic meson G12 SoC DDR PMU driver") Signed-off-by: Jiucheng Xu --- drivers/perf/amlogic/meson_ddr_pmu_core.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) base-commit: e8a709dc2a9156f223ec953ae70a919e87ad7e9a diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c index b84346dbac2c..0b24dee1ed3c 100644 --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c @@ -156,10 +156,14 @@ static int meson_ddr_perf_event_add(struct perf_event *event, int flags) u64 config2 = event->attr.config2; int i; - for_each_set_bit(i, (const unsigned long *)&config1, sizeof(config1)) + for_each_set_bit(i, + (const unsigned long *)&config1, + BITS_PER_TYPE(config1)) meson_ddr_set_axi_filter(event, i); - for_each_set_bit(i, (const unsigned long *)&config2, sizeof(config2)) + for_each_set_bit(i, + (const unsigned long *)&config2, + BITS_PER_TYPE(config2)) meson_ddr_set_axi_filter(event, i + 64); if (flags & PERF_EF_START) From patchwork Thu Feb 9 11:54:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiucheng Xu X-Patchwork-Id: 54903 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp297814wrn; Thu, 9 Feb 2023 04:13:07 -0800 (PST) X-Google-Smtp-Source: AK7set/+YFBM2+ZVfyrB3IMfVTZ7Ljhp6hayZB4CDwpBu6WZAHEMjXXb05CDmk7Eo8KGdWOCveaA X-Received: by 2002:a17:902:e385:b0:199:4d57:639e with SMTP id g5-20020a170902e38500b001994d57639emr4031116ple.50.1675944787686; Thu, 09 Feb 2023 04:13:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675944787; cv=none; d=google.com; s=arc-20160816; b=xzFkauZffgnjVx2QQeMXp/2ab7/hnuFdyH18AUFn/YhpKsaSfhXq0QeUWSFISgwFai Y2JyOV1YPWZa6jBvQiTs7fJhBOePltQuU7Xrylrzz2Hz3ds1xH7+Xfml2RRIh8Uj+oSF sZAyhcqjXuDRQIgymPUQCWTaYIkLhZBZJ1CjtZYFc6K/GV58M6wDmL9slTDL8fdH+dym +lQf29cZ735dNr958+yBo6GRoqGGn866+VF3KnwucLp68NYemgBlIdu7T6QquE1M8hpz RFNADZyU2cGRgGhNslaD9KdVRGx8wnHuXZHh+DPR2KLOJMCJRDhao2+U79b96PFRgDSX j6gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=IwAqvCY70USuqD+RoDk6z/BFPOPBY2tV2zYRKhzyh28=; b=dVESsHhLZSv6GNk9SwODuQUXbEyHUVblKNn/747T++d0pE4o6UXma9UfQD2QyVcSoo 42oQwTwR1MOmNAKprcQ8g+bYYgsV8c4Tr8I6AxVaFYY7CLoNvo8BCxS9KMNfRy0Vt+FP 3SJsOJhMXRdmUZJTqlsMpko16pwsOG5OEls/7wGGJbz6tpqedFAH0NLYoFzLU/20v8JZ ZHXYDcOEySFjqMYdhCyHp2O7YhiocK2MZSjnN3TWk3beOmS60/93xCGh47XcHqEt6fi2 12V/+DdTiwM0QyQg2wXOqvWPk9h3L1rJAMNcbFHfzhd3U/DlITLfb8a5uhpXHWUrUO3G tgUg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c10-20020a170902848a00b00198cc7d0ef4si1615745plo.457.2023.02.09.04.12.55; Thu, 09 Feb 2023 04:13:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229972AbjBIMGE (ORCPT + 99 others); Thu, 9 Feb 2023 07:06:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229809AbjBIMFp (ORCPT ); Thu, 9 Feb 2023 07:05:45 -0500 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 112AC518D3 for ; Thu, 9 Feb 2023 03:55:19 -0800 (PST) Received: from droid01-xa.amlogic.com (10.88.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Thu, 9 Feb 2023 19:54:12 +0800 From: Jiucheng Xu To: Jiucheng Xu , Will Deacon , Mark Rutland , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl CC: Jianxin Pan , Kelvin Zhang , Chris Healy , Chris Healy , , , Subject: [PATCH 2/3] perf/amlogic: Fix large number of counter issue Date: Thu, 9 Feb 2023 19:54:02 +0800 Message-ID: <20230209115403.521868-2-jiucheng.xu@amlogic.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209115403.521868-1-jiucheng.xu@amlogic.com> References: <20230209115403.521868-1-jiucheng.xu@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.88.11.200] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757355481966711695?= X-GMAIL-MSGID: =?utf-8?q?1757355481966711695?= When use 1ms interval, very large number of counter happens once in a while as below: 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/ 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/ 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/ Root cause is the race between irq handler and pmu.read callback. Use spin lock to protect the sw&hw counters. Signed-off-by: Jiucheng Xu --- drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c index 0b24dee1ed3c..9b2e5d5c0626 100644 --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -23,6 +24,7 @@ struct ddr_pmu { struct pmu pmu; struct dmc_info info; struct dmc_counter counters; /* save counters from hw */ + spinlock_t lock; /* protect hw/sw counter */ bool pmu_enabled; struct device *dev; char *name; @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event) int idx; int chann_nr = pmu->info.hw_info->chann_nr; + spin_lock(&pmu->lock); /* get the remain counters in register. */ pmu->info.hw_info->get_counters(&pmu->info, &dc); ddr_cnt_addition(&sum_dc, &pmu->counters, &dc, chann_nr); + spin_unlock(&pmu->lock); switch (event->attr.config) { case ALL_CHAN_COUNTER_ID: @@ -355,6 +359,7 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id) pmu = dmc_info_to_pmu(info); + spin_lock(&pmu->lock); if (info->hw_info->irq_handler(info, &counters) != 0) goto out; @@ -372,6 +377,8 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id) * it in ISR to support continue mode. */ info->hw_info->enable(info); +out: + spin_unlock(&pmu->lock); dev_dbg(pmu->dev, "counts: %llu %llu %llu, %llu, %llu, %llu\t\t" "sum: %llu %llu %llu, %llu, %llu, %llu\n", @@ -388,7 +395,7 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id) pmu->counters.channel_cnt[1], pmu->counters.channel_cnt[2], pmu->counters.channel_cnt[3]); -out: + return IRQ_HANDLED; } @@ -539,6 +546,7 @@ int meson_ddr_pmu_create(struct platform_device *pdev) pmu->name = name; pmu->dev = &pdev->dev; pmu->pmu_enabled = false; + spin_lock_init(&pmu->lock); platform_set_drvdata(pdev, pmu); From patchwork Thu Feb 9 11:54:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiucheng Xu X-Patchwork-Id: 54904 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp297850wrn; Thu, 9 Feb 2023 04:13:11 -0800 (PST) X-Google-Smtp-Source: AK7set+U6IEEi772YJCMZbg1KBQk0MN0P3dlha5qjvDwy3Z0I+ouObDVfOnR4WpbURrbsy4Q8Utc X-Received: by 2002:a17:90b:3b87:b0:230:9f49:4335 with SMTP id pc7-20020a17090b3b8700b002309f494335mr12270164pjb.11.1675944791578; Thu, 09 Feb 2023 04:13:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675944791; cv=none; d=google.com; s=arc-20160816; b=VJamswGyQuSxmhNGLKg5npFw4+O1r864BIdp82vxX4BjEeVz0z97+rsw3/VW++YTI/ xQ3ruXl/eWgmTigYqcp4BZ2OoTRVj6w+CwWf5vkytwdT3q4S1IYmFRqqOSmhEe2MBXfv yDq5OTKRvjXyi0PVIPgCbmCKxr1jbRj7Ej/O5vBeazClX4ZZ7YSCb2WVSnQvYiKl+cfQ yfrX6STfTOkEHuyMRBGgRg8QBMgjwmvJzaKAGnjrnaN7bu0D3SxFWUcpy+REXhveMJxq gilddwqy1s/lD3H9jAY1v5oGG/plGjVz6fok/dfZZYbx80QmjXAciPt4XiCxWgWiwfk3 g2CA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=O6kUfH0lkb34oFi+ekesQOC+1heZErHrx0yMUSjN9uk=; b=KKEUEYTqLED3OoebY/auqGPWaRtGWWXoHz0FD6ys+8KNBQocN7IBttIVB5K2oIWpFR mTLCmaAtE6RzFsg+fbj8tKiNolH7t20luzLiivI6KA8WDaQIQtnyYtrARsCY9Ug5kiy3 wz+yG8r9N3V3Iw+sR9yK6ZHk7wKEukX0nWHJAA56Jjo4fNYKoyjqUXbsB9oLJ4EEJPiI kJweIoUerw7BnvXc26FfyO7ksMH5ov9UqFK3n/H9D+oNBXsduwVjiFIr5U6cgPxtx28+ PRO46GNb3WfcfXfoePeAuBs6T/P1peJAy6+a5Aw41Jf+h3lgz03oGwjwJW1YxxHSGvyI wmZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h2-20020a63b002000000b004fb471d2e31si1581336pgf.694.2023.02.09.04.12.57; Thu, 09 Feb 2023 04:13:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230062AbjBIMGI (ORCPT + 99 others); Thu, 9 Feb 2023 07:06:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229843AbjBIMFp (ORCPT ); Thu, 9 Feb 2023 07:05:45 -0500 X-Greylist: delayed 63 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Thu, 09 Feb 2023 03:55:17 PST Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2C18199E9 for ; Thu, 9 Feb 2023 03:55:17 -0800 (PST) Received: from droid01-xa.amlogic.com (10.88.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Thu, 9 Feb 2023 19:54:14 +0800 From: Jiucheng Xu To: Catalin Marinas , Will Deacon CC: Jianxin Pan , Kelvin Zhang , Chris Healy , Chris Healy , Neil Armstrong , , Jiucheng Xu , , Subject: [PATCH 3/3] arm64: defconfig: Add Meson DDR PMU as build-in Date: Thu, 9 Feb 2023 19:54:03 +0800 Message-ID: <20230209115403.521868-3-jiucheng.xu@amlogic.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209115403.521868-1-jiucheng.xu@amlogic.com> References: <20230209115403.521868-1-jiucheng.xu@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.88.11.200] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757355486246568810?= X-GMAIL-MSGID: =?utf-8?q?1757355486246568810?= Add Meson DDR PMU to defconfig so that build errors are caught. Signed-off-by: Jiucheng Xu Reviewed-by: Chris Healy --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 851e8f9be06d..9fefe659ade7 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1296,6 +1296,7 @@ CONFIG_ARM_DMC620_PMU=m CONFIG_QCOM_L2_PMU=y CONFIG_QCOM_L3_PMU=y CONFIG_HISI_PMU=y +CONFIG_MESON_DDR_PMU=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_IMX_OCOTP_SCU=y CONFIG_NVMEM_MTK_EFUSE=y