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Wed, 8 Feb 2023 03:17:15 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 03:17:15 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Wed, 8 Feb 2023 03:17:08 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 1/5] dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq Date: Wed, 8 Feb 2023 16:46:41 +0530 Message-ID: <20230208111645.3863534-2-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208111645.3863534-1-mmaddireddy@nvidia.com> References: <20230208111645.3863534-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT038:EE_|PH8PR12MB6868:EE_ X-MS-Office365-Filtering-Correlation-Id: 0021138e-f15f-4e10-dbbc-08db09c6112b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:29.7287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0021138e-f15f-4e10-dbbc-08db09c6112b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6868 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757261584485853916?= X-GMAIL-MSGID: =?utf-8?q?1757261584485853916?= From: Jeffy Chen Add device tree support to pass PCIe WAKE# pin information to PCI core driver. To support PCIe WAKE# and PCI irqs, add definition of the optional properties "interrupts" and "interrupt-names". These properties should be defined by the PCIe port to which wake capable Endpoint is connected, so the definition is added under "PCI-PCI Bridge properties" section. Signed-off-by: Jeffy Chen Signed-off-by: Manikanta Maddireddy Reviewed-by: Rob Herring --- Changes in v14: Move the device tree properties definition to "PCI-PCI Bridge properties" section and also update commit message. Changes in v13: None Changes in v12: Only add irq definitions for PCI devices and rewrite the commit message. Changes in v11: None Changes in v10: None Changes in v9: Add section for PCI devices and rewrite the commit message. Changes in v8: Add optional "pci", and rewrite commit message. Changes in v7: None Changes in v6: None Changes in v5: Move to pci.txt Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/pci/pci.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 6a8f2874a24d..53bd559a7305 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -71,6 +71,14 @@ Optional properties: trusted with relaxed DMA protection, as users could easily attach malicious devices to this port. +- interrupts: Interrupt specifier for each name in interrupt-names. +- interrupt-names: + May contain "wakeup" for PCIe WAKE# interrupt and "pci" for PCI interrupt. + The PCI devices may optionally include an 'interrupts' property that + represents the legacy PCI interrupt. And when we try to specify the PCIe + WAKE# pin, a corresponding 'interrupt-names' property is required to + distinguish them. + Example: pcie@10000000 { From patchwork Wed Feb 8 11:16:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 54407 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp3395453wrn; Wed, 8 Feb 2023 03:20:40 -0800 (PST) X-Google-Smtp-Source: AK7set8+tilvM+8r3eZk/ruiafS1Jy/LOWXScEGXjN58EtFDNTj67FHDHpxM8UpNSevwPG6nHwcp X-Received: by 2002:a62:a10b:0:b0:587:bdcc:bf0d with SMTP id b11-20020a62a10b000000b00587bdccbf0dmr6861995pff.0.1675855240267; Wed, 08 Feb 2023 03:20:40 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675855240; cv=pass; d=google.com; s=arc-20160816; b=GYXTWhADfSUXuhRvgxmg7wLBLmYfLs7a4LQK3wNW6RCaSeoWYeFecWgfSR97nWxJNs qRHlzi8Es0txeoAcg8tmarErJk/PemwUZO944q7nbcK3O9XMB2tjZpnrUtQOwgNhhsqZ X5wIGIwdsn50eDQB+bl/PTcdDMPdZMXk0cM8VEKbQPTGfg88kEswxHQISECo1FxwlYuM pprnOIdOKOEw8RZY3F3Ob0YB/nF4TBpmam8AICR1JeUt45W+TuRWPuDQx1B73y+TYdXL WU7trvigoZaucF3hSln67SGM1yGecLjKWGNmNzksxcob4dmHi+/KxfN7xqKMe0pjwrp3 wyWA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZAUMVkexY8e8tpIUPhxUFjFshADWTnT3tonlCqFWF5M=; b=qD3ChDJ8zY82sM6LGhct8WqpK+7oCjAvUkgAf7vr1VcnhxsAFhhQGhcGrZHxaZSOpy aqGuR8LGqBjuHcVpfEHros34E9Zv+ND3Rzew/F53DT++cXxo44j81h5m7TiKgKfHAg1/ Y44HtPLEwzPrZtLyK40FrWwiAu3IKbqW74WnDD7+0QDRFiNZ2GcWQHq7E1b1fcwaDPPp 186soP9PpgwDV9hKmKtQ2XGkVl2iGkbXeIi1e2wWDQgsTUrPm/TYXy54CsTJHxlCh8Yq P44pxQ7M6QIUHNbPyLruWoAIV+jG177opE1kkk06DSMTc7/CpZhEmgewW2QwM1Faj+ub fXmw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="r/o16C2i"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:30.7776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e99e9885-9c41-4aec-3964-08db09c611bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT102.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5962 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757261584606525409?= X-GMAIL-MSGID: =?utf-8?q?1757261584606525409?= From: Jeffy Chen Currently we are considering the first irq as the PCI interrupt pin, but a PCI device may have multiple interrupts(e.g. PCIe WAKE# pin). Only parse the PCI interrupt pin when the irq is unnamed or named as "pci". Signed-off-by: Jeffy Chen Signed-off-by: Manikanta Maddireddy Reviewed-by: Thierry Reding --- Changes in v14: Address Rob's comment on using of_property_match_string(). Changes in v13: None Changes in v12: None Changes in v11: Address Brian's comments. Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v3: None Changes in v2: None drivers/pci/of.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 196834ed44fe..ff897c40ed71 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -429,9 +429,17 @@ static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args * */ dn = pci_device_to_OF_node(pdev); if (dn) { - rc = of_irq_parse_one(dn, 0, out_irq); - if (!rc) - return rc; + int index = 0; + + index = of_property_match_string(dn, "interrupt-names", "pci"); + if (index == -EINVAL) /* Property doesn't exist */ + index = 0; + + if (index >= 0) { + rc = of_irq_parse_one(dn, index, out_irq); + if (!rc) + return rc; + } } /* From patchwork Wed Feb 8 11:16:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 54409 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp3395506wrn; Wed, 8 Feb 2023 03:20:45 -0800 (PST) X-Google-Smtp-Source: AK7set/eTxXg7cg7ZzR9dwT9chI0X9Vq0AAKZk62yf+5l8VVosoHuBWBFh2GN0AdgRnStMHNSkxX X-Received: by 2002:a17:90a:71c5:b0:230:9ae4:b5e4 with SMTP id m5-20020a17090a71c500b002309ae4b5e4mr170030pjs.0.1675855245094; Wed, 08 Feb 2023 03:20:45 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675855245; cv=pass; d=google.com; s=arc-20160816; b=oA/q5cxLA2+2yvPhygfwSJOKuMXv3r0BlGyVXy/pss9YNrlUvT3D2QEZXTveqKQbE9 Tf/g0uptXG2xG36iyv4bWISj6yG6fLeRAjmIC1x1RQWAGV3XMWzKJ0qzDilR7UblX4pq 5vLqJIKsnWEHOKxETruUsELpcRWN7Uaoi7k6B+bm0wWA6sk5xW1BKNlH3QsUkP5Forll 9FonDAWydPad9XVCQNiCJWS2NYDehcZLZNmtX4I9pApgiIHtJjnaXL9U+Ysywxmyd5N7 PaM4zQ5FQrB77ycczfkNvfSgU9lvKFsv0s3kAiRjMyCdjYooCK9RdVbnAYMuICEZbvH9 Hccw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CioCbog9+DveTk+544k+87uyyBf+XseOQ5gERTL8wJ8=; b=REQgykcBiYAvpSAEdM3+Ex3KhmstSWs4ogJZtjdPG9Osv0H5coFDfOImW8T/gM7pgn JDSXPyz35QgB+12uXJwPGu3N/3mxkabJhSjijf8OBliMUvUo7krHGcDuF5NJFR75iqBv j+s5oRFTCcpqChFoeEK3g7vCN59RqFtIZYJtNCYfPZBa4dKkWb0zW7ZU+2O2bxypgRPa 9O+dlYcvG42zpcTVSkO85qjcJhzXkjKepN1PuAcD/oL0HmsLI/rlcAl34A0Vzx7i3tBb fgBfbGqX5ovuIHkgq9FujLehOlIQQmsz7asqCUp8CpIKyQhYmsnKPUS/Ood6+6MGedz/ 0pNQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=GBg7LTyw; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Wed, 8 Feb 2023 03:17:30 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 03:17:29 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Wed, 8 Feb 2023 03:17:23 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 3/5] PCI / PM: Add support for the PCIe WAKE# signal for OF Date: Wed, 8 Feb 2023 16:46:43 +0530 Message-ID: <20230208111645.3863534-4-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208111645.3863534-1-mmaddireddy@nvidia.com> References: <20230208111645.3863534-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT025:EE_|PH8PR12MB8430:EE_ X-MS-Office365-Filtering-Correlation-Id: 973b9164-0dd2-4938-c10d-08db09c61a8c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:45.4476 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 973b9164-0dd2-4938-c10d-08db09c61a8c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8430 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757261589510798162?= X-GMAIL-MSGID: =?utf-8?q?1757261589510798162?= From: Jeffy Chen Add of_pci_setup_wake_irq() to parse the PCIe WAKE# interrupt from the device tree and set the wake irq. Add of_pci_teardown_wake_irq() to clear the wake irq. Call of_pci_setup_wake_irq() in pci_device_probe() to setup PCIe WAKE# interrupt during PCIe Endpoint enumeration. Enable or disable PCIe WAKE# interrupt in platform_pci_set_wakeup(). Signed-off-by: Jeffy Chen Signed-off-by: Manikanta Maddireddy --- Changes in v14: pci_platform_pm_ops structure is removed in latest kernel, so dropped pci-of driver. Instead, enable wake in platform_pci_set_wakeup(). Changes in v13: Fix compiler error reported by kbuild test robot Changes in v12: Enable the wake irq in noirq stage to avoid possible irq storm. Changes in v11: Only support 1-per-device PCIe WAKE# pin as suggested. Changes in v10: Use device_set_wakeup_capable() instead of device_set_wakeup_enable(), since dedicated wakeirq will be lost in device_set_wakeup_enable(false). Changes in v9: Fix check error in .cleanup(). Move dedicated wakeirq setup to setup() callback and use device_set_wakeup_enable() to enable/disable. Changes in v8: Add pci-of.c and use platform_pm_ops to handle the PCIe WAKE# signal. Changes in v7: Move PCIE_WAKE handling into pci core. Changes in v6: Fix device_init_wake error handling, and add some comments. Changes in v5: Rebase. Changes in v3: Fix error handling. Changes in v2: Use dev_pm_set_dedicated_wake_irq. drivers/pci/of.c | 49 ++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci-driver.c | 10 ++++++++ drivers/pci/pci.c | 7 ++++++ drivers/pci/pci.h | 8 +++++++ 4 files changed, 74 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index ff897c40ed71..1c348e63f175 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "pci.h" #ifdef CONFIG_PCI @@ -705,3 +706,51 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +int of_pci_setup_wake_irq(struct pci_dev *pdev) +{ + struct pci_dev *ppdev; + struct device_node *dn; + int ret, irq; + + /* Get the pci_dev of our parent. Hopefully it's a port. */ + ppdev = pdev->bus->self; + /* Nope, it's a host bridge. */ + if (!ppdev) + return 0; + + dn = pci_device_to_OF_node(ppdev); + if (!dn) + return 0; + + irq = of_irq_get_byname(dn, "wakeup"); + if (irq == -EPROBE_DEFER) { + return irq; + } else if (irq < 0) { + /* Ignore other errors, since a missing wakeup is non-fatal. */ + dev_info(&pdev->dev, "cannot get wakeup interrupt: %d\n", irq); + return 0; + } + + device_init_wakeup(&pdev->dev, true); + + ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, irq); + if (ret < 0) { + dev_err(&pdev->dev, "failed to set wake IRQ: %d\n", ret); + device_init_wakeup(&pdev->dev, false); + return ret; + } + + /* Start out disabled to avoid irq storm */ + dev_pm_disable_wake_irq(&pdev->dev); + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_setup_wake_irq); + +void of_pci_teardown_wake_irq(struct pci_dev *pdev) +{ + dev_pm_clear_wake_irq(&pdev->dev); + device_init_wakeup(&pdev->dev, false); +} +EXPORT_SYMBOL_GPL(of_pci_teardown_wake_irq); diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index d934c27491c4..fca966137fac 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -456,10 +457,17 @@ static int pci_device_probe(struct device *dev) if (error < 0) return error; + error = of_pci_setup_wake_irq(pci_dev); + if (error < 0) { + pcibios_free_irq(pci_dev); + return error; + } + pci_dev_get(pci_dev); error = __pci_device_probe(drv, pci_dev); if (error) { pcibios_free_irq(pci_dev); + of_pci_teardown_wake_irq(pci_dev); pci_dev_put(pci_dev); } @@ -471,6 +479,8 @@ static void pci_device_remove(struct device *dev) struct pci_dev *pci_dev = to_pci_dev(dev); struct pci_driver *drv = pci_dev->driver; + of_pci_teardown_wake_irq(pci_dev); + if (drv->remove) { pm_runtime_get_sync(dev); drv->remove(pci_dev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index fba95486caaf..332a0b98b6c3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -1052,6 +1053,12 @@ static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) if (pci_use_mid_pm()) return PCI_POWER_ERROR; + /* Enable or disable wakeirq if set via device tree. */ + if (enable) + dev_pm_enable_wake_irq(&dev->dev); + else + dev_pm_disable_wake_irq(&dev->dev); + return acpi_pci_wakeup(dev, enable); } diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 9ed3b5550043..83a2af148631 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -631,6 +631,8 @@ int of_pci_get_max_link_speed(struct device_node *node); u32 of_pci_get_slot_power_limit(struct device_node *node, u8 *slot_power_limit_value, u8 *slot_power_limit_scale); +int of_pci_setup_wake_irq(struct pci_dev *pdev); +void of_pci_teardown_wake_irq(struct pci_dev *pdev); void pci_set_of_node(struct pci_dev *dev); void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); @@ -669,6 +671,12 @@ of_pci_get_slot_power_limit(struct device_node *node, return 0; } +static inline int of_pci_setup_wake_irq(struct pci_dev *pdev) +{ + return 0; +} + +static inline void of_pci_teardown_wake_irq(struct pci_dev *pdev) { } static inline void pci_set_of_node(struct pci_dev *dev) { } static inline void pci_release_of_node(struct pci_dev *dev) { } static inline void pci_set_bus_of_node(struct pci_bus *bus) { } From patchwork Wed Feb 8 11:16:44 2023 Content-Type: text/plain; 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Signed-off-by: Manikanta Maddireddy --- Changes in v14: New patch in the series to support PCIe WAKE# in NVIDIA Jetson AGX Orin. .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 8a9747855d6b..9c89be263141 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2147,6 +2147,17 @@ pcie@14100000 { phys = <&p2u_hsio_3>; phy-names = "p2u-0"; + + pci@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "wakeup"; + }; }; pcie@14160000 { From patchwork Wed Feb 8 11:16:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 54411 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp3396141wrn; Wed, 8 Feb 2023 03:22:06 -0800 (PST) X-Google-Smtp-Source: AK7set+aoxf5A1+QA6AC0oCwtiNH5UZSAMm8c0Aj9F9Dkg6a6Xeoob27YczULYK9eXULhhBX1QJ3 X-Received: by 2002:a17:902:f685:b0:199:190c:3c0c with SMTP id l5-20020a170902f68500b00199190c3c0cmr7720493plg.2.1675855326414; Wed, 08 Feb 2023 03:22:06 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675855326; cv=pass; d=google.com; s=arc-20160816; b=i+wY5ujEjEizhpGywQDahDIhyWf/BisJWJYeQoNAnIunKbDzvuJfqptN3GR4V012iq c1eROFWAD3JFMR0ZjpT5Rd9yEOam6E+n3rrvVVpOzJKE/meJk0zgEzwr6chRF45CHjLA aW24d9vXpp79RkBKhV0fJujVhsl6hghLBJLKmQ8zqvEPV8qTF4Oiojj0fhHyrR5CxSAH 3XlCAKjKZBRA70WOpOMdOlmiag49xNeOmvl4GowZK0IKzwXoKwZhcobSU4sRruNfuA0D dW7UZO5HOcTyMmjx+18V4kmPknIzjatWnXy16IYvO6FxhvalBUv3W55Pi0t2Jxbma7i8 ECng== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gFJuUx+vshbAtE3PcS6oKKtJhnpxHv7OrgQo9Xd4G4g=; b=XtYbCaopQAzC3ZabMu9PwKAe1Pmy8qPgcd2Z5vw2ExIbKv7CFs71B+O293sBDzlwcD QmQRjlp1c8BGL6cExQM23RhhNaCqg8/oQ6rBg6hRcjgw93IIso9rUiNZJo4NFS4xHdiF fmKJMdMr895fu7e/ch8kH2wnvqAzjnNDxib5X1549K+lg+bWThyUZi77rRNtfYhDFGHe Wr29s1onaCU8W8Dy1EGsjr9Y3W0C250sVVxlprbDYEDclHFy1ZergboDB2bfNC/jO4Dz nF5N4+j4KFkKyVSk1JE9PCthwoE0HVOEDJXghsdHDJEHe6/Fi/X89u29zACfYysuBSY4 DMCw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=SH0Nd86d; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Manikanta Maddireddy --- Changes in v14: New patch in the series to support PCIe WAKE# in NVIDIA Jetson AGX Orin. drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index cf4cfbf9f7c5..139ee853c32b 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -4225,6 +4225,7 @@ static const char * const tegra234_reset_sources[] = { }; static const struct tegra_wake_event tegra234_wake_events[] = { + TEGRA_WAKE_GPIO("pcie", 1, 0, TEGRA234_MAIN_GPIO(L, 2)), TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), TEGRA_WAKE_IRQ("rtc", 73, 10), };