From patchwork Wed Feb 8 02:49:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 54149 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp3213690wrn; Tue, 7 Feb 2023 18:50:18 -0800 (PST) X-Google-Smtp-Source: AK7set/9ZrZldN08MRF+CHpOwC661QeUw5lLcfkNAEJ3lmz/OZiigu2fxCohkAPkuQlKw5W3upkt X-Received: by 2002:a17:907:6f12:b0:8aa:c145:f6ff with SMTP id sy18-20020a1709076f1200b008aac145f6ffmr1997910ejc.46.1675824618239; Tue, 07 Feb 2023 18:50:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675824618; cv=none; d=google.com; s=arc-20160816; b=UOB2JbFBFLViA6kpRQlJE5tjf9I0iyzGmHmjTo0gEktbHWR06EfHynA+fUtnhrsmC7 WJE4f3cjpoKWILKIbIjgXy4diolOSwrt82rLZcCKi1gn8U9UO9g3YmPjJs6/4Z68nLC+ F6y3SIVvosMbGKyLTBIJLxWY/OcM50TR02prLQq+2IsoBPXrGGEhbZ6zUHCDxGJIY6Do grKKRZsRnWU40WV5ssfweSQhUU08mjmi96/3LXIzX7ez2E7G/NgWSgfsAYCzTZDnS720 U6koGcGfh8ZN80D8Xfzmni3WXHNkKI8udcS9MkJBJDNeIHosLkP/jlwlPdyhANx+KLlv V8Dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=1PFWBmHyWqJnAh68DrxLacPCDkitYbwlkWNaGp6u2V0=; b=Dwo27LW/BD8POCfQC4djNGRR+iHa3re7b+qNZsBtb2h6/IGNrECmFmr+tdmJBoJqT5 DZxCkJzjAtYh+rvrQAboslx82G5VXS2rcArX1QUypmv2l4sehuSOuJup9Nt7CkJNr/At +EUJmfQ6AizAYHQhuSht+Y7It1ETE5j6muIjRDepHxaEvNu+pabCqc21IIaDJ/4FaJ2A PvnrMcWyjyHA/bIa7aMs8GoQElGlxueCYK9pm537BNW1FEdb67XT52Z2zujxwzSB20fZ LqhNLUVfx07Z0Dj/c1VBg0JA0VrTlOEiSTlik4jODC3KiIQn90QQ38ZP2sxEgb+1yc4D P6qg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id c24-20020a17090620d800b0088741fb18d8si26397590ejc.338.2023.02.07.18.50.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 18:50:18 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5CE76385841D for ; Wed, 8 Feb 2023 02:50:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id 0D9BC3858280 for ; Wed, 8 Feb 2023 02:49:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0D9BC3858280 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1675824552tcg5lphu Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 08 Feb 2023 10:49:11 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: q+yjhizk/eLGN6q1KhwUpnJaytfaBboBkeJ6x1jforfRtgvKC18PE+5vW8rVm shxUGlZZ8WS09BDlTt70h5KNtKULCSOclBJC/MrCfCGxmtQVv9Mj1vIjt8U3M0VoJr0lp58 aaiDIsilbe4U7i0rM3GHvD0KRuxi1sPW9WxBsUpV3Cyhf6irVzkLdMzE7YeSS9x2p1cjJO+ 1uK9DkL1b16iiDC4svu1rWz66xmksuIC9I8BGsHbtGfezAz7PqE2kZq2EauUZ71gSSUfRMr +hF+hE4Tgr1sHpjlmQPKr0oxrwOa2e8QHx1mvqlEzZNluvKeP4z0ag4WUfb6qCJS5H6iMVx x6L/UJXTYr1tMHuba8o1xxJ9AkgN3ocrry+8IZOa+4ZPGKurss= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vsbc C++ API tests Date: Wed, 8 Feb 2023 10:49:10 +0800 Message-Id: <20230208024910.230380-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757229475016745836?= X-GMAIL-MSGID: =?utf-8?q?1757229475016745836?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vsbc_vvm-1.C: New test. * g++.target/riscv/rvv/base/vsbc_vvm-2.C: New test. * g++.target/riscv/rvv/base/vsbc_vvm-3.C: New test. * g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C: New test. * g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C: New test. * g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C: New test. --- .../g++.target/riscv/rvv/base/vsbc_vvm-1.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm-2.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm-3.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv32-1.C | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv32-2.C | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv32-3.C | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv64-1.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv64-2.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_rv64-3.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv32-1.C | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv32-2.C | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv32-3.C | 289 +++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv64-1.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv64-2.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vsbc_vxm_tu_rv64-3.C | 292 ++++++++++++++++++ 18 files changed, 5238 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-1.C new file mode 100644 index 00000000000..bf475cfa9e8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8mf4_t test___riscv_vsbc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8mf2_t test___riscv_vsbc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m1_t test___riscv_vsbc(vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m2_t test___riscv_vsbc(vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m4_t test___riscv_vsbc(vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m8_t test___riscv_vsbc(vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16mf4_t test___riscv_vsbc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16mf2_t test___riscv_vsbc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m1_t test___riscv_vsbc(vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m2_t test___riscv_vsbc(vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m4_t test___riscv_vsbc(vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m8_t test___riscv_vsbc(vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32mf2_t test___riscv_vsbc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m1_t test___riscv_vsbc(vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m2_t test___riscv_vsbc(vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m4_t test___riscv_vsbc(vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m8_t test___riscv_vsbc(vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m1_t test___riscv_vsbc(vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m2_t test___riscv_vsbc(vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m4_t test___riscv_vsbc(vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m8_t test___riscv_vsbc(vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8mf8_t test___riscv_vsbc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8mf4_t test___riscv_vsbc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8mf2_t test___riscv_vsbc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m1_t test___riscv_vsbc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m2_t test___riscv_vsbc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m4_t test___riscv_vsbc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m8_t test___riscv_vsbc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16mf4_t test___riscv_vsbc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16mf2_t test___riscv_vsbc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m1_t test___riscv_vsbc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m2_t test___riscv_vsbc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m4_t test___riscv_vsbc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m8_t test___riscv_vsbc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32mf2_t test___riscv_vsbc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m1_t test___riscv_vsbc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m2_t test___riscv_vsbc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m4_t test___riscv_vsbc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m8_t test___riscv_vsbc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m1_t test___riscv_vsbc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m2_t test___riscv_vsbc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m4_t test___riscv_vsbc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m8_t test___riscv_vsbc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-2.C new file mode 100644 index 00000000000..6a7de4e1a91 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8mf4_t test___riscv_vsbc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8mf2_t test___riscv_vsbc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m1_t test___riscv_vsbc(vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m2_t test___riscv_vsbc(vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m4_t test___riscv_vsbc(vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m8_t test___riscv_vsbc(vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16mf4_t test___riscv_vsbc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16mf2_t test___riscv_vsbc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m1_t test___riscv_vsbc(vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m2_t test___riscv_vsbc(vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m4_t test___riscv_vsbc(vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m8_t test___riscv_vsbc(vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32mf2_t test___riscv_vsbc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m1_t test___riscv_vsbc(vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m2_t test___riscv_vsbc(vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m4_t test___riscv_vsbc(vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m8_t test___riscv_vsbc(vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m1_t test___riscv_vsbc(vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m2_t test___riscv_vsbc(vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m4_t test___riscv_vsbc(vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m8_t test___riscv_vsbc(vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8mf8_t test___riscv_vsbc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8mf4_t test___riscv_vsbc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8mf2_t test___riscv_vsbc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m1_t test___riscv_vsbc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m2_t test___riscv_vsbc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m4_t test___riscv_vsbc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m8_t test___riscv_vsbc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16mf4_t test___riscv_vsbc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16mf2_t test___riscv_vsbc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m1_t test___riscv_vsbc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m2_t test___riscv_vsbc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m4_t test___riscv_vsbc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m8_t test___riscv_vsbc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32mf2_t test___riscv_vsbc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m1_t test___riscv_vsbc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m2_t test___riscv_vsbc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m4_t test___riscv_vsbc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m8_t test___riscv_vsbc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m1_t test___riscv_vsbc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m2_t test___riscv_vsbc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m4_t test___riscv_vsbc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m8_t test___riscv_vsbc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-3.C new file mode 100644 index 00000000000..a0b6b7cd460 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8mf4_t test___riscv_vsbc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8mf2_t test___riscv_vsbc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m1_t test___riscv_vsbc(vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m2_t test___riscv_vsbc(vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m4_t test___riscv_vsbc(vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m8_t test___riscv_vsbc(vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16mf4_t test___riscv_vsbc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16mf2_t test___riscv_vsbc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m1_t test___riscv_vsbc(vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m2_t test___riscv_vsbc(vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m4_t test___riscv_vsbc(vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m8_t test___riscv_vsbc(vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32mf2_t test___riscv_vsbc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m1_t test___riscv_vsbc(vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m2_t test___riscv_vsbc(vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m4_t test___riscv_vsbc(vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m8_t test___riscv_vsbc(vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m1_t test___riscv_vsbc(vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m2_t test___riscv_vsbc(vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m4_t test___riscv_vsbc(vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m8_t test___riscv_vsbc(vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8mf8_t test___riscv_vsbc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8mf4_t test___riscv_vsbc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8mf2_t test___riscv_vsbc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m1_t test___riscv_vsbc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m2_t test___riscv_vsbc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m4_t test___riscv_vsbc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m8_t test___riscv_vsbc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16mf4_t test___riscv_vsbc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16mf2_t test___riscv_vsbc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m1_t test___riscv_vsbc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m2_t test___riscv_vsbc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m4_t test___riscv_vsbc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m8_t test___riscv_vsbc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32mf2_t test___riscv_vsbc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m1_t test___riscv_vsbc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m2_t test___riscv_vsbc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m4_t test___riscv_vsbc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m8_t test___riscv_vsbc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m1_t test___riscv_vsbc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m2_t test___riscv_vsbc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m4_t test___riscv_vsbc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m8_t test___riscv_vsbc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C new file mode 100644 index 00000000000..f9a6994b762 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vsbc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf4_t test____riscv_vsbc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf2_t test____riscv_vsbc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m1_t test____riscv_vsbc_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m2_t test____riscv_vsbc_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m4_t test____riscv_vsbc_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m8_t test____riscv_vsbc_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf4_t test____riscv_vsbc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf2_t test____riscv_vsbc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m1_t test____riscv_vsbc_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m2_t test____riscv_vsbc_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m4_t test____riscv_vsbc_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m8_t test____riscv_vsbc_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32mf2_t test____riscv_vsbc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m1_t test____riscv_vsbc_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m2_t test____riscv_vsbc_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m4_t test____riscv_vsbc_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m8_t test____riscv_vsbc_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m1_t test____riscv_vsbc_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m2_t test____riscv_vsbc_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m4_t test____riscv_vsbc_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m8_t test____riscv_vsbc_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf8_t test____riscv_vsbc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf4_t test____riscv_vsbc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf2_t test____riscv_vsbc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m1_t test____riscv_vsbc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m2_t test____riscv_vsbc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m4_t test____riscv_vsbc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m8_t test____riscv_vsbc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf4_t test____riscv_vsbc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf2_t test____riscv_vsbc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m1_t test____riscv_vsbc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m2_t test____riscv_vsbc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m4_t test____riscv_vsbc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m8_t test____riscv_vsbc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32mf2_t test____riscv_vsbc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m1_t test____riscv_vsbc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m2_t test____riscv_vsbc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m4_t test____riscv_vsbc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m8_t test____riscv_vsbc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m1_t test____riscv_vsbc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m2_t test____riscv_vsbc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m4_t test____riscv_vsbc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m8_t test____riscv_vsbc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C new file mode 100644 index 00000000000..5c447b2e741 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vsbc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf4_t test____riscv_vsbc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf2_t test____riscv_vsbc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m1_t test____riscv_vsbc_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m2_t test____riscv_vsbc_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m4_t test____riscv_vsbc_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m8_t test____riscv_vsbc_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf4_t test____riscv_vsbc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf2_t test____riscv_vsbc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m1_t test____riscv_vsbc_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m2_t test____riscv_vsbc_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m4_t test____riscv_vsbc_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m8_t test____riscv_vsbc_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32mf2_t test____riscv_vsbc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m1_t test____riscv_vsbc_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m2_t test____riscv_vsbc_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m4_t test____riscv_vsbc_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m8_t test____riscv_vsbc_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m1_t test____riscv_vsbc_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m2_t test____riscv_vsbc_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m4_t test____riscv_vsbc_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m8_t test____riscv_vsbc_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf8_t test____riscv_vsbc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf4_t test____riscv_vsbc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf2_t test____riscv_vsbc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m1_t test____riscv_vsbc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m2_t test____riscv_vsbc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m4_t test____riscv_vsbc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m8_t test____riscv_vsbc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf4_t test____riscv_vsbc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf2_t test____riscv_vsbc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m1_t test____riscv_vsbc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m2_t test____riscv_vsbc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m4_t test____riscv_vsbc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m8_t test____riscv_vsbc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32mf2_t test____riscv_vsbc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m1_t test____riscv_vsbc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m2_t test____riscv_vsbc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m4_t test____riscv_vsbc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m8_t test____riscv_vsbc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m1_t test____riscv_vsbc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m2_t test____riscv_vsbc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m4_t test____riscv_vsbc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m8_t test____riscv_vsbc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C new file mode 100644 index 00000000000..af032d690b9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vsbc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf4_t test____riscv_vsbc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf2_t test____riscv_vsbc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m1_t test____riscv_vsbc_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m2_t test____riscv_vsbc_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m4_t test____riscv_vsbc_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m8_t test____riscv_vsbc_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf4_t test____riscv_vsbc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf2_t test____riscv_vsbc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m1_t test____riscv_vsbc_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m2_t test____riscv_vsbc_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m4_t test____riscv_vsbc_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m8_t test____riscv_vsbc_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32mf2_t test____riscv_vsbc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m1_t test____riscv_vsbc_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m2_t test____riscv_vsbc_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m4_t test____riscv_vsbc_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m8_t test____riscv_vsbc_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m1_t test____riscv_vsbc_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m2_t test____riscv_vsbc_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m4_t test____riscv_vsbc_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m8_t test____riscv_vsbc_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf8_t test____riscv_vsbc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf4_t test____riscv_vsbc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf2_t test____riscv_vsbc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m1_t test____riscv_vsbc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m2_t test____riscv_vsbc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m4_t test____riscv_vsbc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m8_t test____riscv_vsbc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf4_t test____riscv_vsbc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf2_t test____riscv_vsbc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m1_t test____riscv_vsbc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m2_t test____riscv_vsbc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m4_t test____riscv_vsbc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m8_t test____riscv_vsbc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32mf2_t test____riscv_vsbc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m1_t test____riscv_vsbc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m2_t test____riscv_vsbc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m4_t test____riscv_vsbc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m8_t test____riscv_vsbc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m1_t test____riscv_vsbc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m2_t test____riscv_vsbc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m4_t test____riscv_vsbc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m8_t test____riscv_vsbc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C new file mode 100644 index 00000000000..6502614f68f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8mf4_t test___riscv_vsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8mf2_t test___riscv_vsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m1_t test___riscv_vsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m2_t test___riscv_vsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m4_t test___riscv_vsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m8_t test___riscv_vsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16mf4_t test___riscv_vsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16mf2_t test___riscv_vsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m1_t test___riscv_vsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m2_t test___riscv_vsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m4_t test___riscv_vsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m8_t test___riscv_vsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32mf2_t test___riscv_vsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m1_t test___riscv_vsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m2_t test___riscv_vsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m4_t test___riscv_vsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m8_t test___riscv_vsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m1_t test___riscv_vsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m2_t test___riscv_vsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m4_t test___riscv_vsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m8_t test___riscv_vsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8mf8_t test___riscv_vsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8mf4_t test___riscv_vsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8mf2_t test___riscv_vsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m1_t test___riscv_vsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m2_t test___riscv_vsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m4_t test___riscv_vsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m8_t test___riscv_vsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16mf4_t test___riscv_vsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16mf2_t test___riscv_vsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m1_t test___riscv_vsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m2_t test___riscv_vsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m4_t test___riscv_vsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m8_t test___riscv_vsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32mf2_t test___riscv_vsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m1_t test___riscv_vsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m2_t test___riscv_vsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m4_t test___riscv_vsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m8_t test___riscv_vsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m1_t test___riscv_vsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m2_t test___riscv_vsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m4_t test___riscv_vsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m8_t test___riscv_vsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C new file mode 100644 index 00000000000..ded142e514a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8mf4_t test___riscv_vsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8mf2_t test___riscv_vsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m1_t test___riscv_vsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m2_t test___riscv_vsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m4_t test___riscv_vsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m8_t test___riscv_vsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16mf4_t test___riscv_vsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16mf2_t test___riscv_vsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m1_t test___riscv_vsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m2_t test___riscv_vsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m4_t test___riscv_vsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m8_t test___riscv_vsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32mf2_t test___riscv_vsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m1_t test___riscv_vsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m2_t test___riscv_vsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m4_t test___riscv_vsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m8_t test___riscv_vsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m1_t test___riscv_vsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m2_t test___riscv_vsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m4_t test___riscv_vsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m8_t test___riscv_vsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8mf8_t test___riscv_vsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8mf4_t test___riscv_vsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8mf2_t test___riscv_vsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m1_t test___riscv_vsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m2_t test___riscv_vsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m4_t test___riscv_vsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m8_t test___riscv_vsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16mf4_t test___riscv_vsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16mf2_t test___riscv_vsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m1_t test___riscv_vsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m2_t test___riscv_vsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m4_t test___riscv_vsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m8_t test___riscv_vsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32mf2_t test___riscv_vsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m1_t test___riscv_vsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m2_t test___riscv_vsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m4_t test___riscv_vsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m8_t test___riscv_vsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m1_t test___riscv_vsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m2_t test___riscv_vsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m4_t test___riscv_vsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m8_t test___riscv_vsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C new file mode 100644 index 00000000000..b71f81710e1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8mf4_t test___riscv_vsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8mf2_t test___riscv_vsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m1_t test___riscv_vsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m2_t test___riscv_vsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m4_t test___riscv_vsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m8_t test___riscv_vsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16mf4_t test___riscv_vsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16mf2_t test___riscv_vsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m1_t test___riscv_vsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m2_t test___riscv_vsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m4_t test___riscv_vsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m8_t test___riscv_vsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32mf2_t test___riscv_vsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m1_t test___riscv_vsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m2_t test___riscv_vsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m4_t test___riscv_vsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m8_t test___riscv_vsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m1_t test___riscv_vsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m2_t test___riscv_vsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m4_t test___riscv_vsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m8_t test___riscv_vsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8mf8_t test___riscv_vsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8mf4_t test___riscv_vsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8mf2_t test___riscv_vsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m1_t test___riscv_vsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m2_t test___riscv_vsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m4_t test___riscv_vsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m8_t test___riscv_vsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16mf4_t test___riscv_vsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16mf2_t test___riscv_vsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m1_t test___riscv_vsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m2_t test___riscv_vsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m4_t test___riscv_vsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m8_t test___riscv_vsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32mf2_t test___riscv_vsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m1_t test___riscv_vsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m2_t test___riscv_vsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m4_t test___riscv_vsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m8_t test___riscv_vsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m1_t test___riscv_vsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m2_t test___riscv_vsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m4_t test___riscv_vsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m8_t test___riscv_vsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C new file mode 100644 index 00000000000..ef72c1bfa22 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8mf4_t test___riscv_vsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8mf2_t test___riscv_vsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m1_t test___riscv_vsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m2_t test___riscv_vsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m4_t test___riscv_vsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint8m8_t test___riscv_vsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16mf4_t test___riscv_vsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16mf2_t test___riscv_vsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m1_t test___riscv_vsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m2_t test___riscv_vsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m4_t test___riscv_vsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint16m8_t test___riscv_vsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32mf2_t test___riscv_vsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m1_t test___riscv_vsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m2_t test___riscv_vsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m4_t test___riscv_vsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint32m8_t test___riscv_vsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m1_t test___riscv_vsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m2_t test___riscv_vsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m4_t test___riscv_vsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vint64m8_t test___riscv_vsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8mf8_t test___riscv_vsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8mf4_t test___riscv_vsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8mf2_t test___riscv_vsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m1_t test___riscv_vsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m2_t test___riscv_vsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m4_t test___riscv_vsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint8m8_t test___riscv_vsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16mf4_t test___riscv_vsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16mf2_t test___riscv_vsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m1_t test___riscv_vsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m2_t test___riscv_vsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m4_t test___riscv_vsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint16m8_t test___riscv_vsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32mf2_t test___riscv_vsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m1_t test___riscv_vsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m2_t test___riscv_vsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m4_t test___riscv_vsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint32m8_t test___riscv_vsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m1_t test___riscv_vsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m2_t test___riscv_vsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m4_t test___riscv_vsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + +vuint64m8_t test___riscv_vsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C new file mode 100644 index 00000000000..356ed92b003 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8mf4_t test___riscv_vsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8mf2_t test___riscv_vsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m1_t test___riscv_vsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m2_t test___riscv_vsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m4_t test___riscv_vsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint8m8_t test___riscv_vsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16mf4_t test___riscv_vsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16mf2_t test___riscv_vsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m1_t test___riscv_vsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m2_t test___riscv_vsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m4_t test___riscv_vsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint16m8_t test___riscv_vsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32mf2_t test___riscv_vsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m1_t test___riscv_vsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m2_t test___riscv_vsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m4_t test___riscv_vsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint32m8_t test___riscv_vsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m1_t test___riscv_vsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m2_t test___riscv_vsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m4_t test___riscv_vsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vint64m8_t test___riscv_vsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8mf8_t test___riscv_vsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8mf4_t test___riscv_vsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8mf2_t test___riscv_vsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m1_t test___riscv_vsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m2_t test___riscv_vsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m4_t test___riscv_vsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint8m8_t test___riscv_vsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16mf4_t test___riscv_vsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16mf2_t test___riscv_vsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m1_t test___riscv_vsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m2_t test___riscv_vsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m4_t test___riscv_vsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint16m8_t test___riscv_vsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32mf2_t test___riscv_vsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m1_t test___riscv_vsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m2_t test___riscv_vsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m4_t test___riscv_vsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint32m8_t test___riscv_vsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m1_t test___riscv_vsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m2_t test___riscv_vsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m4_t test___riscv_vsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + +vuint64m8_t test___riscv_vsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C new file mode 100644 index 00000000000..05e3f1fc19b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsbc(vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8mf4_t test___riscv_vsbc(vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8mf2_t test___riscv_vsbc(vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m1_t test___riscv_vsbc(vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m2_t test___riscv_vsbc(vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m4_t test___riscv_vsbc(vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint8m8_t test___riscv_vsbc(vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16mf4_t test___riscv_vsbc(vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16mf2_t test___riscv_vsbc(vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m1_t test___riscv_vsbc(vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m2_t test___riscv_vsbc(vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m4_t test___riscv_vsbc(vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint16m8_t test___riscv_vsbc(vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32mf2_t test___riscv_vsbc(vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m1_t test___riscv_vsbc(vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m2_t test___riscv_vsbc(vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m4_t test___riscv_vsbc(vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint32m8_t test___riscv_vsbc(vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m1_t test___riscv_vsbc(vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m2_t test___riscv_vsbc(vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m4_t test___riscv_vsbc(vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vint64m8_t test___riscv_vsbc(vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8mf8_t test___riscv_vsbc(vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8mf4_t test___riscv_vsbc(vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8mf2_t test___riscv_vsbc(vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m1_t test___riscv_vsbc(vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m2_t test___riscv_vsbc(vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m4_t test___riscv_vsbc(vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint8m8_t test___riscv_vsbc(vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16mf4_t test___riscv_vsbc(vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16mf2_t test___riscv_vsbc(vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m1_t test___riscv_vsbc(vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m2_t test___riscv_vsbc(vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m4_t test___riscv_vsbc(vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint16m8_t test___riscv_vsbc(vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32mf2_t test___riscv_vsbc(vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m1_t test___riscv_vsbc(vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m2_t test___riscv_vsbc(vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m4_t test___riscv_vsbc(vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint32m8_t test___riscv_vsbc(vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m1_t test___riscv_vsbc(vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m2_t test___riscv_vsbc(vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m4_t test___riscv_vsbc(vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + +vuint64m8_t test___riscv_vsbc(vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc(op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C new file mode 100644 index 00000000000..ef1de2b335f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vsbc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf4_t test____riscv_vsbc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf2_t test____riscv_vsbc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m1_t test____riscv_vsbc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m2_t test____riscv_vsbc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m4_t test____riscv_vsbc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m8_t test____riscv_vsbc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf4_t test____riscv_vsbc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf2_t test____riscv_vsbc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m1_t test____riscv_vsbc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m2_t test____riscv_vsbc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m4_t test____riscv_vsbc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m8_t test____riscv_vsbc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32mf2_t test____riscv_vsbc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m1_t test____riscv_vsbc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m2_t test____riscv_vsbc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m4_t test____riscv_vsbc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m8_t test____riscv_vsbc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m1_t test____riscv_vsbc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m2_t test____riscv_vsbc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m4_t test____riscv_vsbc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m8_t test____riscv_vsbc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf8_t test____riscv_vsbc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf4_t test____riscv_vsbc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf2_t test____riscv_vsbc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m1_t test____riscv_vsbc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m2_t test____riscv_vsbc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m4_t test____riscv_vsbc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m8_t test____riscv_vsbc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf4_t test____riscv_vsbc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf2_t test____riscv_vsbc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m1_t test____riscv_vsbc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m2_t test____riscv_vsbc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m4_t test____riscv_vsbc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m8_t test____riscv_vsbc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32mf2_t test____riscv_vsbc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m1_t test____riscv_vsbc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m2_t test____riscv_vsbc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m4_t test____riscv_vsbc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m8_t test____riscv_vsbc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m1_t test____riscv_vsbc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m2_t test____riscv_vsbc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m4_t test____riscv_vsbc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m8_t test____riscv_vsbc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C new file mode 100644 index 00000000000..4e0ed444e8d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vsbc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf4_t test____riscv_vsbc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf2_t test____riscv_vsbc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m1_t test____riscv_vsbc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m2_t test____riscv_vsbc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m4_t test____riscv_vsbc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m8_t test____riscv_vsbc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf4_t test____riscv_vsbc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf2_t test____riscv_vsbc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m1_t test____riscv_vsbc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m2_t test____riscv_vsbc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m4_t test____riscv_vsbc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m8_t test____riscv_vsbc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32mf2_t test____riscv_vsbc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m1_t test____riscv_vsbc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m2_t test____riscv_vsbc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m4_t test____riscv_vsbc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m8_t test____riscv_vsbc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m1_t test____riscv_vsbc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m2_t test____riscv_vsbc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m4_t test____riscv_vsbc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m8_t test____riscv_vsbc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf8_t test____riscv_vsbc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf4_t test____riscv_vsbc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf2_t test____riscv_vsbc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m1_t test____riscv_vsbc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m2_t test____riscv_vsbc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m4_t test____riscv_vsbc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m8_t test____riscv_vsbc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf4_t test____riscv_vsbc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf2_t test____riscv_vsbc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m1_t test____riscv_vsbc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m2_t test____riscv_vsbc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m4_t test____riscv_vsbc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m8_t test____riscv_vsbc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32mf2_t test____riscv_vsbc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m1_t test____riscv_vsbc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m2_t test____riscv_vsbc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m4_t test____riscv_vsbc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m8_t test____riscv_vsbc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m1_t test____riscv_vsbc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m2_t test____riscv_vsbc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m4_t test____riscv_vsbc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m8_t test____riscv_vsbc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C new file mode 100644 index 00000000000..c5750c759a1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vsbc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf4_t test____riscv_vsbc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf2_t test____riscv_vsbc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m1_t test____riscv_vsbc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m2_t test____riscv_vsbc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m4_t test____riscv_vsbc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m8_t test____riscv_vsbc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf4_t test____riscv_vsbc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf2_t test____riscv_vsbc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m1_t test____riscv_vsbc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m2_t test____riscv_vsbc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m4_t test____riscv_vsbc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m8_t test____riscv_vsbc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32mf2_t test____riscv_vsbc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m1_t test____riscv_vsbc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m2_t test____riscv_vsbc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m4_t test____riscv_vsbc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m8_t test____riscv_vsbc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m1_t test____riscv_vsbc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m2_t test____riscv_vsbc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m4_t test____riscv_vsbc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m8_t test____riscv_vsbc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf8_t test____riscv_vsbc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf4_t test____riscv_vsbc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf2_t test____riscv_vsbc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m1_t test____riscv_vsbc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m2_t test____riscv_vsbc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m4_t test____riscv_vsbc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m8_t test____riscv_vsbc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf4_t test____riscv_vsbc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf2_t test____riscv_vsbc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m1_t test____riscv_vsbc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m2_t test____riscv_vsbc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m4_t test____riscv_vsbc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m8_t test____riscv_vsbc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32mf2_t test____riscv_vsbc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m1_t test____riscv_vsbc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m2_t test____riscv_vsbc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m4_t test____riscv_vsbc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m8_t test____riscv_vsbc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m1_t test____riscv_vsbc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m2_t test____riscv_vsbc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m4_t test____riscv_vsbc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m8_t test____riscv_vsbc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsbc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C new file mode 100644 index 00000000000..b7592162f94 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vsbc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf4_t test____riscv_vsbc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8mf2_t test____riscv_vsbc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m1_t test____riscv_vsbc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m2_t test____riscv_vsbc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m4_t test____riscv_vsbc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint8m8_t test____riscv_vsbc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf4_t test____riscv_vsbc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16mf2_t test____riscv_vsbc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m1_t test____riscv_vsbc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m2_t test____riscv_vsbc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m4_t test____riscv_vsbc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint16m8_t test____riscv_vsbc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32mf2_t test____riscv_vsbc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m1_t test____riscv_vsbc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m2_t test____riscv_vsbc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m4_t test____riscv_vsbc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint32m8_t test____riscv_vsbc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m1_t test____riscv_vsbc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m2_t test____riscv_vsbc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m4_t test____riscv_vsbc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vint64m8_t test____riscv_vsbc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf8_t test____riscv_vsbc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf4_t test____riscv_vsbc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8mf2_t test____riscv_vsbc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m1_t test____riscv_vsbc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m2_t test____riscv_vsbc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m4_t test____riscv_vsbc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint8m8_t test____riscv_vsbc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf4_t test____riscv_vsbc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16mf2_t test____riscv_vsbc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m1_t test____riscv_vsbc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m2_t test____riscv_vsbc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m4_t test____riscv_vsbc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint16m8_t test____riscv_vsbc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32mf2_t test____riscv_vsbc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m1_t test____riscv_vsbc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m2_t test____riscv_vsbc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m4_t test____riscv_vsbc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint32m8_t test____riscv_vsbc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m1_t test____riscv_vsbc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m2_t test____riscv_vsbc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m4_t test____riscv_vsbc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + +vuint64m8_t test____riscv_vsbc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C new file mode 100644 index 00000000000..29b2d474180 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vsbc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf4_t test____riscv_vsbc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8mf2_t test____riscv_vsbc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m1_t test____riscv_vsbc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m2_t test____riscv_vsbc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m4_t test____riscv_vsbc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint8m8_t test____riscv_vsbc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf4_t test____riscv_vsbc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16mf2_t test____riscv_vsbc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m1_t test____riscv_vsbc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m2_t test____riscv_vsbc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m4_t test____riscv_vsbc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint16m8_t test____riscv_vsbc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32mf2_t test____riscv_vsbc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m1_t test____riscv_vsbc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m2_t test____riscv_vsbc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m4_t test____riscv_vsbc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint32m8_t test____riscv_vsbc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m1_t test____riscv_vsbc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m2_t test____riscv_vsbc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m4_t test____riscv_vsbc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vint64m8_t test____riscv_vsbc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf8_t test____riscv_vsbc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf4_t test____riscv_vsbc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8mf2_t test____riscv_vsbc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m1_t test____riscv_vsbc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m2_t test____riscv_vsbc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m4_t test____riscv_vsbc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint8m8_t test____riscv_vsbc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf4_t test____riscv_vsbc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16mf2_t test____riscv_vsbc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m1_t test____riscv_vsbc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m2_t test____riscv_vsbc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m4_t test____riscv_vsbc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint16m8_t test____riscv_vsbc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32mf2_t test____riscv_vsbc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m1_t test____riscv_vsbc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m2_t test____riscv_vsbc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m4_t test____riscv_vsbc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint32m8_t test____riscv_vsbc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m1_t test____riscv_vsbc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m2_t test____riscv_vsbc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m4_t test____riscv_vsbc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + +vuint64m8_t test____riscv_vsbc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C new file mode 100644 index 00000000000..c52631f6ad7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vsbc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf4_t test____riscv_vsbc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8mf2_t test____riscv_vsbc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m1_t test____riscv_vsbc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m2_t test____riscv_vsbc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m4_t test____riscv_vsbc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint8m8_t test____riscv_vsbc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf4_t test____riscv_vsbc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16mf2_t test____riscv_vsbc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m1_t test____riscv_vsbc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m2_t test____riscv_vsbc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m4_t test____riscv_vsbc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint16m8_t test____riscv_vsbc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32mf2_t test____riscv_vsbc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m1_t test____riscv_vsbc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m2_t test____riscv_vsbc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m4_t test____riscv_vsbc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint32m8_t test____riscv_vsbc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m1_t test____riscv_vsbc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m2_t test____riscv_vsbc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m4_t test____riscv_vsbc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vint64m8_t test____riscv_vsbc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf8_t test____riscv_vsbc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf4_t test____riscv_vsbc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8mf2_t test____riscv_vsbc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m1_t test____riscv_vsbc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m2_t test____riscv_vsbc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m4_t test____riscv_vsbc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint8m8_t test____riscv_vsbc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf4_t test____riscv_vsbc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16mf2_t test____riscv_vsbc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m1_t test____riscv_vsbc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m2_t test____riscv_vsbc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m4_t test____riscv_vsbc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint16m8_t test____riscv_vsbc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32mf2_t test____riscv_vsbc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m1_t test____riscv_vsbc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m2_t test____riscv_vsbc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m4_t test____riscv_vsbc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint32m8_t test____riscv_vsbc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m1_t test____riscv_vsbc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m2_t test____riscv_vsbc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m4_t test____riscv_vsbc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + +vuint64m8_t test____riscv_vsbc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t borrowin,size_t vl) +{ + return __riscv_vsbc_tu(maskedoff,op1,op2,borrowin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsbc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */