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Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwaddu.w c++ API TESTS Date: Tue, 7 Feb 2023 14:50:45 +0800 Message-Id: <20230207065045.49209-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757154065884073351?= X-GMAIL-MSGID: =?utf-8?q?1757154065884073351?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwaddu_wv-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwaddu_wx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwaddu_wv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwaddu_wx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwaddu_wx-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwaddu_wx_tumu-3.C | 111 +++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-1.C new file mode 100644 index 00000000000..770fd4caf0f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vwaddu_wv(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-2.C new file mode 100644 index 00000000000..1aa38c89d4f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vwaddu_wv(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-3.C new file mode 100644 index 00000000000..37f978b3502 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vwaddu_wv(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-1.C new file mode 100644 index 00000000000..8211bbf5f13 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-2.C new file mode 100644 index 00000000000..e89cca00609 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-3.C new file mode 100644 index 00000000000..e4d0613dd52 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-1.C new file mode 100644 index 00000000000..c9431c7a604 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-2.C new file mode 100644 index 00000000000..17af5c3744e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-3.C new file mode 100644 index 00000000000..5ef919e4937 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-1.C new file mode 100644 index 00000000000..bc53576ff21 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-2.C new file mode 100644 index 00000000000..d6b0077b96c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-3.C new file mode 100644 index 00000000000..e469cf881dd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-1.C new file mode 100644 index 00000000000..46a83503413 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-2.C new file mode 100644 index 00000000000..0281197af07 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-3.C new file mode 100644 index 00000000000..1518e52aba6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-1.C new file mode 100644 index 00000000000..5744100cc58 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,vl); +} + + +vuint16mf4_t test___riscv_vwaddu_wx(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-2.C new file mode 100644 index 00000000000..5cf2fd8f009 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,31); +} + + +vuint16mf4_t test___riscv_vwaddu_wx(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-3.C new file mode 100644 index 00000000000..1a45b723d11 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(op1,0xAA,32); +} + + +vuint16mf4_t test___riscv_vwaddu_wx(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx(mask,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-1.C new file mode 100644 index 00000000000..f43e3380f09 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-2.C new file mode 100644 index 00000000000..cecdd5141ca --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-3.C new file mode 100644 index 00000000000..e1586255a34 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_mu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-1.C new file mode 100644 index 00000000000..c4fd8f7dc47 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-2.C new file mode 100644 index 00000000000..e5a412e95b9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-3.C new file mode 100644 index 00000000000..be217e5e13c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tu(merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-1.C new file mode 100644 index 00000000000..ceb6ee676dd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-2.C new file mode 100644 index 00000000000..c6fc1440b79 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-3.C new file mode 100644 index 00000000000..8635633e03b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tum(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-1.C new file mode 100644 index 00000000000..2cdc83e72ae --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-2.C new file mode 100644 index 00000000000..91badbe2d7c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-3.C new file mode 100644 index 00000000000..b370ca805db --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_tumu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */