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[2620:137:e000::1:20]) by mx.google.com with ESMTP id q11-20020a17090a304b00b00229b4d71719si12942128pjl.98.2023.02.06.20.45.52; Mon, 06 Feb 2023 20:46:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229731AbjBGEoO (ORCPT + 99 others); Mon, 6 Feb 2023 23:44:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229574AbjBGEoK (ORCPT ); Mon, 6 Feb 2023 23:44:10 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F549274A1; Mon, 6 Feb 2023 20:44:07 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 233CB1A11FA; Tue, 7 Feb 2023 05:44:06 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B5B361A0B82; Tue, 7 Feb 2023 05:44:05 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id D0891180327D; Tue, 7 Feb 2023 12:44:03 +0800 (+08) From: Richard Zhu To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, l.stach@pengutronix.de, shawnguo@kernel.org, lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v10 1/4] dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema Date: Tue, 7 Feb 2023 12:18:25 +0800 Message-Id: <1675743508-24702-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1675743508-24702-1-git-send-email-hongxing.zhu@nxp.com> References: <1675743508-24702-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757146162396290306?= X-GMAIL-MSGID: =?utf-8?q?1757146162396290306?= Restruct i.MX PCIe schema, derive the common properties, thus they can be shared by both the RC and Endpoint schema. Update the description of fsl,imx6q-pcie.yaml, and move the EP mode compatible to fsl,imx6q-pcie-ep.yaml. Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER accordingly. Signed-off-by: Richard Zhu Reviewed-by: Rob Herring --- .../bindings/pci/fsl,imx6q-pcie-common.yaml | 279 ++++++++++++++++++ .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 85 ++++++ .../bindings/pci/fsl,imx6q-pcie.yaml | 240 +-------------- MAINTAINERS | 2 + 4 files changed, 372 insertions(+), 234 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml new file mode 100644 index 000000000000..9bff8ecb653c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -0,0 +1,279 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 PCIe RC/EP controller + +maintainers: + - Lucas Stach + - Richard Zhu + +description: + Generic Freescale i.MX PCIe Root Port and Endpoint controller + properties. + +properties: + clocks: + minItems: 3 + items: + - description: PCIe bridge clock. + - description: PCIe bus clock. + - description: PCIe PHY clock. + - description: Additional required clock entry for imx6sx-pcie, + imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep. + + clock-names: + minItems: 3 + items: + - const: pcie + - const: pcie_bus + - enum: [ pcie_phy, pcie_aux ] + - enum: [ pcie_inbound_axi, pcie_aux ] + + num-lanes: + const: 1 + + fsl,imx7d-pcie-phy: + $ref: /schemas/types.yaml#/definitions/phandle + description: A phandle to an fsl,imx7d-pcie-phy node. Additional + required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie, + and imx8mq-pcie-ep. + + power-domains: + minItems: 1 + items: + - description: The phandle pointing to the DISPLAY domain for + imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for + imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep. + - description: The phandle pointing to the PCIE_PHY power domains + for imx6sx-pcie and imx6sx-pcie-ep. + + power-domain-names: + minItems: 1 + items: + - const: pcie + - const: pcie_phy + + resets: + minItems: 2 + maxItems: 3 + description: Phandles to PCIe-related reset lines exposed by SRC + IP block. Additional required by imx7d-pcie, imx7d-pcie-ep, + imx8mq-pcie, and imx8mq-pcie-ep. + + reset-names: + minItems: 2 + maxItems: 3 + + fsl,tx-deemph-gen1: + description: Gen1 De-emphasis value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + fsl,tx-deemph-gen2-3p5db: + description: Gen2 (3.5db) De-emphasis value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + fsl,tx-deemph-gen2-6db: + description: Gen2 (6db) De-emphasis value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 20 + + fsl,tx-swing-full: + description: Gen2 TX SWING FULL value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 127 + + fsl,tx-swing-low: + description: TX launch amplitude swing_low value (optional required). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 127 + + fsl,max-link-speed: + description: Specify PCI Gen for link capability (optional required). + Note that the IMX6 LVDS clock outputs do not meet gen2 jitter + requirements and thus for gen2 capability a gen2 compliant clock + generator should be used and configured. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + default: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + vpcie-supply: + description: Should specify the regulator in charge of PCIe port power. + The regulator will be enabled when initializing the PCIe host and + disabled either as part of the init process or when shutting down + the host (optional required). + + vph-supply: + description: Should specify the regulator in charge of VPH one of + the three PCIe PHY powers. This regulator can be supplied by both + 1.8v and 3.3v voltage supplies (optional required). + +required: + - clocks + - clock-names + - num-lanes + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-pcie + - fsl,imx6sx-pcie-ep + then: + properties: + clock-names: + items: + - {} + - {} + - const: pcie_phy + - const: pcie_inbound_axi + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mq-pcie + - fsl,imx8mq-pcie-ep + then: + properties: + clock-names: + items: + - {} + - {} + - const: pcie_phy + - const: pcie_aux + - if: + properties: + compatible: + not: + contains: + enum: + - fsl,imx6sx-pcie + - fsl,imx8mq-pcie + - fsl,imx6sx-pcie-ep + - fsl,imx8mq-pcie-ep + then: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + - fsl,imx7d-pcie-ep + then: + properties: + clock-names: + maxItems: 3 + contains: + const: pcie_phy + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + - fsl,imx8mm-pcie-ep + - fsl,imx8mp-pcie-ep + then: + properties: + clock-names: + maxItems: 3 + contains: + const: pcie_aux + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + then: + properties: + power-domains: false + power-domain-names: false + + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-pcie + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + - fsl,imx6sx-pcie-ep + - fsl,imx6q-pcie-ep + - fsl,imx6qp-pcie-ep + then: + properties: + power-domains: + maxItems: 1 + power-domain-names: false + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mq-pcie + - fsl,imx6q-pcie-ep + - fsl,imx6sx-pcie-ep + - fsl,imx6qp-pcie-ep + - fsl,imx7d-pcie-ep + - fsl,imx8mq-pcie-ep + then: + properties: + resets: + minItems: 3 + reset-names: + items: + - const: pciephy + - const: apps + - const: turnoff + else: + properties: + resets: + maxItems: 2 + reset-names: + items: + - const: apps + - const: turnoff + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml new file mode 100644 index 000000000000..f4a328ec1daa --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 PCIe Endpoint controller + +maintainers: + - Lucas Stach + - Richard Zhu + +description: |+ + This PCIe controller is based on the Synopsys DesignWare PCIe IP and + thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. + The controller instances are dual mode where in they can work either in + Root Port mode or Endpoint mode but one at a time. + +properties: + compatible: + enum: + - fsl,imx8mm-pcie-ep + - fsl,imx8mq-pcie-ep + - fsl,imx8mp-pcie-ep + + reg: + minItems: 2 + + reg-names: + items: + - const: dbi + - const: addr_space + + interrupts: + items: + - description: builtin eDMA interrupter. + + interrupt-names: + items: + - const: dma + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + pcie_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; + reg-names = "dbi", "addr_space"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + }; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index f13f87fddb3d..2443641754d3 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -13,6 +13,11 @@ maintainers: description: |+ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. + The controller instances are dual mode where in they can work either in + Root Port mode or Endpoint mode but one at a time. + + See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree + bindings. properties: compatible: @@ -24,9 +29,6 @@ properties: - fsl,imx8mq-pcie - fsl,imx8mm-pcie - fsl,imx8mp-pcie - - fsl,imx8mm-pcie-ep - - fsl,imx8mq-pcie-ep - - fsl,imx8mp-pcie-ep reg: items: @@ -46,96 +48,6 @@ properties: items: - const: msi - clocks: - minItems: 3 - items: - - description: PCIe bridge clock. - - description: PCIe bus clock. - - description: PCIe PHY clock. - - description: Additional required clock entry for imx6sx-pcie, - imx8mq-pcie. - - clock-names: - minItems: 3 - items: - - const: pcie - - const: pcie_bus - - enum: [ pcie_phy, pcie_aux ] - - enum: [ pcie_inbound_axi, pcie_aux ] - - num-lanes: - const: 1 - - fsl,imx7d-pcie-phy: - $ref: /schemas/types.yaml#/definitions/phandle - description: A phandle to an fsl,imx7d-pcie-phy node. Additional - required properties for imx7d-pcie and imx8mq-pcie. - - power-domains: - minItems: 1 - items: - - description: The phandle pointing to the DISPLAY domain for - imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and - imx8mq-pcie. - - description: The phandle pointing to the PCIE_PHY power domains - for imx6sx-pcie. - - power-domain-names: - minItems: 1 - items: - - const: pcie - - const: pcie_phy - - resets: - minItems: 2 - maxItems: 3 - description: Phandles to PCIe-related reset lines exposed by SRC - IP block. Additional required by imx7d-pcie and imx8mq-pcie. - - reset-names: - minItems: 2 - maxItems: 3 - - fsl,tx-deemph-gen1: - description: Gen1 De-emphasis value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 0 - - fsl,tx-deemph-gen2-3p5db: - description: Gen2 (3.5db) De-emphasis value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 0 - - fsl,tx-deemph-gen2-6db: - description: Gen2 (6db) De-emphasis value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 20 - - fsl,tx-swing-full: - description: Gen2 TX SWING FULL value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 127 - - fsl,tx-swing-low: - description: TX launch amplitude swing_low value (optional required). - $ref: /schemas/types.yaml#/definitions/uint32 - default: 127 - - fsl,max-link-speed: - description: Specify PCI Gen for link capability (optional required). - Note that the IMX6 LVDS clock outputs do not meet gen2 jitter - requirements and thus for gen2 capability a gen2 compliant clock - generator should be used and configured. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 3, 4] - default: 1 - - phys: - maxItems: 1 - - phy-names: - const: pcie-phy - reset-gpio: description: Should specify the GPIO for controlling the PCI bus device reset signal. It's not polarity aware and defaults to active-low reset @@ -147,17 +59,6 @@ properties: L=operation state) (optional required). type: boolean - vpcie-supply: - description: Should specify the regulator in charge of PCIe port power. - The regulator will be enabled when initializing the PCIe host and - disabled either as part of the init process or when shutting down - the host (optional required). - - vph-supply: - description: Should specify the regulator in charge of VPH one of - the three PCIe PHY powers. This regulator can be supplied by both - 1.8v and 3.3v voltage supplies (optional required). - required: - compatible - reg @@ -167,144 +68,15 @@ required: - device_type - bus-range - ranges - - num-lanes - interrupts - interrupt-names - "#interrupt-cells" - interrupt-map-mask - interrupt-map - - clocks - - clock-names allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# - - if: - properties: - compatible: - contains: - const: fsl,imx6sx-pcie - then: - properties: - clock-names: - items: - - {} - - {} - - const: pcie_phy - - const: pcie_inbound_axi - power-domains: - minItems: 2 - power-domain-names: - minItems: 2 - - if: - properties: - compatible: - contains: - const: fsl,imx8mq-pcie - then: - properties: - clock-names: - items: - - {} - - {} - - const: pcie_phy - - const: pcie_aux - - if: - properties: - compatible: - not: - contains: - enum: - - fsl,imx6sx-pcie - - fsl,imx8mq-pcie - then: - properties: - clocks: - maxItems: 3 - clock-names: - maxItems: 3 - - - if: - properties: - compatible: - contains: - enum: - - fsl,imx6q-pcie - - fsl,imx6qp-pcie - - fsl,imx7d-pcie - then: - properties: - clock-names: - maxItems: 3 - contains: - const: pcie_phy - - - if: - properties: - compatible: - contains: - enum: - - fsl,imx8mm-pcie - - fsl,imx8mp-pcie - then: - properties: - clock-names: - maxItems: 3 - contains: - const: pcie_aux - - if: - properties: - compatible: - contains: - enum: - - fsl,imx6q-pcie - - fsl,imx6qp-pcie - then: - properties: - power-domains: false - power-domain-names: false - - - if: - not: - properties: - compatible: - contains: - enum: - - fsl,imx6sx-pcie - - fsl,imx6q-pcie - - fsl,imx6qp-pcie - then: - properties: - power-domains: - maxItems: 1 - power-domain-names: false - - - if: - properties: - compatible: - contains: - enum: - - fsl,imx6q-pcie - - fsl,imx6sx-pcie - - fsl,imx6qp-pcie - - fsl,imx7d-pcie - - fsl,imx8mq-pcie - then: - properties: - resets: - minItems: 3 - reset-names: - items: - - const: pciephy - - const: apps - - const: turnoff - else: - properties: - resets: - maxItems: 2 - reset-names: - items: - - const: apps - - const: turnoff + - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# unevaluatedProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index 5dce1c45f4d1..5ee8de98d4a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15997,6 +15997,8 @@ M: Lucas Stach L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml F: drivers/pci/controller/dwc/*imx6* From patchwork Tue Feb 7 04:18:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 53653 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2647136wrn; Mon, 6 Feb 2023 20:45:53 -0800 (PST) X-Google-Smtp-Source: AK7set+JXwdVMDB9tQtoCKB11UrsyGRmGYO/hh6gZWl9FW/9x7PE4qXFfhYmQkVcP5O8Az2bqi1q X-Received: by 2002:a05:6a20:4403:b0:b8:9f05:5216 with SMTP id ce3-20020a056a20440300b000b89f055216mr2664659pzb.57.1675745152854; Mon, 06 Feb 2023 20:45:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675745152; cv=none; d=google.com; s=arc-20160816; b=Ztf1r0JwVn0k/oofsEW65XKCG4GRQx07w2kuoiWYeLXFkmQnSFrjbohthH/mXneIUu y5sq8aXRyqsRUi133YSb0M1C0j2eitwNfx/HurjahisVYZBJTXoSwLyD7/Z8OuhNFkQ4 Q71R3UDBFfRYvhePnwKAOP2XBrxFF/NZvygChNdf7Rnqn3rr8b4i9gXa0PGU/AO40qVW AIJfxX1BATvNuwSXTYVuzBXXN5NYy+IP8aJpv2wqp3Z+p/UTlB3Ms9MTPuxyjUahnXuu mcHRqNG96xtfXSZdF1bn5lr9VsUtfDyjPlkekoawL8gHNrSWMYZfXOui67QCPLHYeZL2 Kofg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=aWUR9tiIWLhM0hfumcvn2GOAHCKK+5Agt3v8H0EHu/c=; b=tj0p6VbS1fCmpfkJeGghyvYTlL/JTb6JTcqg+RVl22Bgf6+aykniUp7jXQ9gtw5fap kxECslFjzB3Na5fHEwtZHP+pV0/5qpGzqGLMMmO7JlwvxJg0RCSid5egvpcPdapoA70M yYDFqw4Mpge63rEmHikQ/DlgJNSM2I/kYCM5JmiCjV34e0KvnEPYzNVxARGUBcllOZaG k8hO/6snuUFoSAlkP/owsy7+fFCwUZGqON/v4EKASpNZwdDT8dPTwDUUKEbpdAe7JmCS VC6wb+WDEt+vA8O7mN9H0izKt59M5VYAbw8352gkngaChniobnDM4CMhO9voBgQfjfnF nhoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g25-20020a639f19000000b004d21c99e5c7si13133620pge.28.2023.02.06.20.45.40; Mon, 06 Feb 2023 20:45:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbjBGEoR (ORCPT + 99 others); Mon, 6 Feb 2023 23:44:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229447AbjBGEoK (ORCPT ); Mon, 6 Feb 2023 23:44:10 -0500 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF50426CF5; Mon, 6 Feb 2023 20:44:08 -0800 (PST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6B2522012BA; Tue, 7 Feb 2023 05:44:07 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3465E200B72; Tue, 7 Feb 2023 05:44:07 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 46DD4183ABF3; Tue, 7 Feb 2023 12:44:05 +0800 (+08) From: Richard Zhu To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, l.stach@pengutronix.de, shawnguo@kernel.org, lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v10 2/4] arm64: dts: Add i.MX8MM PCIe EP support Date: Tue, 7 Feb 2023 12:18:26 +0800 Message-Id: <1675743508-24702-3-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1675743508-24702-1-git-send-email-hongxing.zhu@nxp.com> References: <1675743508-24702-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757146149377085698?= X-GMAIL-MSGID: =?utf-8?q?1757146149377085698?= Add i.MX8MM PCIe EP support. Signed-off-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 31f4548f85cf..a9552867e547 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1315,6 +1315,30 @@ pcie0: pcie@33800000 { status = "disabled"; }; + pcie0_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x400000>, + <0x18000000 0x8000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gpu_3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; From patchwork Tue Feb 7 04:18:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 53652 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2647051wrn; Mon, 6 Feb 2023 20:45:37 -0800 (PST) X-Google-Smtp-Source: AK7set8cjsXPdUMxwKIgP+74v9Wjc7LcIAzIAl4gy6AyweZFrhvq0LquvfcD4qNAhJ30KnJW4kVK X-Received: by 2002:a05:6a20:e688:b0:b6:204c:d606 with SMTP id mz8-20020a056a20e68800b000b6204cd606mr1672243pzb.62.1675745136994; Mon, 06 Feb 2023 20:45:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675745136; cv=none; d=google.com; s=arc-20160816; b=DI4PWEGoil20KrUQFuD4S80A5dd18Vg50hp3W5SE0YGiLKr5Mztv93kbPBzUdA1k9z qiYbEdIm4+xuxG8jjSMb/87rPY7u0EJ/84qpzCOTRWiDkO3kQbL85Kcs+wf9tJDuJNUu y9apymAJLGUjTdSuhVRVkVNOG0wFswMNClo+RVIgoB2fyVSywt2xGirMeu2Yd8GYRZpz DhH1E7Sd5tkCMAhm04QqyC1YBmingjl0hH+Q4M/YhmnLRTpKpr0V5otq35NUyG4u7/h7 idP2IdRmsBm96dosPevvvCsT7zUxEi4h6yhG8RSwCd5Nb12fRfJbAeUmVhZrOrIvajhd I5qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=5UuBja/D+wBuzNHmiPUEhYYlvToz6fWqOfRU7TKgQbM=; b=r2dUJ7FWam0Q0qZwQ4weYupXuUKuVIOQM7xJeNErpwG6OuzCuY309Zw3u5cfN5IGlH cNYs0IitTXfv38Nym4BFZeeH+acJ++ybzQLxZ1J/+1COh4wZu0uNZ+mOSRROMFGPBhWK I91uIjw0JSTnvASOKzwXfw8NoAsVksWTAf4ndGcqB5YLkgLesp/EsFNxWK+0sn9U1beJ 4dn5wOqmN6m5WtJIwEAPN9AfFuGb+JTC7vIKKvpvMcK0KbAepxBbHmvFotJIZNORP7QK rtIUsy7jrcGmTPjW/sFGim8XIF17gdzzyQeWxQi6sjP8A6odH+LyQvts9WvkCTDOUqr0 QAnw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 202-20020a6300d3000000b004f2e3b7425csi14287123pga.857.2023.02.06.20.45.24; Mon, 06 Feb 2023 20:45:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229874AbjBGEoU (ORCPT + 99 others); Mon, 6 Feb 2023 23:44:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229625AbjBGEoL (ORCPT ); Mon, 6 Feb 2023 23:44:11 -0500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FC4027D59; Mon, 6 Feb 2023 20:44:10 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id D4F951A1200; Tue, 7 Feb 2023 05:44:08 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 9E69F1A0B82; Tue, 7 Feb 2023 05:44:08 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id B97D0183ABF0; Tue, 7 Feb 2023 12:44:06 +0800 (+08) From: Richard Zhu To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, l.stach@pengutronix.de, shawnguo@kernel.org, lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v10 3/4] arm64: dts: Add i.MX8MQ PCIe EP support Date: Tue, 7 Feb 2023 12:18:27 +0800 Message-Id: <1675743508-24702-4-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1675743508-24702-1-git-send-email-hongxing.zhu@nxp.com> References: <1675743508-24702-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757146132493920075?= X-GMAIL-MSGID: =?utf-8?q?1757146132493920075?= Add i.MX8MQ PCIe EP support. Signed-off-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 98fbba4c99a9..9f950a6ac6c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1605,6 +1605,38 @@ pcie1: pcie@33c00000 { status = "disabled"; }; + pcie1_ep: pcie-ep@33c00000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33c00000 0x000400000>, + <0x20000000 0x08000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ From patchwork Tue Feb 7 04:18:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 53655 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2647238wrn; Mon, 6 Feb 2023 20:46:11 -0800 (PST) X-Google-Smtp-Source: AK7set/Uk4bndGlBDNjew4/6XhGBA16/sXLQ0lRmGE3tNi2GiVpryeEbX7MRutp78K7v72iGxTwC X-Received: by 2002:a17:902:e1d4:b0:199:109e:832 with SMTP id t20-20020a170902e1d400b00199109e0832mr1193992pla.37.1675745171216; Mon, 06 Feb 2023 20:46:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675745171; cv=none; d=google.com; s=arc-20160816; b=0qhJQxt94mYZLzTNxCWQoOwyTSxbCPKu0KYb4ynX4MIMPEpclA4TtNGAN6WknSkdwU rLMy9Wr/ndBeQWXyOBlIm/FgACnZuPRY+N7Wz1yiYyvd7hYRyEHE2GJWxuNLQdH7e6Wo rcN6poU8guM8GiPZP0K8e3t3uP9un6S+SOiFujYocFjyEzcVEDsNLihDnRwhxBlMRgAP UD9f5p6vw+ZrMuKcgQrDq7KPuiKILHr3yuaxGYQpapQimrJyr8zBYP+AA9b39l1WVfOc 1/TP4nw3JpazukeBqc8qzVmoYEu2UXOZRpLql+d8A+BBBLBhVXn9sxx0bzxhz08XNtXz ko6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=yZTA4s1giQ6Rqu7IflMSN4GslCqiMZ3iZc6kXGG2AYc=; b=Dym6Ya2bMW/h08hYLb0JIn3BqzjF98ELImjSgvmESJiTeFw1xb+/UMxwaVkv/DOCvs qNTS43CpxdzmwaBunaiXeWM+3T46Euz2xT41E/eosI6kY0ym89lh4wBvIZaLcBfwi2M4 CDEGPEWckrx+DeVG+jUbmcCOC5VpXAhzp3ohneVn8oJpH2djPZJ+6Iw3kgteMSpzzolG QdimSpGqmEIhCnMoMryh8iFkMZu2M6GYdVPEurcynJl+oH7+V5FgWdKOsb2jxLpY4Wp7 jqGfYdFG1vA3en+YCJGUzSUQAH/6U8ycupCex5HKDxLqTUiMHDzR9keQkWz4onyLX2oV yFiw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l2-20020a170903244200b0019608f60abesi14028827pls.240.2023.02.06.20.45.58; Mon, 06 Feb 2023 20:46:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230020AbjBGEo2 (ORCPT + 99 others); Mon, 6 Feb 2023 23:44:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229686AbjBGEoM (ORCPT ); Mon, 6 Feb 2023 23:44:12 -0500 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D62527D74; Mon, 6 Feb 2023 20:44:11 -0800 (PST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 4AAD82012B8; Tue, 7 Feb 2023 05:44:10 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 13A39200B7C; Tue, 7 Feb 2023 05:44:10 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 2ED6E183ABF9; Tue, 7 Feb 2023 12:44:08 +0800 (+08) From: Richard Zhu To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, l.stach@pengutronix.de, shawnguo@kernel.org, lorenzo.pieralisi@arm.com, peng.fan@nxp.com, marex@denx.de, marcel.ziswiler@toradex.com, tharvey@gateworks.com, frank.li@nxp.com Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Subject: [PATCH v10 4/4] arm64: dts: Add i.MX8MP PCIe EP support Date: Tue, 7 Feb 2023 12:18:28 +0800 Message-Id: <1675743508-24702-5-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1675743508-24702-1-git-send-email-hongxing.zhu@nxp.com> References: <1675743508-24702-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757146168433105439?= X-GMAIL-MSGID: =?utf-8?q?1757146168433105439?= Add i.MX8MP PCIe EP support. Signed-off-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index a19224fe1a6a..2f84b8b0118e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1309,6 +1309,32 @@ pcie: pcie@33800000 { status = "disabled"; }; + pcie_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; + reg-names = "dbi", "addr_space"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>;