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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q33-20020a05640224a100b0044e9c289ae5si8118712eda.155.2022.10.17.01.37.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Oct 2022 01:37:36 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 26ABD3857827 for ; Mon, 17 Oct 2022 08:37:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id 463C83858D3C for ; Mon, 17 Oct 2022 08:36:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 463C83858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp87t1665995805t4ofj4s0 Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 17 Oct 2022 16:36:43 +0800 (CST) X-QQ-SSF: 01400000000000D0K000000A0000000 X-QQ-FEAT: 9E3Ddn8eo0IWxK03d06cPm53CGBqXh3aW83dAnW+UqFhyBV/VPAWDGjTtiuPT ppRnuSUyf3+3sHIflCNxtAzbc8KwfcA2ad8wqR7tmqLdvoxs73+OgGz6imHEB9rxKW0AhQP MXW31cHL42D08Wqk0Kvtqi7YLUMWIvtdXAGcB6SvUmDzfiPJUNS9io0Phwlgkd7sTYvG/pf i7V6z9IBjDQbHRa0MqqtaNcz312mPa58AoAgR803a4krgd13DhU68MdQtk9wZgVPUrEKr2d E6MvQTG1ThWL8ZGKyrkQePNyB3A3sydOwV3pyOC30MTZWeCilsPfm1Xouyz+T4wSEjjdwjs yQrHdJg1FiF3YlB5K/dJcXRnngHMEc9k08QuqKAVEnk3zvMMlMKLHHxPN9bX9LZi4OoZLUH X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. Date: Mon, 17 Oct 2022 16:36:42 +0800 Message-Id: <20221017083642.184867-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746923271067673256?= X-GMAIL-MSGID: =?utf-8?q?1746923271067673256?= From: Ju-Zhe Zhong gcc/ChangeLog: * config.gcc: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o * config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro. (DEF_RVV_FUNCTION): Ditto. (handle_pragma_vector): Add intrinsic framework. * config/riscv/riscv.cc (riscv_print_operand): Add operand print for vsetvl/vsetvlmax. * config/riscv/riscv.md: include vector.md. * config/riscv/t-riscv: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o * config/riscv/riscv-vector-builtins-bases.cc: New file. * config/riscv/riscv-vector-builtins-bases.h: New file. * config/riscv/riscv-vector-builtins-functions.def: New file. * config/riscv/riscv-vector-builtins-shapes.cc: New file. * config/riscv/riscv-vector-builtins-shapes.h: New file. * config/riscv/riscv-vector-builtins-types.def: New file. * config/riscv/vector.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vsetvl-1.c: New test. --- gcc/config.gcc | 2 +- .../riscv/riscv-vector-builtins-bases.cc | 104 +++ .../riscv/riscv-vector-builtins-bases.h | 33 + .../riscv/riscv-vector-builtins-functions.def | 43 + .../riscv/riscv-vector-builtins-shapes.cc | 104 +++ .../riscv/riscv-vector-builtins-shapes.h | 33 + .../riscv/riscv-vector-builtins-types.def | 50 ++ gcc/config/riscv/riscv-vector-builtins.cc | 56 ++ gcc/config/riscv/riscv.cc | 26 + gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/t-riscv | 28 +- gcc/config/riscv/vector.md | 72 ++ .../gcc.target/riscv/rvv/base/vsetvl-1.c | 750 ++++++++++++++++++ 13 files changed, 1300 insertions(+), 2 deletions(-) create mode 100644 gcc/config/riscv/riscv-vector-builtins-bases.cc create mode 100644 gcc/config/riscv/riscv-vector-builtins-bases.h create mode 100644 gcc/config/riscv/riscv-vector-builtins-functions.def create mode 100644 gcc/config/riscv/riscv-vector-builtins-shapes.cc create mode 100644 gcc/config/riscv/riscv-vector-builtins-shapes.h create mode 100644 gcc/config/riscv/riscv-vector-builtins-types.def create mode 100644 gcc/config/riscv/vector.md create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c diff --git a/gcc/config.gcc b/gcc/config.gcc index 486e8790544..3826ae42803 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -516,7 +516,7 @@ pru-*-*) riscv*) cpu_type=riscv extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o" - extra_objs="${extra_objs} riscv-vector-builtins.o" + extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o" d_target_objs="riscv-d.o" extra_headers="riscv_vector.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc new file mode 100644 index 00000000000..8582c0cae4c --- /dev/null +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -0,0 +1,104 @@ +/* function_base implementation for RISC-V 'V' Extension for GNU compiler. + Copyright (C) 2022-2022 Free Software Foundation, Inc. + Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "tree.h" +#include "rtl.h" +#include "tm_p.h" +#include "memmodel.h" +#include "insn-codes.h" +#include "optabs.h" +#include "recog.h" +#include "expr.h" +#include "basic-block.h" +#include "function.h" +#include "fold-const.h" +#include "gimple.h" +#include "gimple-iterator.h" +#include "gimplify.h" +#include "explow.h" +#include "emit-rtl.h" +#include "tree-vector-builder.h" +#include "rtx-vector-builder.h" +#include "riscv-vector-builtins.h" +#include "riscv-vector-builtins-shapes.h" +#include "riscv-vector-builtins-bases.h" + +using namespace riscv_vector; + +namespace riscv_vector { + +/* Implements vsetvl && vsetvlmax. */ +template +class vsetvl : public function_base +{ +public: + unsigned int call_properties (const function_instance &) const + { + return CP_READ_CSR | CP_WRITE_CSR; + } + + rtx expand (function_expander &e) const override + { + if (VLMAX_P) + e.add_input_operand (Pmode, gen_rtx_REG (Pmode, 0)); + else + e.add_input_operand (0); + + tree type = builtin_types[e.type.index].vector; + machine_mode mode = TYPE_MODE (type); + machine_mode inner_mode = GET_MODE_INNER (mode); + /* SEW. */ + e.add_input_operand (Pmode, + gen_int_mode (GET_MODE_BITSIZE (inner_mode), Pmode)); + + /* LMUL. Define the bitmap rule as follows: + | 4 | 3 2 1 0 | + | fractional_p | factor | + */ + bool fractional_p = known_lt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR); + unsigned int factor + = fractional_p ? exact_div (BYTES_PER_RISCV_VECTOR, GET_MODE_SIZE (mode)) + .to_constant () + : exact_div (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR) + .to_constant (); + e.add_input_operand (Pmode, + gen_int_mode ((fractional_p << 4) | factor, Pmode)); + + /* TA. */ + e.add_input_operand (Pmode, gen_int_mode (1, Pmode)); + + /* MU. */ + e.add_input_operand (Pmode, gen_int_mode (0, Pmode)); + return e.generate_insn (code_for_vsetvl (Pmode)); + } +}; + +static CONSTEXPR const vsetvl vsetvl_obj; +static CONSTEXPR const vsetvl vsetvlmax_obj; +namespace bases { +const function_base *const vsetvl = &vsetvl_obj; +const function_base *const vsetvlmax = &vsetvlmax_obj; +} + +} // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h new file mode 100644 index 00000000000..a0ae18eef03 --- /dev/null +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -0,0 +1,33 @@ +/* function_base declaration for RISC-V 'V' Extension for GNU compiler. + Copyright (C) 2022-2022 Free Software Foundation, Inc. + Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef GCC_RISCV_VECTOR_BUILTINS_BASES_H +#define GCC_RISCV_VECTOR_BUILTINS_BASES_H + +namespace riscv_vector { + +namespace bases { +extern const function_base *const vsetvl; +extern const function_base *const vsetvlmax; +} + +} // end namespace riscv_vector + +#endif diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def new file mode 100644 index 00000000000..dc41537865e --- /dev/null +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -0,0 +1,43 @@ +/* Intrinsic define macros for RISC-V 'V' Extension for GNU compiler. + Copyright (C) 2022-2022 Free Software Foundation, Inc. + Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +/* Use "DEF_RVV_FUNCTION" macro to define RVV intrinsic functions. + + - NAME not only describes the base_name of the functions + but also point to the name of the function_base class. + + - SHAPE point to the function_shape class. + + - PREDS describes the predication types that are supported in the + functions. + + - OPS_INFO describes all information of return type and each + argument type. + +*/ +#ifndef DEF_RVV_FUNCTION +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) +#endif + +/* 6. Configuration-Setting Instructions. */ +DEF_RVV_FUNCTION (vsetvl, vsetvl, none_preds, i_none_size_size_ops) +DEF_RVV_FUNCTION (vsetvlmax, vsetvlmax, none_preds, i_none_size_void_ops) + +#undef DEF_RVV_FUNCTION diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc new file mode 100644 index 00000000000..24fc1c02341 --- /dev/null +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -0,0 +1,104 @@ +/* function_shape implementation for RISC-V 'V' Extension for GNU compiler. + Copyright (C) 2022-2022 Free Software Foundation, Inc. + Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "tree.h" +#include "rtl.h" +#include "tm_p.h" +#include "memmodel.h" +#include "insn-codes.h" +#include "optabs.h" +#include "riscv-vector-builtins.h" +#include "riscv-vector-builtins-shapes.h" + +namespace riscv_vector { + +/* Add one function instance for GROUP, using operand suffix at index OI, + mode suffix at index PAIR && bi and predication suffix at index pred_idx. */ +static void +build_one (function_builder &b, const function_group_info &group, + unsigned int pred_idx, unsigned int vec_type_idx) +{ + /* Byte forms of non-tuple vlxusegei take 21 arguments. */ + auto_vec argument_types; + function_instance function_instance (group.base_name, *group.base, + *group.shape, + group.ops_infos.types[vec_type_idx], + group.preds[pred_idx], &group.ops_infos); + tree return_type = group.ops_infos.ret.get_tree_type ( + group.ops_infos.types[vec_type_idx].index); + b.allocate_argument_types (function_instance, argument_types); + b.add_unique_function (function_instance, (*group.shape), return_type, + argument_types); +} + +/* Add a function instance for every operand && predicate && args + combination in GROUP. Take the function base name from GROUP && operand + suffix from operand_suffixes && mode suffix from type_suffixes && predication + suffix from predication_suffixes. Use apply_predication to add in + the predicate. */ +static void +build_all (function_builder &b, const function_group_info &group) +{ + for (unsigned int pred_idx = 0; group.preds[pred_idx] != NUM_PRED_TYPES; + ++pred_idx) + for (unsigned int vec_type_idx = 0; + group.ops_infos.types[vec_type_idx].index != NUM_VECTOR_TYPES; + ++vec_type_idx) + build_one (b, group, pred_idx, vec_type_idx); +} + +/* Declare the function shape NAME, pointing it to an instance + of class _def. */ +#define SHAPE(DEF, VAR) \ + static CONSTEXPR const DEF##_def VAR##_obj; \ + namespace shapes { const function_shape *const VAR = &VAR##_obj; } + +/* Base class for for build. */ +struct build_base : public function_shape +{ + void build (function_builder &b, + const function_group_info &group) const override + { + build_all (b, group); + } +}; + +/* vsetvl_def class. */ +struct vsetvl_def : public build_base +{ + char *get_name (function_builder &b, const function_instance &instance, + bool overloaded_p) const override + { + /* vsetvl* instruction doesn't have C++ overloaded functions. */ + if (overloaded_p) + return nullptr; + b.append_name (instance.base_name); + b.append_name (type_suffixes[instance.type.index].vsetvl); + return b.finish_name (); + } +}; +SHAPE(vsetvl, vsetvl) +SHAPE(vsetvl, vsetvlmax) + +} // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h b/gcc/config/riscv/riscv-vector-builtins-shapes.h new file mode 100644 index 00000000000..f2d876fb133 --- /dev/null +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h @@ -0,0 +1,33 @@ +/* function_shape declaration for RISC-V 'V' Extension for GNU compiler. + Copyright (C) 2022-2022 Free Software Foundation, Inc. + Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef GCC_RISCV_VECTOR_BUILTINS_SHAPES_H +#define GCC_RISCV_VECTOR_BUILTINS_SHAPES_H + +namespace riscv_vector { + +namespace shapes { +extern const function_shape *const vsetvl; +extern const function_shape *const vsetvlmax; +} + +} // end namespace riscv_vector + +#endif diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def new file mode 100644 index 00000000000..f282a5e7654 --- /dev/null +++ b/gcc/config/riscv/riscv-vector-builtins-types.def @@ -0,0 +1,50 @@ +/* Intrinsic type iterators for RISC-V 'V' Extension for GNU compiler. + Copyright (C) 2022-2022 Free Software Foundation, Inc. + Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +/* Use "DEF_ALL_SIGNED_INTEGER" macro include all signed integer which will be + iterated and registered as intrinsic functions. */ +#ifndef DEF_RVV_I_OPS +#define DEF_RVV_I_OPS(TYPE, REQUIRE) +#endif + +DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint8mf4_t, 0) +DEF_RVV_I_OPS (vint8mf2_t, 0) +DEF_RVV_I_OPS (vint8m1_t, 0) +DEF_RVV_I_OPS (vint8m2_t, 0) +DEF_RVV_I_OPS (vint8m4_t, 0) +DEF_RVV_I_OPS (vint8m8_t, 0) +DEF_RVV_I_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint16mf2_t, 0) +DEF_RVV_I_OPS (vint16m1_t, 0) +DEF_RVV_I_OPS (vint16m2_t, 0) +DEF_RVV_I_OPS (vint16m4_t, 0) +DEF_RVV_I_OPS (vint16m8_t, 0) +DEF_RVV_I_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint32m1_t, 0) +DEF_RVV_I_OPS (vint32m2_t, 0) +DEF_RVV_I_OPS (vint32m4_t, 0) +DEF_RVV_I_OPS (vint32m8_t, 0) +DEF_RVV_I_OPS (vint64m1_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint64m2_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint64m4_t, RVV_REQUIRE_ZVE64) +DEF_RVV_I_OPS (vint64m8_t, RVV_REQUIRE_ZVE64) + +#undef DEF_RVV_I_OPS diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 5c20788b3ab..dc410788c99 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -45,6 +45,8 @@ #include "targhooks.h" #include "regs.h" #include "riscv-vector-builtins.h" +#include "riscv-vector-builtins-shapes.h" +#include "riscv-vector-builtins-bases.h" using namespace riscv_vector; @@ -115,6 +117,49 @@ const char *const predication_suffixes[NUM_PRED_TYPES] = { #include "riscv-vector-builtins.def" }; +/* A list of all signed integer will be registered for intrinsic functions. */ +static const rvv_type_info i_ops[] = { +#define DEF_RVV_I_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + +static CONSTEXPR const rvv_arg_type_info rvv_arg_type_info_end + = rvv_arg_type_info (NUM_BASE_TYPES); + +/* A list of args for size_t func (void) function. */ +static CONSTEXPR const rvv_arg_type_info void_args[] + = {rvv_arg_type_info (RVV_BASE_void), rvv_arg_type_info_end}; + +/* A list of args for size_t func (size_t) function. */ +static CONSTEXPR const rvv_arg_type_info size_args[] + = {rvv_arg_type_info (RVV_BASE_size), rvv_arg_type_info_end}; + +/* A list of none preds that will be registered for intrinsic functions. */ +static CONSTEXPR const predication_type_index none_preds[] + = {PRED_TYPE_none, NUM_PRED_TYPES}; + +/* A static operand information for size_t func (void) function registration. */ +static CONSTEXPR const rvv_op_info i_none_size_void_ops + = {i_ops, /* Types */ + OP_TYPE_none, /* Suffix */ + rvv_arg_type_info (RVV_BASE_size), /* Return type */ + void_args /* Args */}; + +/* A static operand information for size_t func (size_t) function registration. + */ +static CONSTEXPR const rvv_op_info i_none_size_size_ops + = {i_ops, /* Types */ + OP_TYPE_none, /* Suffix */ + rvv_arg_type_info (RVV_BASE_size), /* Return type */ + size_args /* Args */}; + +/* A list of all RVV intrinsic functions. */ +static function_group_info function_groups[] = { +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) \ + {#NAME, &bases::NAME, &shapes::SHAPE, PREDS, OPS_INFO}, +#include "riscv-vector-builtins-functions.def" +}; + /* The RVV types, with their built-in "__rvv..._t" name. Allow an index of NUM_VECTOR_TYPES, which always yields a null tree. */ @@ -787,11 +832,22 @@ verify_type_context (location_t loc, type_context_kind context, const_tree type, void handle_pragma_vector () { + if (function_table) + { + error ("duplicate definition of %qs", "riscv_vector.h"); + return; + } rvv_switcher rvv; /* Define the vector and tuple types. */ for (unsigned int type_i = 0; type_i < NUM_VECTOR_TYPES; ++type_i) register_vector_type ((enum vector_type_index) type_i); + + /* Define the functions. */ + function_table = new hash_table (1023); + function_builder builder; + for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i) + builder.register_function_group (function_groups[i]); } /* Return the function decl with RVV function subcode CODE, or error_mark_node diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ad57b995e7b..90a39047dd7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4135,6 +4135,32 @@ riscv_print_operand (FILE *file, rtx op, int letter) switch (letter) { + case 'm': { + if (code == CONST_INT) + { + /* LMUL. Define the bitmap rule as follows: + | 4 | 3 2 1 0 | + | fractional_p | factor | + */ + bool fractional_p = (UINTVAL (op) >> 4) & 0x1; + unsigned int factor = UINTVAL (op) & 0xf; + asm_fprintf (file, "%s%d", fractional_p ? "mf" : "m", factor); + } + else + output_operand_lossage ("invalid vector constant"); + break; + } + case 'p': { + if (code == CONST_INT) + { + /* Tail && Mask policy. */ + bool agnostic_p = UINTVAL (op) & 0x1; + asm_fprintf (file, "%s", agnostic_p ? "a" : "u"); + } + else + output_operand_lossage ("invalid vector constant"); + break; + } case 'h': if (code == HIGH) op = XEXP (op, 0); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 2d1cda2b98f..b3654915fde 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2999,3 +2999,4 @@ (include "pic.md") (include "generic.md") (include "sifive-7.md") +(include "vector.md") diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 15b9e7c01b1..8f67676cad7 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -11,10 +11,36 @@ riscv-vector-builtins.o: $(srcdir)/config/riscv/riscv-vector-builtins.cc \ $(FUNCTION_H) fold-const.h gimplify.h explow.h stor-layout.h $(REGS_H) \ alias.h langhooks.h attribs.h stringpool.h \ $(srcdir)/config/riscv/riscv-vector-builtins.h \ - $(srcdir)/config/riscv/riscv-vector-builtins.def + $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \ + $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \ + $(srcdir)/config/riscv/riscv-vector-builtins.def \ + $(srcdir)/config/riscv/riscv-vector-builtins-types.def \ + $(srcdir)/config/riscv/riscv-vector-builtins-functions.def $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/riscv/riscv-vector-builtins.cc +riscv-vector-builtins-shapes.o: \ + $(srcdir)/config/riscv/riscv-vector-builtins-shapes.cc \ + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \ + $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) \ + $(srcdir)/config/riscv/riscv-vector-builtins.h \ + $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/riscv/riscv-vector-builtins-shapes.cc + +riscv-vector-builtins-bases.o: \ + $(srcdir)/config/riscv/riscv-vector-builtins-bases.cc \ + $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \ + $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \ + $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \ + gimple-iterator.h gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \ + rtx-vector-builder.h \ + $(srcdir)/config/riscv/riscv-vector-builtins.h \ + $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \ + $(srcdir)/config/riscv/riscv-vector-builtins-bases.h + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/riscv/riscv-vector-builtins-bases.cc + riscv-sr.o: $(srcdir)/config/riscv/riscv-sr.cc $(CONFIG_H) \ $(SYSTEM_H) $(TM_H) $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md new file mode 100644 index 00000000000..82ce902c0fb --- /dev/null +++ b/gcc/config/riscv/vector.md @@ -0,0 +1,72 @@ +;; Machine description for RISC-V 'V' Extension for GNU compiler. +;; Copyright (C) 2022-2022 Free Software Foundation, Inc. +;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; This file describes the RISC-V 'V' Extension, Version 1.0. +;; +;; This file include : +;; +;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc) +;; - Auto-vectorization (TBD) +;; - Combine optimization (TBD) + +(define_c_enum "unspec" [ + UNSPEC_VSETVL +]) + +;; ----------------------------------------------------------------- +;; ---- 6. Configuration-Setting Instructions +;; ----------------------------------------------------------------- +;; Includes: +;; - 6.1 vsetvli/vsetivl/vsetvl instructions +;; ----------------------------------------------------------------- + +;; we dont't define vsetvli as unspec_volatile which has side effects. +;; This instruction can be scheduled by the instruction scheduler. +;; This means these instructions will be deleted when +;; there is no instructions using vl or vtype in the following. +;; rd | rs1 | AVL value | Effect on vl +;; - | !x0 | x[rs1] | Normal stripmining +;; !x0 | x0 | ~0 | Set vl to VLMAX +;; operands[0]: VL. +;; operands[1]: AVL. +;; operands[2]: SEW +;; operands[3]: LMUL +;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic) +;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic) +(define_insn "@vsetvl" + [(set (match_operand:P 0 "register_operand" "=r,r") + (unspec:P [(match_operand:P 1 "csr_operand" "r,K") + (match_operand 2 "const_int_operand" "i,i") + (match_operand 3 "const_int_operand" "i,i") + (match_operand 4 "const_int_operand" "i,i") + (match_operand 5 "const_int_operand" "i,i")] UNSPEC_VSETVL)) + (set (reg:SI VL_REGNUM) + (unspec:SI [(match_dup 1) + (match_dup 2) + (match_dup 3)] UNSPEC_VSETVL)) + (set (reg:SI VTYPE_REGNUM) + (unspec:SI [(match_dup 2) + (match_dup 3) + (match_dup 4) + (match_dup 5)] UNSPEC_VSETVL))] + "TARGET_VECTOR" + "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5" + [(set_attr "type" "vsetvl") + (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c new file mode 100644 index 00000000000..661f2c9170e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c @@ -0,0 +1,750 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ + +#include +#include + +size_t test_vsetvl_e8mf8_imm0() +{ + size_t vl = vsetvl_e8mf8(0); + return vl; +} + +size_t test_vsetvl_e8mf8_imm31() +{ + size_t vl = vsetvl_e8mf8(31); + return vl; +} + +size_t test_vsetvl_e8mf8_imm32() +{ + size_t vl = vsetvl_e8mf8(32); + return vl; +} + +size_t test_vsetvl_e8mf8(size_t avl) +{ + size_t vl = vsetvl_e8mf8(avl); + return vl; +} + +size_t test_vsetvlmax_e8mf8() +{ + size_t vl = vsetvlmax_e8mf8(); + return vl; +} + +size_t test_vsetvl_e8mf4_imm0() +{ + size_t vl = vsetvl_e8mf4(0); + return vl; +} + +size_t test_vsetvl_e8mf4_imm31() +{ + size_t vl = vsetvl_e8mf4(31); + return vl; +} + +size_t test_vsetvl_e8mf4_imm32() +{ + size_t vl = vsetvl_e8mf4(32); + return vl; +} + +size_t test_vsetvl_e8mf4(size_t avl) +{ + size_t vl = vsetvl_e8mf4(avl); + return vl; +} + +size_t test_vsetvlmax_e8mf4() +{ + size_t vl = vsetvlmax_e8mf4(); + return vl; +} + +size_t test_vsetvl_e8mf2_imm0() +{ + size_t vl = vsetvl_e8mf2(0); + return vl; +} + +size_t test_vsetvl_e8mf2_imm31() +{ + size_t vl = vsetvl_e8mf2(31); + return vl; +} + +size_t test_vsetvl_e8mf2_imm32() +{ + size_t vl = vsetvl_e8mf2(32); + return vl; +} + +size_t test_vsetvl_e8mf2(size_t avl) +{ + size_t vl = vsetvl_e8mf2(avl); + return vl; +} + +size_t test_vsetvlmax_e8mf2() +{ + size_t vl = vsetvlmax_e8mf2(); + return vl; +} + +size_t test_vsetvl_e8m1_imm0() +{ + size_t vl = vsetvl_e8m1(0); + return vl; +} + +size_t test_vsetvl_e8m1_imm31() +{ + size_t vl = vsetvl_e8m1(31); + return vl; +} + +size_t test_vsetvl_e8m1_imm32() +{ + size_t vl = vsetvl_e8m1(32); + return vl; +} + +size_t test_vsetvl_e8m1(size_t avl) +{ + size_t vl = vsetvl_e8m1(avl); + return vl; +} + +size_t test_vsetvlmax_e8m1() +{ + size_t vl = vsetvlmax_e8m1(); + return vl; +} + +size_t test_vsetvl_e8m2_imm0() +{ + size_t vl = vsetvl_e8m2(0); + return vl; +} + +size_t test_vsetvl_e8m2_imm31() +{ + size_t vl = vsetvl_e8m2(31); + return vl; +} + +size_t test_vsetvl_e8m2_imm32() +{ + size_t vl = vsetvl_e8m2(32); + return vl; +} + +size_t test_vsetvl_e8m2(size_t avl) +{ + size_t vl = vsetvl_e8m2(avl); + return vl; +} + +size_t test_vsetvlmax_e8m2() +{ + size_t vl = vsetvlmax_e8m2(); + return vl; +} + +size_t test_vsetvl_e8m4_imm0() +{ + size_t vl = vsetvl_e8m4(0); + return vl; +} + +size_t test_vsetvl_e8m4_imm31() +{ + size_t vl = vsetvl_e8m4(31); + return vl; +} + +size_t test_vsetvl_e8m4_imm32() +{ + size_t vl = vsetvl_e8m4(32); + return vl; +} +size_t test_vsetvl_e8m4(size_t avl) +{ + size_t vl = vsetvl_e8m4(avl); + return vl; +} + +size_t test_vsetvlmax_e8m4() +{ + size_t vl = vsetvlmax_e8m4(); + return vl; +} + +size_t test_vsetvl_e8m8_imm0() +{ + size_t vl = vsetvl_e8m8(0); + return vl; +} + +size_t test_vsetvl_e8m8_imm31() +{ + size_t vl = vsetvl_e8m8(31); + return vl; +} + +size_t test_vsetvl_e8m8_imm32() +{ + size_t vl = vsetvl_e8m8(32); + return vl; +} + +size_t test_vsetvl_e8m8(size_t avl) +{ + size_t vl = vsetvl_e8m8(avl); + return vl; +} + +size_t test_vsetvlmax_e8m8() +{ + size_t vl = vsetvlmax_e8m8(); + return vl; +} + +size_t test_vsetvl_e16mf4_imm0() +{ + size_t vl = vsetvl_e16mf4(0); + return vl; +} + +size_t test_vsetvl_e16mf4_imm31() +{ + size_t vl = vsetvl_e16mf4(31); + return vl; +} + +size_t test_vsetvl_e16mf4_imm32() +{ + size_t vl = vsetvl_e16mf4(32); + return vl; +} + +size_t test_vsetvl_e16mf4(size_t avl) +{ + size_t vl = vsetvl_e16mf4(avl); + return vl; +} + +size_t test_vsetvlmax_e16mf4() +{ + size_t vl = vsetvlmax_e16mf4(); + return vl; +} + +size_t test_vsetvl_e16mf2_imm0() +{ + size_t vl = vsetvl_e16mf2(0); + return vl; +} + +size_t test_vsetvl_e16mf2_imm31() +{ + size_t vl = vsetvl_e16mf2(31); + return vl; +} + +size_t test_vsetvl_e16mf2_imm32() +{ + size_t vl = vsetvl_e16mf2(32); + return vl; +} + +size_t test_vsetvl_e16mf2(size_t avl) +{ + size_t vl = vsetvl_e16mf2(avl); + return vl; +} + +size_t test_vsetvlmax_e16mf2() +{ + size_t vl = vsetvlmax_e16mf2(); + return vl; +} + +size_t test_vsetvl_e16m1_imm0() +{ + size_t vl = vsetvl_e16m1(0); + return vl; +} + +size_t test_vsetvl_e16m1_imm31() +{ + size_t vl = vsetvl_e16m1(31); + return vl; +} + +size_t test_vsetvl_e16m1_imm32() +{ + size_t vl = vsetvl_e16m1(32); + return vl; +} + +size_t test_vsetvl_e16m1(size_t avl) +{ + size_t vl = vsetvl_e16m1(avl); + return vl; +} + +size_t test_vsetvlmax_e16m1() +{ + size_t vl = vsetvlmax_e16m1(); + return vl; +} + +size_t test_vsetvl_e16m2_imm0() +{ + size_t vl = vsetvl_e16m2(0); + return vl; +} + +size_t test_vsetvl_e16m2_imm31() +{ + size_t vl = vsetvl_e16m2(31); + return vl; +} + +size_t test_vsetvl_e16m2_imm32() +{ + size_t vl = vsetvl_e16m2(32); + return vl; +} + +size_t test_vsetvl_e16m2(size_t avl) +{ + size_t vl = vsetvl_e16m2(avl); + return vl; +} + +size_t test_vsetvlmax_e16m2() +{ + size_t vl = vsetvlmax_e16m2(); + return vl; +} + +size_t test_vsetvl_e16m4_imm0() +{ + size_t vl = vsetvl_e16m4(0); + return vl; +} + +size_t test_vsetvl_e16m4_imm31() +{ + size_t vl = vsetvl_e16m4(31); + return vl; +} + +size_t test_vsetvl_e16m4_imm32() +{ + size_t vl = vsetvl_e16m4(32); + return vl; +} + +size_t test_vsetvl_e16m4(size_t avl) +{ + size_t vl = vsetvl_e16m4(avl); + return vl; +} + +size_t test_vsetvlmax_e16m4() +{ + size_t vl = vsetvlmax_e16m4(); + return vl; +} + +size_t test_vsetvl_e16m8_imm0() +{ + size_t vl = vsetvl_e16m8(0); + return vl; +} + +size_t test_vsetvl_e16m8_imm31() +{ + size_t vl = vsetvl_e16m8(31); + return vl; +} + +size_t test_vsetvl_e16m8_imm32() +{ + size_t vl = vsetvl_e16m8(32); + return vl; +} + +size_t test_vsetvl_e16m8(size_t avl) +{ + size_t vl = vsetvl_e16m8(avl); + return vl; +} + +size_t test_vsetvlmax_e16m8() +{ + size_t vl = vsetvlmax_e16m8(); + return vl; +} + +size_t test_vsetvl_e32mf2_imm0() +{ + size_t vl = vsetvl_e32mf2(0); + return vl; +} + +size_t test_vsetvl_e32mf2_imm31() +{ + size_t vl = vsetvl_e32mf2(31); + return vl; +} + +size_t test_vsetvl_e32mf2_imm32() +{ + size_t vl = vsetvl_e32mf2(32); + return vl; +} + +size_t test_vsetvl_e32mf2(size_t avl) +{ + size_t vl = vsetvl_e32mf2(avl); + return vl; +} + +size_t test_vsetvlmax_e32mf2() +{ + size_t vl = vsetvlmax_e32mf2(); + return vl; +} + +size_t test_vsetvl_e32m1_imm0() +{ + size_t vl = vsetvl_e32m1(0); + return vl; +} + +size_t test_vsetvl_e32m1_imm31() +{ + size_t vl = vsetvl_e32m1(31); + return vl; +} + +size_t test_vsetvl_e32m1_imm32() +{ + size_t vl = vsetvl_e32m1(32); + return vl; +} + +size_t test_vsetvl_e32m1(size_t avl) +{ + size_t vl = vsetvl_e32m1(avl); + return vl; +} + +size_t test_vsetvlmax_e32m1() +{ + size_t vl = vsetvlmax_e32m1(); + return vl; +} + +size_t test_vsetvl_e32m2_imm0() +{ + size_t vl = vsetvl_e32m2(0); + return vl; +} + +size_t test_vsetvl_e32m2_imm31() +{ + size_t vl = vsetvl_e32m2(31); + return vl; +} + +size_t test_vsetvl_e32m2_imm32() +{ + size_t vl = vsetvl_e32m2(32); + return vl; +} + +size_t test_vsetvl_e32m2(size_t avl) +{ + size_t vl = vsetvl_e32m2(avl); + return vl; +} + +size_t test_vsetvlmax_e32m2() +{ + size_t vl = vsetvlmax_e32m2(); + return vl; +} + +size_t test_vsetvl_e32m4_imm0() +{ + size_t vl = vsetvl_e32m4(0); + return vl; +} + +size_t test_vsetvl_e32m4_imm31() +{ + size_t vl = vsetvl_e32m4(31); + return vl; +} + +size_t test_vsetvl_e32m4_imm32() +{ + size_t vl = vsetvl_e32m4(32); + return vl; +} + +size_t test_vsetvl_e32m4(size_t avl) +{ + size_t vl = vsetvl_e32m4(avl); + return vl; +} + +size_t test_vsetvlmax_e32m4() +{ + size_t vl = vsetvlmax_e32m4(); + return vl; +} + +size_t test_vsetvl_e32m8_imm0() +{ + size_t vl = vsetvl_e32m8(0); + return vl; +} + +size_t test_vsetvl_e32m8_imm31() +{ + size_t vl = vsetvl_e32m8(31); + return vl; +} + +size_t test_vsetvl_e32m8_imm32() +{ + size_t vl = vsetvl_e32m8(32); + return vl; +} +size_t test_vsetvl_e32m8(size_t avl) +{ + size_t vl = vsetvl_e32m8(avl); + return vl; +} + +size_t test_vsetvlmax_e32m8() +{ + size_t vl = vsetvlmax_e32m8(); + return vl; +} + +size_t test_vsetvl_e64m1_imm0() +{ + size_t vl = vsetvl_e64m1(0); + return vl; +} + +size_t test_vsetvl_e64m1_imm31() +{ + size_t vl = vsetvl_e64m1(31); + return vl; +} + +size_t test_vsetvl_e64m1_imm32() +{ + size_t vl = vsetvl_e64m1(32); + return vl; +} + +size_t test_vsetvl_e64m1(size_t avl) +{ + size_t vl = vsetvl_e64m1(avl); + return vl; +} + +size_t test_vsetvlmax_e64m1() +{ + size_t vl = vsetvlmax_e64m1(); + return vl; +} + +size_t test_vsetvl_e64m2_imm0() +{ + size_t vl = vsetvl_e64m2(0); + return vl; +} + +size_t test_vsetvl_e64m2_imm31() +{ + size_t vl = vsetvl_e64m2(31); + return vl; +} + +size_t test_vsetvl_e64m2_imm32() +{ + size_t vl = vsetvl_e64m2(32); + return vl; +} +size_t test_vsetvl_e64m2(size_t avl) +{ + size_t vl = vsetvl_e64m2(avl); + return vl; +} + +size_t test_vsetvlmax_e64m2() +{ + size_t vl = vsetvlmax_e64m2(); + return vl; +} + +size_t test_vsetvl_e64m4_imm0() +{ + size_t vl = vsetvl_e64m4(0); + return vl; +} + +size_t test_vsetvl_e64m4_imm31() +{ + size_t vl = vsetvl_e64m4(31); + return vl; +} + +size_t test_vsetvl_e64m4_imm32() +{ + size_t vl = vsetvl_e64m4(32); + return vl; +} + +size_t test_vsetvl_e64m4(size_t avl) +{ + size_t vl = vsetvl_e64m4(avl); + return vl; +} + +size_t test_vsetvlmax_e64m4() +{ + size_t vl = vsetvlmax_e64m4(); + return vl; +} + +size_t test_vsetvl_e64m8_imm0() +{ + size_t vl = vsetvl_e64m8(0); + return vl; +} + +size_t test_vsetvl_e64m8_imm31() +{ + size_t vl = vsetvl_e64m8(31); + return vl; +} + +size_t test_vsetvl_e64m8_imm32() +{ + size_t vl = vsetvl_e64m8(32); + return vl; +} +size_t test_vsetvl_e64m8(size_t avl) +{ + size_t vl = vsetvl_e64m8(avl); + return vl; +} + +size_t test_vsetvlmax_e64m8() +{ + size_t vl = vsetvlmax_e64m8(); + return vl; +} + +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf4,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*mf2,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*mf2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m1,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m2,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m4,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e16,\s*m8,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e16,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*mf2,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*mf2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m1,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m2,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m4,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e32,\s*m8,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e32,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m1,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m1,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m2,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m2,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m4,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*0,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*31,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*e64,\s*m8,\s*ta,\s*mu} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e64,\s*m8,\s*ta,\s*mu} 1 } } */