From patchwork Mon Oct 17 08:12:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfeng Ye X-Patchwork-Id: 3268 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1328861wrs; Mon, 17 Oct 2022 01:16:28 -0700 (PDT) X-Google-Smtp-Source: AMsMyM70xf+k3Rxmn/Cj9RMqsgNHvfiGaSPYcLZQ4OaAXftzTnboxTIi1rb0UMvSKLw+eF9B1d6X X-Received: by 2002:a17:902:f641:b0:17f:3633:5439 with SMTP id m1-20020a170902f64100b0017f36335439mr10868002plg.94.1665994588652; Mon, 17 Oct 2022 01:16:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665994588; cv=none; d=google.com; s=arc-20160816; b=u7/cr6jildqaiuKuBCQYB619rFmZ4M8JsRFfNpPPjcl60hv42jj+nCrm2izod8U62Y lnzuIKuIYRnl8SVKZLbxoCnwGbfNUUYM+MqdUiqKFLak49RQNBtka24Ir0zj3EQw6CYu i12+wSLJKfnbKmB7c1ZnmRyHANrnh4YbySZU3s9Rvf3wF2iVqfxpkkQWfWjTeordC+gl rhYUwRM4BLDbX+qXjwbgCxYECaxycnTiB+V4gfJMzuYlutbjd5OMV65SLJbAABO/4raD +IRT/K+LMUvSSiFkLPA81uH3J139V/MpzkcDjayt89GvzczaaMFCMdiJdb3QaFciWP2T /uTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from; bh=vil5wfA+bNFxOKO+afllxL779Wns6Xlb9zIczuv8bzc=; b=LPT1DtzM5osGysKPvROwkhQ1MwzHbiqTblqfnFM7y5229xzqGwEXxB0xwiEK7wUH68 n2lYmjT5plavmWxr/1S2+yG9DSttjWxFQx7SfBCpdN6oD7rZP8JGyY3xgJct2XE4SRqx nr8P6nqESyLxAQ/zQGJgvaYYda7enPCPUF6MZMQsSN6ZjOdsxZ1/A3P9MVUlEir+cJid V7hOiUDffFB6JWXuMV9rH+M/vDEJoHp4B/s9+u5BLevhj8/OgjkIMF3Qnwla0PtpbkmH I0XXxEGnmRdk0Ges0v/V27UzguhWZa5RCyiDFr5i75JHBbbTq/tZvAYSf2E+/e40Lios fOIg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d14-20020aa7868e000000b0055035da1c58si10044273pfo.138.2022.10.17.01.16.15; Mon, 17 Oct 2022 01:16:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230072AbiJQINx (ORCPT + 99 others); Mon, 17 Oct 2022 04:13:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229949AbiJQINk (ORCPT ); Mon, 17 Oct 2022 04:13:40 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D8245C360 for ; Mon, 17 Oct 2022 01:13:36 -0700 (PDT) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4MrV4h2cfnz1P7SM; Mon, 17 Oct 2022 16:08:52 +0800 (CST) Received: from huawei.com (10.44.134.232) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 17 Oct 2022 16:13:03 +0800 From: y00318929 To: , , , , , Subject: [PATCH 1/5] arm64: mm: Define asid_bitmap structure for pinned_asid Date: Mon, 17 Oct 2022 16:12:54 +0800 Message-ID: <20221017081258.3678830-2-yeyunfeng@huawei.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221017081258.3678830-1-yeyunfeng@huawei.com> References: <20221017081258.3678830-1-yeyunfeng@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.44.134.232] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746921941578836831?= X-GMAIL-MSGID: =?utf-8?q?1746921941578836831?= From: Yunfeng Ye It is clearer to use the asid_bitmap structure for pinned_sid, and we will use it for isolated asid later. No functional change. Signed-off-by: Yunfeng Ye --- arch/arm64/mm/context.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index e1e0dca01839..8549b5f30352 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -17,6 +17,12 @@ #include #include +struct asid_bitmap { + unsigned long *map; + unsigned long nr; + unsigned long max; +}; + static u32 asid_bits; static DEFINE_RAW_SPINLOCK(cpu_asid_lock); @@ -27,9 +33,7 @@ static DEFINE_PER_CPU(atomic64_t, active_asids); static DEFINE_PER_CPU(u64, reserved_asids); static cpumask_t tlb_flush_pending; -static unsigned long max_pinned_asids; -static unsigned long nr_pinned_asids; -static unsigned long *pinned_asid_map; +static struct asid_bitmap pinned_asid; #define ASID_MASK (~GENMASK(asid_bits - 1, 0)) #define ASID_FIRST_VERSION (1UL << asid_bits) @@ -90,8 +94,8 @@ static void set_kpti_asid_bits(unsigned long *map) static void set_reserved_asid_bits(void) { - if (pinned_asid_map) - bitmap_copy(asid_map, pinned_asid_map, NUM_USER_ASIDS); + if (pinned_asid.map) + bitmap_copy(asid_map, pinned_asid.map, NUM_USER_ASIDS); else if (arm64_kernel_unmapped_at_el0()) set_kpti_asid_bits(asid_map); else @@ -275,7 +279,7 @@ unsigned long arm64_mm_context_get(struct mm_struct *mm) unsigned long flags; u64 asid; - if (!pinned_asid_map) + if (!pinned_asid.map) return 0; raw_spin_lock_irqsave(&cpu_asid_lock, flags); @@ -285,7 +289,7 @@ unsigned long arm64_mm_context_get(struct mm_struct *mm) if (refcount_inc_not_zero(&mm->context.pinned)) goto out_unlock; - if (nr_pinned_asids >= max_pinned_asids) { + if (pinned_asid.nr >= pinned_asid.max) { asid = 0; goto out_unlock; } @@ -299,8 +303,8 @@ unsigned long arm64_mm_context_get(struct mm_struct *mm) atomic64_set(&mm->context.id, asid); } - nr_pinned_asids++; - __set_bit(ctxid2asid(asid), pinned_asid_map); + pinned_asid.nr++; + __set_bit(ctxid2asid(asid), pinned_asid.map); refcount_set(&mm->context.pinned, 1); out_unlock: @@ -321,14 +325,14 @@ void arm64_mm_context_put(struct mm_struct *mm) unsigned long flags; u64 asid = atomic64_read(&mm->context.id); - if (!pinned_asid_map) + if (!pinned_asid.map) return; raw_spin_lock_irqsave(&cpu_asid_lock, flags); if (refcount_dec_and_test(&mm->context.pinned)) { - __clear_bit(ctxid2asid(asid), pinned_asid_map); - nr_pinned_asids--; + __clear_bit(ctxid2asid(asid), pinned_asid.map); + pinned_asid.nr--; } raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); @@ -377,8 +381,8 @@ static int asids_update_limit(void) if (arm64_kernel_unmapped_at_el0()) { num_available_asids /= 2; - if (pinned_asid_map) - set_kpti_asid_bits(pinned_asid_map); + if (pinned_asid.map) + set_kpti_asid_bits(pinned_asid.map); } /* * Expect allocation after rollover to fail if we don't have at least @@ -393,7 +397,7 @@ static int asids_update_limit(void) * even if all CPUs have a reserved ASID and the maximum number of ASIDs * are pinned, there still is at least one empty slot in the ASID map. */ - max_pinned_asids = num_available_asids - num_possible_cpus() - 2; + pinned_asid.max = num_available_asids - num_possible_cpus() - 2; return 0; } arch_initcall(asids_update_limit); @@ -407,8 +411,8 @@ static int asids_init(void) panic("Failed to allocate bitmap for %lu ASIDs\n", NUM_USER_ASIDS); - pinned_asid_map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); - nr_pinned_asids = 0; + pinned_asid.map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); + pinned_asid.nr = 0; /* * We cannot call set_reserved_asid_bits() here because CPU From patchwork Mon Oct 17 08:12:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfeng Ye X-Patchwork-Id: 3265 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1328742wrs; Mon, 17 Oct 2022 01:16:06 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6eQxCV/kyO0d2U05V72WFNhXxmz+HQh+2JDta1FIBIzd9VhvL3tw9xI2t8Q0SUUnB08whc X-Received: by 2002:a17:902:7104:b0:17f:cdc1:f4c3 with SMTP id a4-20020a170902710400b0017fcdc1f4c3mr10630387pll.149.1665994565989; Mon, 17 Oct 2022 01:16:05 -0700 (PDT) ARC-Seal: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s10-20020a170902ea0a00b0018010c3d7e3si12965632plg.404.2022.10.17.01.15.53; Mon, 17 Oct 2022 01:16:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230258AbiJQINq (ORCPT + 99 others); Mon, 17 Oct 2022 04:13:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230050AbiJQINi (ORCPT ); Mon, 17 Oct 2022 04:13:38 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B48B35C372 for ; Mon, 17 Oct 2022 01:13:36 -0700 (PDT) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4MrV4h2sCDz1P7YB; Mon, 17 Oct 2022 16:08:52 +0800 (CST) Received: from huawei.com (10.44.134.232) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 17 Oct 2022 16:13:03 +0800 From: y00318929 To: , , , , , Subject: [PATCH 2/5] arm64: mm: Extract the processing of asid_generation Date: Mon, 17 Oct 2022 16:12:55 +0800 Message-ID: <20221017081258.3678830-3-yeyunfeng@huawei.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221017081258.3678830-1-yeyunfeng@huawei.com> References: <20221017081258.3678830-1-yeyunfeng@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.44.134.232] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746921917888999578?= X-GMAIL-MSGID: =?utf-8?q?1746921917888999578?= From: Yunfeng Ye To prepare for supporting ASID isolation feature, extract the processing of asid_generation. it is convenient to modify the asid_generation centrally. By the way, It is clearer to put flush_generation() into flush_context(). Signed-off-by: Yunfeng Ye --- arch/arm64/mm/context.c | 39 ++++++++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 8549b5f30352..380c7b05c36b 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -102,14 +102,40 @@ static void set_reserved_asid_bits(void) bitmap_clear(asid_map, 0, NUM_USER_ASIDS); } -#define asid_gen_match(asid) \ - (!(((asid) ^ atomic64_read(&asid_generation)) >> asid_bits)) +static void asid_generation_init(void) +{ + atomic64_set(&asid_generation, ASID_FIRST_VERSION); +} + +static void flush_generation(void) +{ + /* We're out of ASIDs, so increment the global generation count */ + atomic64_add_return_relaxed(ASID_FIRST_VERSION, + &asid_generation); +} + +static inline u64 asid_read_generation(void) +{ + return atomic64_read(&asid_generation); +} + +static inline bool asid_match(u64 asid, u64 genid) +{ + return (!(((asid) ^ (genid)) >> asid_bits)); +} + +static inline bool asid_gen_match(u64 asid) +{ + return asid_match(asid, asid_read_generation()); +} static void flush_context(void) { int i; u64 asid; + flush_generation(); + /* Update the list of reserved ASIDs and the ASID bitmap. */ set_reserved_asid_bits(); @@ -163,7 +189,7 @@ static u64 new_context(struct mm_struct *mm) { static u32 cur_idx = 1; u64 asid = atomic64_read(&mm->context.id); - u64 generation = atomic64_read(&asid_generation); + u64 generation = asid_read_generation(); if (asid != 0) { u64 newasid = asid2ctxid(ctxid2asid(asid), generation); @@ -202,14 +228,12 @@ static u64 new_context(struct mm_struct *mm) if (asid != NUM_USER_ASIDS) goto set_asid; - /* We're out of ASIDs, so increment the global generation count */ - generation = atomic64_add_return_relaxed(ASID_FIRST_VERSION, - &asid_generation); flush_context(); /* We have more ASIDs than CPUs, so this will always succeed */ asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1); + generation = asid_read_generation(); set_asid: __set_bit(asid, asid_map); cur_idx = asid; @@ -405,7 +429,8 @@ arch_initcall(asids_update_limit); static int asids_init(void) { asid_bits = get_cpu_asid_bits(); - atomic64_set(&asid_generation, ASID_FIRST_VERSION); + asid_generation_init(); + asid_map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); if (!asid_map) panic("Failed to allocate bitmap for %lu ASIDs\n", From patchwork Mon Oct 17 08:12:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfeng Ye X-Patchwork-Id: 3266 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1328788wrs; Mon, 17 Oct 2022 01:16:13 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6H9VEqYgA40SLaaJSmqoAGZP+TrTjm0X7tDaKnRy07ocWtoHEiL72sdAC5VwYYhjXycSqY X-Received: by 2002:a65:45c1:0:b0:461:5855:8d86 with SMTP id m1-20020a6545c1000000b0046158558d86mr9533695pgr.436.1665994573327; Mon, 17 Oct 2022 01:16:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665994573; cv=none; d=google.com; s=arc-20160816; b=lSPFPeRXbH0h0opmmPmTt0cVh8NUEU7pfjjuzV1mjQxZC24IA+vtxP0qDjfcwaEFyP Y4siMKLYlfvBl2ZSiJUZPt9B1tjXlmIdIL21kqZKHU2vNSyeqdhBlNTgu71VCnEW2XdR /4SsUSrGOyIj7KKmr2GHQ8e5bu3CINq0nFbWdN4dHipVJYJ5FxD6k3K8/H1qpRsr6SHQ JIVsLPX8HpV22tW4VdoTrhaC/imXcaS/xymCrtzOhrHFfCrZvD5TK+hMzE6sfBNdVsq4 Ydf2RR9zrETckPnSAHYA5qFewW1NCWelFKa8J+TcnszmJTeMMZYyuo3kMQpJgfXeNJZX aOOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from; bh=Q7vA6C/KfZxYTacrgSiiLtRhNznQ0WnUOGoX3klwkLM=; b=tr+3IyyLH+A370ZWc+5JVIZMSeApb+Fc9MEX6YzLlb0SjWsVPxhmCLFkp2LwsaORl8 aSSHfH3ywTat2cV1NbMmUypMsU4W++GRahIlN02O8gRBOTuFEADBDZrrY1hbh12KToAf IvV7w+yQnQ9ybeBWmIiTGr45YorKNJLXHlqVhn3h8T4Arno6++hn+7K0f0QLLom3y9c4 gHLc/ZQiB7+QnRLStlcgcuZ4N22J2wMjP4p4M7vXMEO8xVM4BCzduioFh8FbX4hgUmNZ uhaKXQPdx4wTTvZ88jx/vKW/kaNDoRafvGFDVJkEZLJugb5/n/dxpXAu7pBK72hrzHeV +3wQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k22-20020aa788d6000000b005251a2f06bbsi11520483pff.59.2022.10.17.01.16.00; Mon, 17 Oct 2022 01:16:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230264AbiJQINs (ORCPT + 99 others); Mon, 17 Oct 2022 04:13:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230168AbiJQINj (ORCPT ); Mon, 17 Oct 2022 04:13:39 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4A3A5C377 for ; Mon, 17 Oct 2022 01:13:36 -0700 (PDT) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4MrV4h352tz1P7Zm; Mon, 17 Oct 2022 16:08:52 +0800 (CST) Received: from huawei.com (10.44.134.232) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 17 Oct 2022 16:13:03 +0800 From: y00318929 To: , , , , , Subject: [PATCH 3/5] arm64: mm: Use cpumask in flush_context() Date: Mon, 17 Oct 2022 16:12:56 +0800 Message-ID: <20221017081258.3678830-4-yeyunfeng@huawei.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221017081258.3678830-1-yeyunfeng@huawei.com> References: <20221017081258.3678830-1-yeyunfeng@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.44.134.232] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746921926114121935?= X-GMAIL-MSGID: =?utf-8?q?1746921926114121935?= From: Yunfeng Ye Currently, all CPUs are selected to flush TLB in flush_context(). In order to prepare for flushing only part of the CPUs TLB, we use asid_housekeeping_mask and use cpumask_or() instead of cpumask_setall(). Signed-off-by: Yunfeng Ye --- arch/arm64/mm/context.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 380c7b05c36b..e402997aa1c2 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -32,6 +33,7 @@ static unsigned long *asid_map; static DEFINE_PER_CPU(atomic64_t, active_asids); static DEFINE_PER_CPU(u64, reserved_asids); static cpumask_t tlb_flush_pending; +static const struct cpumask *asid_housekeeping_mask; static struct asid_bitmap pinned_asid; @@ -129,17 +131,23 @@ static inline bool asid_gen_match(u64 asid) return asid_match(asid, asid_read_generation()); } +static const struct cpumask *flush_cpumask(void) +{ + return asid_housekeeping_mask; +} + static void flush_context(void) { int i; u64 asid; + const struct cpumask *cpumask = flush_cpumask(); flush_generation(); /* Update the list of reserved ASIDs and the ASID bitmap. */ set_reserved_asid_bits(); - for_each_possible_cpu(i) { + for_each_cpu(i, cpumask) { asid = atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0); /* * If this CPU has already been through a @@ -158,7 +166,7 @@ static void flush_context(void) * Queue a TLB invalidation for each CPU to perform on next * context-switch */ - cpumask_setall(&tlb_flush_pending); + cpumask_or(&tlb_flush_pending, &tlb_flush_pending, cpumask); } static bool check_update_reserved_asid(u64 asid, u64 newasid) @@ -439,6 +447,8 @@ static int asids_init(void) pinned_asid.map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); pinned_asid.nr = 0; + asid_housekeeping_mask = cpu_possible_mask; + /* * We cannot call set_reserved_asid_bits() here because CPU * caps are not finalized yet, so it is safer to assume KPTI From patchwork Mon Oct 17 08:12:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfeng Ye X-Patchwork-Id: 3267 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1328794wrs; Mon, 17 Oct 2022 01:16:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4CFUbtLypz8/8rK066Q9H6qqynpCrz5M+AndDDvanvc4xqApo135F4m6JpPG60tBDEw9EV X-Received: by 2002:a05:6a00:d72:b0:562:86e9:ae55 with SMTP id n50-20020a056a000d7200b0056286e9ae55mr11323317pfv.13.1665994573922; Mon, 17 Oct 2022 01:16:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665994573; cv=none; d=google.com; s=arc-20160816; b=oJHpantMoxGax0PtY3+NS5PV4ttie9x07I0x0FkkVxHWHQAqfpxLHSq6l/3xNRAbBj WO6+/r0CfFdWwsQsCvDE0Mnjluoujhr99Qb+Elhe5H0aw1HaF5qR6jdxgNbpqVYLTm8u OEhGzglEEClCkUqPrSGborjQj4NaoTLa83CAXRODz2BwMejQ3fWkRoXp28zZuHw7vJkv tWedArkOKqU7IHSFn4YHUy1zbJajNZfOp8x0PeD/Qe0ky/rN+ciZv6Hx0zbBmyzhfsa3 7ygXq+CFX7rK7L32Dun17Y7nKdhv1ks10dTkkELFKDQ3szLYTuMmtVnu4Q4hmnAFLCD0 1gNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from; bh=MCxWTLVaEPnrLiHDKsQ1CHp3tbEfMpO5h+H6hoEg1kA=; b=x5T4znRD2q4IMfSmL5sEGigkyLuycwwkr1T4LueoXVlrGvQ7pJ7iBccFxU8++aa8CM Qjt/QbpXvncHBicTigO3E0lVvJUT7Lvh3tNV+sKi0ls8gD1y8gyyFvSO2jCdRPMkiqOi Z41LYxipadL8eyLeUDwxIdnmtcyHwivTq48NeQO7gpfy28hIwXU066W56pd9Ef0cvwgv YgJY3VjxUKS1vJZgsHB88unrG19t20C9jYsosgG+YJTV6dKrt9Pl580cG8rqIJUWeE2d XjNlhjpUX3wuSg5M5NXuZ4FhE1IFEfD1S8pIf8SEAK66YAuP3JN6btzlROSqnghVzVlZ geEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q29-20020a635c1d000000b0045131d08c18si11631883pgb.244.2022.10.17.01.16.01; Mon, 17 Oct 2022 01:16:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230283AbiJQIN4 (ORCPT + 99 others); Mon, 17 Oct 2022 04:13:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230190AbiJQINl (ORCPT ); Mon, 17 Oct 2022 04:13:41 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4B345C37F for ; Mon, 17 Oct 2022 01:13:36 -0700 (PDT) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4MrV4j0N2Vz1P7hW; Mon, 17 Oct 2022 16:08:53 +0800 (CST) Received: from huawei.com (10.44.134.232) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 17 Oct 2022 16:13:03 +0800 From: y00318929 To: , , , , , Subject: [PATCH 4/5] arm64: mm: Support ASID isolation feature Date: Mon, 17 Oct 2022 16:12:57 +0800 Message-ID: <20221017081258.3678830-5-yeyunfeng@huawei.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221017081258.3678830-1-yeyunfeng@huawei.com> References: <20221017081258.3678830-1-yeyunfeng@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.44.134.232] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746921926653841081?= X-GMAIL-MSGID: =?utf-8?q?1746921926653841081?= From: Yunfeng Ye After a rollover, the global generation will be flushed, which will cause the process mm->context.id on all CPUs do not match the generation. Thus, the process will compete for the global spinlock lock to reallocate a new ASID and refresh the TLBs of all CPUs on context switch. This will lead to the increase of scheduling delay and TLB miss. In some delay-sensitive scenarios, for example, part of CPUs are isolated, only a limited number of processes are deployed to run on the isolated CPUs. In this case, we do not want these key processes to be affected by the rollover of ASID. An ASID isolation method can reduce interference. We divide the asid_generation into different domains, for example, HOUSEKEEPING and ISOLATION. Processes in different domains allocate ASID from the shared asid_map pool, then combine with the generation of local domain as the mm->context.id. After an ASID rollover, the generation of the HOUSEKEEPING domain can be flushed independently, and only the TLB of HOUSEKEEPING domain CPUs will be flushed, so the processes of ISOLATION domain will not be affected. In addition, the ASID of the ISOLATION domain is stored in the isolated_asid bitmap. When the asid_map is refreshed, the isolated_asid must be copied to the asid_map to ensure that the ASID of the ISOLATION domain is not allocated by other processes. The following figure shows the example: HOUSEKEEPING (genid: G1) ISOLATION (genid: G2) task1(G1,1) task2(G2,2) task3(G2,3) cpu0 cpu1 cpu3 cpu4 cpu5 ------------------------- ----------------------- \ / | \ / isolated_asid: [2,3] \ / asid_map: [1,2,3,4,...,65536] The task1 is running on the HOUSEKEEPING domain, it allocate ASID 1 from shared asid_map, so the context id of task1 is (G1,1). The task2 and task3 are running on the ISOLATION domain, they allocate ASID 2,3 from shared asid_map, and store ASID 2,3 to isolated_asid. the context id of task2 is (G2,2), and the context id of task3 is (G2,3). After a rollover, the generation of HOUSEKEEPING doamin is flushed, for example, it becomes to G3, then the context id of task1 is changed to (G3,1). In this time, the generation of ISOLATION domain is not affected. In some scenarios, a process has multiple threads, and different threads run in different domains, or processes migrate between different domains. But the process has only one context ID, there is a problem that how to select generation in this case. The way we're thinking is, as long as the process has run to ISOLATION doamin, select generation of ISOLATION doamin. For example: HOUSEKEEPING (genid: G1) ISOLATION (genid: G2) task1(G1,1) ====> task1(G2,1) task2(G2,2) <==== task2(G2,2) cpu0 cpu1 cpu3 cpu4 cpu5 ------------------------- ----------------------- When task1 is migrated from HOUSEKEEPING domain to ISOLATION domain, the generation G1 must be changed to G2, and save the ASID 1 to isolated_asid bitmap. But when task2 is migrated from ISOLATION domain to HOUSEKEEPING domain, it still use generation G2. In this way, we solve the problem that which generation should be selected in the scenario of process migration. As mentioned before, the generation of different domains is different. we divide the generation into two parts, the lowest bit is used as the Flag bit to indicate the HOUSEKEEPING and ISOLATION domain, and the rest bits are used as the Upper-generation. After a rollover, only the Upper-generation is flushed, the Flag part does not change in the entire life. This ensures that the genrentaion of different domains is different. asid_generation |---------------------------|-|--------| Upper-generation Flag Finally, it is important to select which domain generation and TLBs are flushed after a rollover. By default, only the HOUSEKEEPING domain is selected. When the number of ASIDs in the ISOLATION domain exceeds the max threshold, the ISOLATION domain is selected too. By default, the ASID isolation feature is disabled, and a cmdline parameter is provided to control whether the ASID isolation feature is enabled. Signed-off-by: Yunfeng Ye --- arch/arm64/mm/context.c | 203 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 183 insertions(+), 20 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index e402997aa1c2..0ea3e7485ae7 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -24,10 +25,20 @@ struct asid_bitmap { unsigned long max; }; +enum { + ASID_HOUSEKEEPING = 0, + ASID_ISOLATION = 1, + ASID_TYPE_MAX, +}; + +struct asid_domain { + atomic64_t asid_generation; +}; + static u32 asid_bits; static DEFINE_RAW_SPINLOCK(cpu_asid_lock); -static atomic64_t asid_generation; +static struct asid_domain asid_domain[ASID_TYPE_MAX]; static unsigned long *asid_map; static DEFINE_PER_CPU(atomic64_t, active_asids); @@ -36,11 +47,16 @@ static cpumask_t tlb_flush_pending; static const struct cpumask *asid_housekeeping_mask; static struct asid_bitmap pinned_asid; +static struct asid_bitmap isolated_asid; + +static int asid_isolation_cmdline; +static DEFINE_STATIC_KEY_FALSE(asid_isolation_enable); #define ASID_MASK (~GENMASK(asid_bits - 1, 0)) -#define ASID_FIRST_VERSION (1UL << asid_bits) +#define NUM_USER_ASIDS (1UL << asid_bits) -#define NUM_USER_ASIDS ASID_FIRST_VERSION +#define ASID_ISOLATION_FLAG (NUM_USER_ASIDS) +#define ASID_FIRST_VERSION (NUM_USER_ASIDS << 1) #define ctxid2asid(asid) ((asid) & ~ASID_MASK) #define asid2ctxid(asid, genid) ((asid) | (genid)) @@ -94,6 +110,61 @@ static void set_kpti_asid_bits(unsigned long *map) memset(map, 0xaa, len); } +static inline bool is_isolated_asid(u64 asid) +{ + /* + * Note that asid 0 is not the isolated asid. The judgment + * is correct in this situation since the ASID_ISOLATION_FLAG + * bit is defined as 1 to indicate ISOLATION domain. + */ + return asid & ASID_ISOLATION_FLAG; +} + +static inline bool on_isolated_cpu(int cpu) +{ + return !cpumask_test_cpu(cpu, asid_housekeeping_mask); +} + +static inline int asid_domain_type(u64 asid, unsigned int cpu) +{ + if (on_isolated_cpu(cpu) || is_isolated_asid(asid)) + return ASID_ISOLATION; + + return ASID_HOUSEKEEPING; +} + +static inline int asid_flush_type(void) +{ + if (isolated_asid.nr > isolated_asid.max) + return ASID_ISOLATION; + else + return ASID_HOUSEKEEPING; +} + +static void asid_try_to_isolate(u64 asid) +{ + if (!static_branch_unlikely(&asid_isolation_enable)) + return; + + if (!is_isolated_asid(asid)) + return; + if (!__test_and_set_bit(ctxid2asid(asid), isolated_asid.map)) + isolated_asid.nr++; +} + +static void update_reserved_asid_bits(void) +{ + if (!static_branch_unlikely(&asid_isolation_enable)) + return; + + if (asid_flush_type() == ASID_HOUSEKEEPING) { + bitmap_or(asid_map, asid_map, isolated_asid.map, NUM_USER_ASIDS); + } else { + bitmap_zero(isolated_asid.map, NUM_USER_ASIDS); + isolated_asid.nr = 0; + } +} + static void set_reserved_asid_bits(void) { if (pinned_asid.map) @@ -102,23 +173,51 @@ static void set_reserved_asid_bits(void) set_kpti_asid_bits(asid_map); else bitmap_clear(asid_map, 0, NUM_USER_ASIDS); + + update_reserved_asid_bits(); } static void asid_generation_init(void) { - atomic64_set(&asid_generation, ASID_FIRST_VERSION); + struct asid_domain *ad; + + ad = &asid_domain[ASID_HOUSEKEEPING]; + atomic64_set(&ad->asid_generation, ASID_FIRST_VERSION); + + ad = &asid_domain[ASID_ISOLATION]; + atomic64_set(&ad->asid_generation, ASID_ISOLATION_FLAG); } static void flush_generation(void) { + struct asid_domain *ad = &asid_domain[ASID_HOUSEKEEPING]; + /* We're out of ASIDs, so increment the global generation count */ atomic64_add_return_relaxed(ASID_FIRST_VERSION, - &asid_generation); + &ad->asid_generation); + + if (asid_flush_type() == ASID_ISOLATION) { + ad = &asid_domain[ASID_ISOLATION]; + atomic64_add_return_relaxed(ASID_FIRST_VERSION, + &ad->asid_generation); + } } -static inline u64 asid_read_generation(void) +static inline u64 asid_read_generation(int type) { - return atomic64_read(&asid_generation); + struct asid_domain *ad = &asid_domain[type]; + + return atomic64_read(&ad->asid_generation); +} + +static inline u64 asid_curr_generation(u64 asid) +{ + int type = ASID_HOUSEKEEPING; + + if (static_branch_unlikely(&asid_isolation_enable)) + type = asid_domain_type(asid, smp_processor_id()); + + return asid_read_generation(type); } static inline bool asid_match(u64 asid, u64 genid) @@ -128,12 +227,28 @@ static inline bool asid_match(u64 asid, u64 genid) static inline bool asid_gen_match(u64 asid) { - return asid_match(asid, asid_read_generation()); + return asid_match(asid, asid_curr_generation(asid)); +} + +static bool asid_is_migrated(u64 asid, u64 newasid) +{ + if (!static_branch_unlikely(&asid_isolation_enable)) + return false; + + if (!is_isolated_asid(asid) && is_isolated_asid(newasid)) { + u64 generation = asid_read_generation(ASID_HOUSEKEEPING); + + return asid_match(asid, generation); + } + return false; } static const struct cpumask *flush_cpumask(void) { - return asid_housekeeping_mask; + if (asid_flush_type() == ASID_HOUSEKEEPING) + return asid_housekeeping_mask; + + return cpu_possible_mask; } static void flush_context(void) @@ -159,6 +274,7 @@ static void flush_context(void) if (asid == 0) asid = per_cpu(reserved_asids, i); __set_bit(ctxid2asid(asid), asid_map); + asid_try_to_isolate(asid); per_cpu(reserved_asids, i) = asid; } @@ -193,21 +309,23 @@ static bool check_update_reserved_asid(u64 asid, u64 newasid) return hit; } -static u64 new_context(struct mm_struct *mm) +static u64 new_context(struct mm_struct *mm, unsigned int cpu) { static u32 cur_idx = 1; u64 asid = atomic64_read(&mm->context.id); - u64 generation = asid_read_generation(); + int domain = asid_domain_type(asid, cpu); + u64 generation = asid_read_generation(domain); + u64 newasid; if (asid != 0) { - u64 newasid = asid2ctxid(ctxid2asid(asid), generation); + newasid = asid2ctxid(ctxid2asid(asid), generation); /* * If our current ASID was active during a rollover, we * can continue to use it and this was just a false alarm. */ if (check_update_reserved_asid(asid, newasid)) - return newasid; + goto out; /* * If it is pinned, we can keep using it. Note that reserved @@ -215,14 +333,21 @@ static u64 new_context(struct mm_struct *mm) * update the generation into the reserved_asids. */ if (refcount_read(&mm->context.pinned)) - return newasid; + goto out; /* * We had a valid ASID in a previous life, so try to re-use * it if possible. */ if (!__test_and_set_bit(ctxid2asid(asid), asid_map)) - return newasid; + goto out; + + /* + * We still have a valid ASID now, but the ASID is migrated from + * normal to isolated domain, we should re-use it. + */ + if (asid_is_migrated(asid, newasid)) + goto out; } /* @@ -241,11 +366,14 @@ static u64 new_context(struct mm_struct *mm) /* We have more ASIDs than CPUs, so this will always succeed */ asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1); - generation = asid_read_generation(); + generation = asid_read_generation(domain); set_asid: __set_bit(asid, asid_map); cur_idx = asid; - return asid2ctxid(asid, generation); + newasid = asid2ctxid(asid, generation); +out: + asid_try_to_isolate(newasid); + return newasid; } void check_and_switch_context(struct mm_struct *mm) @@ -282,12 +410,12 @@ void check_and_switch_context(struct mm_struct *mm) raw_spin_lock_irqsave(&cpu_asid_lock, flags); /* Check that our ASID belongs to the current generation. */ asid = atomic64_read(&mm->context.id); + cpu = smp_processor_id(); if (!asid_gen_match(asid)) { - asid = new_context(mm); + asid = new_context(mm, cpu); atomic64_set(&mm->context.id, asid); } - cpu = smp_processor_id(); if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) local_flush_tlb_all(); @@ -327,11 +455,12 @@ unsigned long arm64_mm_context_get(struct mm_struct *mm) } if (!asid_gen_match(asid)) { + unsigned int cpu = smp_processor_id(); /* * We went through one or more rollover since that ASID was * used. Ensure that it is still valid, or generate a new one. */ - asid = new_context(mm); + asid = new_context(mm, cpu); atomic64_set(&mm->context.id, asid); } @@ -430,10 +559,36 @@ static int asids_update_limit(void) * are pinned, there still is at least one empty slot in the ASID map. */ pinned_asid.max = num_available_asids - num_possible_cpus() - 2; + + /* + * Generally, the user does not care about the number of asids, so set + * to half of the total number as the default setting of the maximum + * threshold of the isolated asid. + */ + if (isolated_asid.map) + isolated_asid.max = num_available_asids / 2; + return 0; } arch_initcall(asids_update_limit); +static void asid_isolation_init(void) +{ + if (asid_isolation_cmdline == 0) + return; + + if (!housekeeping_enabled(HK_TYPE_DOMAIN)) + return; + + isolated_asid.map = bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); + if (!isolated_asid.map) + return; + + asid_housekeeping_mask = housekeeping_cpumask(HK_TYPE_DOMAIN); + static_branch_enable(&asid_isolation_enable); + pr_info("ASID Isolation enable\n"); +} + static int asids_init(void) { asid_bits = get_cpu_asid_bits(); @@ -448,6 +603,7 @@ static int asids_init(void) pinned_asid.nr = 0; asid_housekeeping_mask = cpu_possible_mask; + asid_isolation_init(); /* * We cannot call set_reserved_asid_bits() here because CPU @@ -459,3 +615,10 @@ static int asids_init(void) return 0; } early_initcall(asids_init); + +static int __init asid_isolation_setup(char *str) +{ + asid_isolation_cmdline = 1; + return 1; +} +__setup("asid_isolation", asid_isolation_setup); From patchwork Mon Oct 17 08:12:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfeng Ye X-Patchwork-Id: 3269 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1329148wrs; Mon, 17 Oct 2022 01:17:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4TuJ8vtpb14w9+mmK50F1SV+7sXd70f9ydCUDT4WKwiJF0IIZMaN/ac8uud0DDgtqPYSI0 X-Received: by 2002:a17:902:ce0e:b0:17d:a730:3835 with SMTP id k14-20020a170902ce0e00b0017da7303835mr11204666plg.131.1665994649703; Mon, 17 Oct 2022 01:17:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665994649; cv=none; d=google.com; s=arc-20160816; b=dLW4f93F2srhk3TXdCzNZt+ceDLhkahMqM4Sn+GRScOvb+9x2bs18G61EnxUpm5pgL FPBPYYcM3xbyoLBoGMuWobYCsbggzpSfcLXFxE/16yZJ00XOfl1s0vTt2HI8WerLOayb MD+bTdj9+PDfldKgv7fMNqA66eZhranNMv7854f31mtzOjhe5ViG7g93YnLuKGS3q86Y BuqqyducdPlOS0Aaj7v25mUhmUo/qHrQYsHxb9zh/SWc5vFfdbnCu0Rs/MkaJuJisall +d0UNk7fQ4H6GVnFUqVQM8lmT0c/YtafKMdxDZvc3OpC/Z1bZ8boxkQcEJ1ayeqUPoFI ooNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from; bh=ZDoUrHprh/Gye5YC824UIX5IsNAu7mjmmOSJzmP8zm4=; b=eKJ9J+1mL9zJ7S9rAOIduWv/4TIA3vvc0PDJq3kiW25wm6n5bbpQ8guL3U+VL1+shL zbQlLZ+o7rtE7yjhPb7GJNBlgyYBz4VjFnJ2o6E2KD3LGO1snrDLuSSyL1I1tjzUJxVH EHFsrsMrdzVi0DMaN2tfA07MRe/6FHnOdlredLcjP7pGjbuXFmYtK1gtS4BA3dABmP8N eElYdkjT4UTcnfGS+7+RKTt25dHJ9ZUGbxn1dZU7sRJDpENI8R4rEoem2XU4EQwRpCqo vy4iG/IXvQMidaNhQDsLDI6oBL+idpgomB6g4hhDitHDJccnCZs/xkB1rSFZTprd7+aR LJQQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j3-20020a170903028300b0017a034f7246si13872582plr.560.2022.10.17.01.17.16; Mon, 17 Oct 2022 01:17:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230096AbiJQIOG (ORCPT + 99 others); Mon, 17 Oct 2022 04:14:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230172AbiJQINo (ORCPT ); Mon, 17 Oct 2022 04:13:44 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 416F55C369 for ; Mon, 17 Oct 2022 01:13:40 -0700 (PDT) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4MrV4j0fT1z1P7hZ; Mon, 17 Oct 2022 16:08:53 +0800 (CST) Received: from huawei.com (10.44.134.232) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 17 Oct 2022 16:13:04 +0800 From: y00318929 To: , , , , , Subject: [PATCH 5/5] arm64: mm: Add TLB flush trace on context switch Date: Mon, 17 Oct 2022 16:12:58 +0800 Message-ID: <20221017081258.3678830-6-yeyunfeng@huawei.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221017081258.3678830-1-yeyunfeng@huawei.com> References: <20221017081258.3678830-1-yeyunfeng@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.44.134.232] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746922005887542183?= X-GMAIL-MSGID: =?utf-8?q?1746922005887542183?= From: Yunfeng Ye We do not know how many times the TLB is flushed on context switch. Adding trace_tlb_flush() in check_and_switch_context() may be useful. Signed-off-by: Yunfeng Ye --- arch/arm64/mm/context.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 0ea3e7485ae7..eab470a97620 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -19,6 +19,8 @@ #include #include +#include + struct asid_bitmap { unsigned long *map; unsigned long nr; @@ -60,6 +62,8 @@ static DEFINE_STATIC_KEY_FALSE(asid_isolation_enable); #define ctxid2asid(asid) ((asid) & ~ASID_MASK) #define asid2ctxid(asid, genid) ((asid) | (genid)) +#define TLB_FLUSH_ALL (-1) + /* Get the ASIDBits supported by the current CPU */ static u32 get_cpu_asid_bits(void) { @@ -416,8 +420,10 @@ void check_and_switch_context(struct mm_struct *mm) atomic64_set(&mm->context.id, asid); } - if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) + if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) { local_flush_tlb_all(); + trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL); + } atomic64_set(this_cpu_ptr(&active_asids), asid); raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);