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Subject: [PATCH] RISC-V: Add vzext.vf8 C API tests Date: Mon, 6 Feb 2023 13:08:39 +0800 Message-Id: <20230206050839.214506-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757057034314287081?= X-GMAIL-MSGID: =?utf-8?q?1757057034314287081?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vzext_vf8-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_m-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_m-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_m-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vzext_vf8-1.c | 34 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf8-2.c | 34 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf8-3.c | 34 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf8_m-1.c | 34 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf8_m-2.c | 34 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/vzext_vf8_m-3.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_mu-1.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_mu-2.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_mu-3.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_tu-1.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_tu-2.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_tu-3.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_tum-1.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_tum-2.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_tum-3.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_tumu-1.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_tumu-2.c | 34 +++++++++++++++++++ .../riscv/rvv/base/vzext_vf8_tumu-3.c | 34 +++++++++++++++++++ 18 files changed, 612 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c new file mode 100644 index 00000000000..c0620ec27b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1(op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2(op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4(op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c new file mode 100644 index 00000000000..6a191aef61f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1(op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2(op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4(op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c new file mode 100644 index 00000000000..f29adaf3b0b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1(op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2(op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4(op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c new file mode 100644 index 00000000000..bb35704346f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_m(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_m(mask,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_m(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_m(mask,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_m(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_m(mask,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_m(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c new file mode 100644 index 00000000000..d93cf35f876 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_m(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_m(mask,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_m(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_m(mask,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_m(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_m(mask,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_m(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c new file mode 100644 index 00000000000..4e0be75405b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_m(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_m(mask,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_m(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_m(mask,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_m(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_m(mask,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_m(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c new file mode 100644 index 00000000000..320371062f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_mu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_mu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_mu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c new file mode 100644 index 00000000000..83af580e66f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_mu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_mu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_mu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c new file mode 100644 index 00000000000..44a41981de3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_mu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_mu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_mu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c new file mode 100644 index 00000000000..35bd01227cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_tu(merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_tu(merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_tu(merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c new file mode 100644 index 00000000000..7610fcdcb20 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_tu(merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_tu(merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_tu(merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c new file mode 100644 index 00000000000..705f073874d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_tu(vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_tu(merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_tu(vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_tu(merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_tu(vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_tu(merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_tu(vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c new file mode 100644 index 00000000000..553ea9443b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_tum(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_tum(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_tum(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c new file mode 100644 index 00000000000..8f47c1cb7a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_tum(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_tum(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_tum(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c new file mode 100644 index 00000000000..2c0d0cb10da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_tum(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_tum(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_tum(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c new file mode 100644 index 00000000000..e9341cf0573 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_tumu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_tumu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_tumu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c new file mode 100644 index 00000000000..ac5dd0f55c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_tumu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_tumu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_tumu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c new file mode 100644 index 00000000000..fa6133ec9c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint64m1_t test___riscv_vzext_vf8_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m1_tumu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf8_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m2_tumu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf8_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m4_tumu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf8_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf8_u64m8_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf8\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */