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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2023 13:02:03.5952 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73317ae1-0ecc-45b9-046f-08db05e6d898 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5187 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756815091930907023?= X-GMAIL-MSGID: =?utf-8?q?1756815091930907023?= Tegra234 and Tegra241 devices have QSPI controller that supports TPM devices. Since the controller only supports half duplex, sw wait polling method implemented in tpm_tis_spi does not suffice. Wait polling as per protocol is a hardware feature. Add compatible for Tegra TPM driver with hardware flow control. Signed-off-by: Krishna Yarlagadda --- .../security/tpm/nvidia,tegra-tpm-spi.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.yaml diff --git a/Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.yaml b/Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.yaml new file mode 100644 index 000000000000..dcb78db7355c --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/security/tpm/nvidia,tegra-tpm-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra QSPI TPM driver + +maintainers: + - Thierry Reding + - Jonathan Hunter + +properties: + compatible: + enum: + - nvidia,tegra-tpm-spi + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + qspi1@3250000 { + tpm@0 { + compatible = "nvidia,tegra-tpm-spi"; + reg = <0>; + }; + }; From patchwork Fri Feb 3 13:01:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 52482 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp826392wrn; Fri, 3 Feb 2023 05:05:23 -0800 (PST) X-Google-Smtp-Source: AK7set/jqKu+QIO0BGLza7jaevV1uNKiW6Iqp97m29yFbWs7KrvVs9uHVvUmnXAI12b1CZLqSVB0 X-Received: by 2002:aa7:c44c:0:b0:479:8313:3008 with SMTP id n12-20020aa7c44c000000b0047983133008mr9403790edr.0.1675429523792; Fri, 03 Feb 2023 05:05:23 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675429523; cv=pass; d=google.com; s=arc-20160816; b=VJ3yuqnaXzu5yd+uRG3P3Sp+JEysA511Qik3MyBtLp2bQ7/eIUTi1eEnpxNptFRaTB RWDgYOrDxOX4qBrosZrPyIlrQ+43NMQVI/IHg09LSdRNXMdXJ6c7MDxOokT5mj6clnwK FoF4eaiuFENuDrm7/4sH9uB2yOwbDLaKIY4my9aoBNYGPGnd3V79SnfO8VyWPmO5l7+A s9+zl6q6C/hDBZeeVlPNPqhKHDf0aXcT6443F4kl6oCw/lR7RIU2ruh5f9zewMU1f4kI +3G0StgtZnza2T98um7nSF3joo5MR4L6BTRFKt7znhI44xiYRg/drLICgxq01q/ZGTkq 8d8A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=/HCwdw+VY8n1JR+QE1oTKBbBxFSCXXoMSgE1nTrnikc=; b=ov2Qsq4mQjHrDKZvpLCcdk4xYyN8PmmaTf3iO+eQPJzx3j9YiTyKYg9CRR1z5xgDqb o97amOmJadR4jBiWX3UD2gAX3fvnhgBFcUHgTlcnCaAghxMOgEb5ElJtrIhgdaZCHGsJ O09KxW0mXfP4hY9FfmjMi3uMqetQHVHoleRdcoJxwmWT/PhQ6d307ISVwNu1aBGxgIYA zluvVwdtWrnDiWNAEFD/PrLNGeRUnaiAwQJSmo2KU1BQLIGAN4hSOP63LyUsHdfemLOS U0QnFWSZ8Up2QGzl6KYK97Bye+H1x0RlAtilLYeRM2Tg0YrTP+5Uh3cbfDqB/E5WZshb pLcQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=KrrSsfzP; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Since the controller only supports half duplex, sw wait polling method implemented in tpm_tis_spi does not suffice. Added extending driver to disable sw flow control and send all transfers in single message. Signed-off-by: Krishna Yarlagadda --- drivers/char/tpm/Makefile | 1 + drivers/char/tpm/tpm_tis_spi.h | 1 + drivers/char/tpm/tpm_tis_spi_main.c | 4 +- drivers/char/tpm/tpm_tis_spi_tegra.c | 123 +++++++++++++++++++++++++++ 4 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 drivers/char/tpm/tpm_tis_spi_tegra.c diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile index 0222b1ddb310..445b15493cb3 100644 --- a/drivers/char/tpm/Makefile +++ b/drivers/char/tpm/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_TCG_TIS_SYNQUACER) += tpm_tis_synquacer.o obj-$(CONFIG_TCG_TIS_SPI) += tpm_tis_spi.o tpm_tis_spi-y := tpm_tis_spi_main.o +tpm_tis_spi-y += tpm_tis_spi_tegra.o tpm_tis_spi-$(CONFIG_TCG_TIS_SPI_CR50) += tpm_tis_spi_cr50.o obj-$(CONFIG_TCG_TIS_I2C_CR50) += tpm_tis_i2c_cr50.o diff --git a/drivers/char/tpm/tpm_tis_spi.h b/drivers/char/tpm/tpm_tis_spi.h index d0f66f6f1931..feaea14b428b 100644 --- a/drivers/char/tpm/tpm_tis_spi.h +++ b/drivers/char/tpm/tpm_tis_spi.h @@ -31,6 +31,7 @@ extern int tpm_tis_spi_init(struct spi_device *spi, struct tpm_tis_spi_phy *phy, extern int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len, u8 *in, const u8 *out); +extern int tegra_tpm_spi_probe(struct spi_device *spi); #ifdef CONFIG_TCG_TIS_SPI_CR50 extern int cr50_spi_probe(struct spi_device *spi); #else diff --git a/drivers/char/tpm/tpm_tis_spi_main.c b/drivers/char/tpm/tpm_tis_spi_main.c index a0963a3e92bd..5d4502a4461a 100644 --- a/drivers/char/tpm/tpm_tis_spi_main.c +++ b/drivers/char/tpm/tpm_tis_spi_main.c @@ -198,7 +198,7 @@ static int tpm_tis_spi_driver_probe(struct spi_device *spi) const struct spi_device_id *spi_dev_id = spi_get_device_id(spi); tpm_tis_spi_probe_func probe_func; - probe_func = of_device_get_match_data(&spi->dev); + probe_func = device_get_match_data(&spi->dev); if (!probe_func) { if (spi_dev_id) { probe_func = (tpm_tis_spi_probe_func)spi_dev_id->driver_data; @@ -227,6 +227,7 @@ static const struct spi_device_id tpm_tis_spi_id[] = { { "tpm_tis_spi", (unsigned long)tpm_tis_spi_probe }, { "tpm_tis-spi", (unsigned long)tpm_tis_spi_probe }, { "cr50", (unsigned long)cr50_spi_probe }, + { "tegra-tpm-spi", (unsigned long)tegra_tpm_spi_probe }, {} }; MODULE_DEVICE_TABLE(spi, tpm_tis_spi_id); @@ -236,6 +237,7 @@ static const struct of_device_id of_tis_spi_match[] = { { .compatible = "infineon,slb9670", .data = tpm_tis_spi_probe }, { .compatible = "tcg,tpm_tis-spi", .data = tpm_tis_spi_probe }, { .compatible = "google,cr50", .data = cr50_spi_probe }, + { .compatible = "nvidia,tegra-tpm-spi", .data = tegra_tpm_spi_probe }, {} }; MODULE_DEVICE_TABLE(of, of_tis_spi_match); diff --git a/drivers/char/tpm/tpm_tis_spi_tegra.c b/drivers/char/tpm/tpm_tis_spi_tegra.c new file mode 100644 index 000000000000..23f20684513d --- /dev/null +++ b/drivers/char/tpm/tpm_tis_spi_tegra.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 NVIDIA CORPORATION. + * + * This device driver implements TEGRA QSPI hw wait detection for chips + * + * It is based on tpm_tis_spi driver by Peter Huewe and Christophe Ricard. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "tpm_tis_core.h" +#include "tpm_tis_spi.h" + +#define MAX_SPI_FRAMESIZE 64 + +int tpm_tis_spi_tegra_transfer(struct tpm_tis_data *data, u32 addr, u16 len, + u8 *in, const u8 *out) +{ + struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); + int ret = 0; + struct spi_message m; + struct spi_transfer spi_xfer[3]; + u8 transfer_len; + + spi_bus_lock(phy->spi_device->master); + + while (len) { + transfer_len = min_t(u16, len, MAX_SPI_FRAMESIZE); + + spi_message_init(&m); + phy->iobuf[0] = (in ? 0x80 : 0) | (transfer_len - 1); + phy->iobuf[1] = 0xd4; + phy->iobuf[2] = addr >> 8; + phy->iobuf[3] = addr; + + memset(&spi_xfer, 0, sizeof(spi_xfer)); + + spi_xfer[0].tx_buf = phy->iobuf; + spi_xfer[0].len = 1; + spi_message_add_tail(&spi_xfer[0], &m); + + spi_xfer[1].tx_buf = phy->iobuf + 1; + spi_xfer[1].len = 3; + spi_message_add_tail(&spi_xfer[1], &m); + + if (out) { + spi_xfer[2].tx_buf = &phy->iobuf[4]; + spi_xfer[2].rx_buf = NULL; + memcpy(&phy->iobuf[4], out, transfer_len); + out += transfer_len; + } + if (in) { + spi_xfer[2].tx_buf = NULL; + spi_xfer[2].rx_buf = &phy->iobuf[4]; + } + spi_xfer[2].len = transfer_len; + spi_message_add_tail(&spi_xfer[2], &m); + + reinit_completion(&phy->ready); + ret = spi_sync_locked(phy->spi_device, &m); + if (ret < 0) + goto exit; + + if (in) { + memcpy(in, &phy->iobuf[4], transfer_len); + in += transfer_len; + } + + len -= transfer_len; + } + +exit: + spi_bus_unlock(phy->spi_device->master); + return ret; +} + +static int tpm_tis_spi_tegra_read_bytes(struct tpm_tis_data *data, u32 addr, + u16 len, u8 *result, + enum tpm_tis_io_mode io_mode) +{ + return tpm_tis_spi_tegra_transfer(data, addr, len, result, NULL); +} + +static int tpm_tis_spi_tegra_write_bytes(struct tpm_tis_data *data, u32 addr, + u16 len, const u8 *value, + enum tpm_tis_io_mode io_mode) +{ + return tpm_tis_spi_tegra_transfer(data, addr, len, NULL, value); +} + +static const struct tpm_tis_phy_ops tegra_tpm_spi_phy_ops = { + .read_bytes = tpm_tis_spi_tegra_read_bytes, + .write_bytes = tpm_tis_spi_tegra_write_bytes, +}; + +int tegra_tpm_spi_probe(struct spi_device *dev) +{ + struct tpm_tis_spi_phy *phy; + int irq; + + phy = devm_kzalloc(&dev->dev, sizeof(struct tpm_tis_spi_phy), + GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->flow_control = NULL; + + /* If the SPI device has an IRQ then use that */ + if (dev->irq > 0) + irq = dev->irq; + else + irq = -1; + + init_completion(&phy->ready); + return tpm_tis_spi_init(dev, phy, irq, &tegra_tpm_spi_phy_ops); +} From patchwork Fri Feb 3 13:01:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 52480 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp825443wrn; Fri, 3 Feb 2023 05:04:00 -0800 (PST) X-Google-Smtp-Source: AK7set8U4OatMJaWJKNy5DueapsPlb9+X9IK4kluHfby1SguVJMItwwUNdBpy/NlPp3j5yqqZoOj X-Received: by 2002:a17:907:d609:b0:862:c1d5:ea1b with SMTP id wd9-20020a170907d60900b00862c1d5ea1bmr11079423ejc.8.1675429440125; Fri, 03 Feb 2023 05:04:00 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675429440; cv=pass; d=google.com; s=arc-20160816; b=XdBwqITWk5PFkhBn/BS2sX0RTtvmlBRAY589u2hygoahk2Gq0vrlJ50poLXx2JFrpX 2UM1zMKsTcK4PT+Tz8qCF15FUsqlqk5LM5J0LRwjl0t1x6s1m4enjTl2Q8dsk+pBpIW7 fXfcmYN9Pql6YD7Ir5htrqMwwxhsMa/NY3CpkBZqbwGkdxLlN83PtnXXbAxWoOmNyH9s JkA+Mq60H8MopffKk0cgm/zaHE/bufAo5b9e4rL0lwhZb8PvJ6C7A0ljLZaUfe4GSKQt 2nvFuepra89KqIJUfKF4VeFISpnxO8uqI+tjImJz8UQ5AaqGR0Wqs2lcly8xE9me7+gv wk9A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=aExJLvyqOQDaSH2CBQmqboHZSVYzBuC+9cM/kjEBTHs=; b=A8r0Or76AcCRTWJPGAEFmODGCuMo+jHXtjCJtAD5QfyKpVmuN2ZX2H0VQcuMNHx6uO vxkTbjjx9yEDRhN2j/a5afaaKIUMcjnkJABgwczM9TEnp+TY0nUsDnLjfsr6eE+f+Gmz wsdwzZQmV4dXTk5WKjhmBed7GBD17WR8tu8d517N64+F5D2YwwiF5IgokgggbwOJ7EdN WVbSFfYN9JHvCc/0Tlc9XkXPk3stRf/mr7/GqJeTC+QdyTKTs161qUd9yIhS/pi9JXqH MztZg7y0NHw48jD1mlepPwV7GIXMl2Iav33AwBiWm7jUrmhjBZnr2siwcl4XgNPpGPTC Wq4A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Qp36Qk6c; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Krishna Yarlagadda --- .../bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml index 2c3cada75339..19d2b30cadbf 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml @@ -29,4 +29,10 @@ properties: minimum: 0 maximum: 255 + nvidia,wait-polling: + description: + Enable TPM wait polling feature for QSPI as specified in TCG PC Client + Specific TPM Interface Specification (TIS). + $ref: /schemas/types.yaml#/definitions/flag + additionalProperties: true From patchwork Fri Feb 3 13:01:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 52481 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp826309wrn; Fri, 3 Feb 2023 05:05:16 -0800 (PST) X-Google-Smtp-Source: AK7set8Mb3roBlrmR6qKJFnRFldB5CQdhIQwf85R2Uf8+RJLxg6NKi7otaqiDV64e3ONZq6DnFoM X-Received: by 2002:a17:907:e8d:b0:88d:ba89:1837 with SMTP id ho13-20020a1709070e8d00b0088dba891837mr6588917ejc.8.1675429516651; Fri, 03 Feb 2023 05:05:16 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675429516; cv=pass; d=google.com; s=arc-20160816; b=MnUfvPuCxKxAnSYmJMTer80QDvKgv4j+i+PcOCLX+OLsoye402a7exkmtebfkQO0KP BeImN2kR2zh5Q+ASlDyuxyOHWHj1otZoueQOXIjdiMz3XFspJHTQ7MsqCW9bLRGIBWfr B/QkrxKMgerCNCBImO18IcLb7RETapGwZqKAwchzNyCrmCzgneXBnN8DoOOr+0sCTKZF GVHskOvdyCRIyLYGwtktMyEKTSwn04Ge3EvGDex+Jg+RUF5dW79Ogu+isO9iScZqnGpz yp+RPwgF+3L09JMnDzDu2sLmFmH9oRJ5yOwdtzTnJD25FgHb1zMwWcTDqITXBiGAX/Ft UiDQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=nqWFNUwPKtgLMprxqTkaVOXPw+aYN4kOMzuRnY3qTUs=; b=ecC/sYkxkXTBCBgZVlJwgXiYhsHpsEZlvrhP5euuHco8t3qkSqE2uoamXg5EAxy192 8rO3tnEXzP+ygLcw+NV17D/XXWGrmLEWfZmv/EfPjK77c7N8QhmhPJbN3TfYLQ5ggUHq YtK7pQIzIBUQaMOT/vINqwBB/s77m1VnN4qNZH03iFxg7owQcVSHg8tlgHX3ndZfAyI7 9vdEwSSltwQtnS/ln4znYnY2Hw+xMwrYUk0Jndfn0zZWBD1rPOR1kwBI8XIbQvPbIHJl yNd3Z+w5BKYaEqxtY9gm6/0yF5ofJleDPAgGZ5exuCrub5yfGjfVzzMPkCScDUZz4/3o 1uIA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=BIctkJi7; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2023 13:02:22.2458 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a6423fb-b792-44d7-7b8d-08db05e6e3b3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5145 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756815180733906464?= X-GMAIL-MSGID: =?utf-8?q?1756815180733906464?= Trusted Platform Module defines flow control where slave will drive data line at specified clock cycles. Tegra241 has TPM wait state detections support when using combined sequence transfers. Enabling the feature based on device tree flag. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 9f356612ba7e..ea8a08a3d838 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -142,6 +142,7 @@ #define QSPI_GLOBAL_CONFIG 0X1a4 #define QSPI_CMB_SEQ_EN BIT(0) +#define QSPI_TPM_WAIT_POLL_EN BIT(1) #define QSPI_CMB_SEQ_ADDR 0x1a8 #define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0) @@ -170,6 +171,7 @@ struct tegra_qspi_soc_data { struct tegra_qspi_client_data { int tx_clk_tap_delay; int rx_clk_tap_delay; + bool wait_polling; }; struct tegra_qspi { @@ -934,6 +936,8 @@ static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_devic &cdata->tx_clk_tap_delay); device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay", &cdata->rx_clk_tap_delay); + cdata->wait_polling = + device_property_read_bool(&spi->dev, "nvidia,wait-polling"); return cdata; } @@ -991,6 +995,14 @@ static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi) dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS), tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS)); + dev_dbg(tqspi->dev, "GLOBAL_CFG: 0x%08x\n", + tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG)); + dev_dbg(tqspi->dev, "CMB_CMD: 0x%08x | CMB_CMD_CFG: 0x%08x\n", + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_CMD), + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_CMD_CFG)); + dev_dbg(tqspi->dev, "CMB_ADDR: 0x%08x | CMB_ADDR_CFG: 0x%08x\n", + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_ADDR), + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_ADDR_CFG)); } static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) @@ -1056,6 +1068,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, bool is_first_msg = true; struct spi_transfer *xfer; struct spi_device *spi = msg->spi; + struct tegra_qspi_client_data *cdata = spi->controller_data; u8 transfer_phase = 0; u32 cmd1 = 0, dma_ctl = 0; int ret = 0; @@ -1065,6 +1078,8 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, /* Enable Combined sequence mode */ val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); + if (cdata->wait_polling) + val |= QSPI_TPM_WAIT_POLL_EN; val |= QSPI_CMB_SEQ_EN; tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); /* Process individual transfer list */ @@ -1192,6 +1207,7 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, /* Disable Combined sequence mode */ val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); val &= ~QSPI_CMB_SEQ_EN; + val &= ~QSPI_TPM_WAIT_POLL_EN; tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); list_for_each_entry(transfer, &msg->transfers, transfer_list) { struct spi_transfer *xfer = transfer;