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[37.212.7.39]) by smtp.gmail.com with ESMTPSA id u8-20020a17090657c800b0078c1e174e11sm4645699ejr.136.2022.10.16.08.03.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 08:03:09 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Thomas Bogendoerfer , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 1/4] MIPS: ingenic: add new machine type MACH_JZ4755 Date: Sun, 16 Oct 2022 18:01:06 +0300 Message-Id: <20221016150110.3020451-2-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221016150110.3020451-1-lis8215@gmail.com> References: <20221016150110.3020451-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746856994259221249?= X-GMAIL-MSGID: =?utf-8?q?1746856994259221249?= which is close to jz4725b because it is actually a low price successor of the jz4755. It has the same MIPS32r1 core with Xburst(R) extension MXU version 1 release 2. Signed-off-by: Siarhei Volkau --- arch/mips/ingenic/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig index f595b339a..edd84cf13 100644 --- a/arch/mips/ingenic/Kconfig +++ b/arch/mips/ingenic/Kconfig @@ -4,6 +4,7 @@ config MACH_INGENIC_GENERIC bool select MACH_INGENIC select MACH_JZ4740 + select MACH_JZ4755 select MACH_JZ4725B select MACH_JZ4770 select MACH_JZ4780 @@ -53,6 +54,10 @@ config MACH_JZ4740 bool select SYS_HAS_CPU_MIPS32_R1 +config MACH_JZ4755 + bool + select SYS_HAS_CPU_MIPS32_R1 + config MACH_JZ4770 bool select MIPS_CPU_SCACHE From patchwork Sun Oct 16 15:01:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 3040 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1051407wrs; Sun, 16 Oct 2022 08:03:58 -0700 (PDT) X-Google-Smtp-Source: AMsMyM77VlB79g9FLiZcwcXP3oQ7G0eanUz8mA5f0gpiJfdWbmO7qXTwJ2dWHIgDzuVz0VBYVjfc X-Received: by 2002:a17:902:7c14:b0:17f:6303:f40 with SMTP id x20-20020a1709027c1400b0017f63030f40mr7365227pll.1.1665932637830; Sun, 16 Oct 2022 08:03:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665932637; cv=none; d=google.com; s=arc-20160816; b=Pc09j0gpGTTJkn1/Jb5XXuWjXG0SgAzuYCbQ+luVbSJYqPDZe2o2+Z8fvkcCooZma4 INWHO/TW5kFSxPY0y0pzMB7cumvBrhqygJbZASYhkhyzQe/J5B9M9pgxLrsUuaYpztUR FZquW3kkBZWjoM/3LROlTMDyjOgDsqqerXR8g3IAqUFZqHyS9/3SgFfIYKoyj06C7ajk 80D5bgdEgSngknFkEoSSPiE2Myyp0R8km5z+6Ig/pt3etGFADNxI6+/m07yXd9G/gpId bIncj0aktkFgB1xYeq/rvp3uDIr+QP3fLm1iDzrHHu9Gm+jn+ROe7aDzqOTHsUCVFpMU NKuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=uB/YFZqZEaKiFGlCwO3LrxhNU5OpxJ4tB5tamj6ARsY=; b=DrObDdJEckvngRvY3CeWgWFgPTPfu3Mu4VYjPPf8018EqDzordAgop/sSp0m8Ew5TK vFqHJDgFObg22AE86NhaUZ1KIU4rH5+FGr9SkllSvtEYv546Q5kNvx92eW6fn+sfwgIl zpBPA2WZFZR1G7z/ZC4iaWiC/KfdeTIJfTte7BgE8fUIhyvnIjN9BtOAwb7qSCuV0XYU 7LlijnKRgmTtvZyYmmFeJ3Q6iEl3xGXxVlQ0+8E2/ZUVGpOa3bijIfMBaGZapxj5S7CB St2i/WPKRSXUd6x8zlWnfDcFhWtxs61m1I7BzAWhtDlUfi184ULjcJ/pWv+19+X6JpIw f3uA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=XlKCTvyx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[37.212.7.39]) by smtp.gmail.com with ESMTPSA id u8-20020a17090657c800b0078c1e174e11sm4645699ejr.136.2022.10.16.08.03.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 08:03:11 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Thomas Bogendoerfer , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 2/4] dt-bindings: ingenic: Add support for the JZ4755 CGU Date: Sun, 16 Oct 2022 18:01:07 +0300 Message-Id: <20221016150110.3020451-3-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221016150110.3020451-1-lis8215@gmail.com> References: <20221016150110.3020451-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746856981775836095?= X-GMAIL-MSGID: =?utf-8?q?1746856981775836095?= Acked-by: Krzysztof Kozlowski Signed-off-by: Siarhei Volkau --- Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index aa1df03ef..df256ebcd 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -22,6 +22,7 @@ select: enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu @@ -51,6 +52,7 @@ properties: - enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu From patchwork Sun Oct 16 15:01:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 3042 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1051600wrs; Sun, 16 Oct 2022 08:04:17 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7qRcbP09LDOrHrMLJpVTYyYXya4kuV4G4m7tjag8S9o2F/5S5uVWzH9QR+R6/HtbknAnLi X-Received: by 2002:a17:902:e846:b0:180:c732:1e53 with SMTP id t6-20020a170902e84600b00180c7321e53mr7698597plg.110.1665932657472; Sun, 16 Oct 2022 08:04:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665932657; cv=none; d=google.com; s=arc-20160816; b=iFoyivpdTpjFbpfs1z3RUkrkuzZRzrYyy5am1aOUbq+PUOhbM5FGygqzxNQFHc96Xr Q/KJfcS0IRAT994HQi24zJ8NiqB7onFwAXZQ+zkU0gEktiEUyJyLlsM9y3oDqGCEFGbs 8fa7HJ7m0sypLC45lIQegY0nHY5zlMnbxUE952CbUGRQvUTz8JAA8u02o86teRK4c1Nf odrFxY68AuPuNlCF29JAxjrpKq6PmGzssKmXKE/vG6Kv0lFNPBTBDejWvewH7dbH2bak /MrzsMJPlu8HCV5uhh4aOuhpGAY2QwSotO+KlXAk5YeBKvTLg6LUP6C4llF/hxEZgr0c TbAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=B9Wg20rVnZ4v1joif76gIBjpt9SJeqrGz8H44eRdP3w=; b=F6CadBKnvnXcFrIPOLYmHgNPZPo8B3u/E1MCer/zgl5z8OdV3WeBkHQ5Scdf9nGh8v kp8VBftuFBc36uR0oKdMD7/w9s1vPt733lfG0RevRo09WP6FHYuLpdRTeUyEnaFOkyNj SXXb9FP0XTt8v+Lt2HiVxlbtwAstFfK+2BjHehNpyqByS5x+aCTh2a5mgR7jFHpaA3DV SQtS5oowu+qAIeW5tYA/68Y+aIdKQXjhrxhkakna6jP9pxZbKNzUUpGm1adgNIf5U9Ba Rn6g2ACYZXhZUxmic3fmNt8EhFbdRHOSnAsjsYes78j2enpv73lF5NHBs3ACCrIt7Bkg ec5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=A50Ffwth; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[37.212.7.39]) by smtp.gmail.com with ESMTPSA id u8-20020a17090657c800b0078c1e174e11sm4645699ejr.136.2022.10.16.08.03.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 08:03:13 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Thomas Bogendoerfer , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 3/4] dt-bindings: clock: Add Ingenic JZ4755 CGU header Date: Sun, 16 Oct 2022 18:01:08 +0300 Message-Id: <20221016150110.3020451-4-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221016150110.3020451-1-lis8215@gmail.com> References: <20221016150110.3020451-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746857002247204363?= X-GMAIL-MSGID: =?utf-8?q?1746857002247204363?= This will be used from the devicetree bindings to specify the clocks that should be obtained from the jz4755-cgu driver. Signed-off-by: Siarhei Volkau --- .../dt-bindings/clock/ingenic,jz4755-cgu.h | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h diff --git a/include/dt-bindings/clock/ingenic,jz4755-cgu.h b/include/dt-bindings/clock/ingenic,jz4755-cgu.h new file mode 100644 index 000000000..1ac13d61b --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4755-cgu.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +/* + * This header provides clock numbers for the ingenic,jz4755-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ + +#define JZ4755_CLK_EXT 0 +#define JZ4755_CLK_OSC32K 1 +#define JZ4755_CLK_PLL 2 +#define JZ4755_CLK_PLL_HALF 3 +#define JZ4755_CLK_EXT_HALF 4 +#define JZ4755_CLK_CCLK 5 +#define JZ4755_CLK_H0CLK 6 +#define JZ4755_CLK_PCLK 7 +#define JZ4755_CLK_MCLK 8 +#define JZ4755_CLK_H1CLK 9 +#define JZ4755_CLK_UDC 10 +#define JZ4755_CLK_LCD 11 +#define JZ4755_CLK_UART0 12 +#define JZ4755_CLK_UART1 13 +#define JZ4755_CLK_UART2 14 +#define JZ4755_CLK_DMA 15 +#define JZ4755_CLK_MMC 16 +#define JZ4755_CLK_MMC0 17 +#define JZ4755_CLK_MMC1 18 +#define JZ4755_CLK_EXT512 19 +#define JZ4755_CLK_RTC 20 +#define JZ4755_CLK_UDC_PHY 21 +#define JZ4755_CLK_I2S 22 +#define JZ4755_CLK_SPI 23 +#define JZ4755_CLK_AIC 24 +#define JZ4755_CLK_ADC 25 +#define JZ4755_CLK_TCU 26 +#define JZ4755_CLK_BCH 27 +#define JZ4755_CLK_I2C 28 +#define JZ4755_CLK_TVE 29 +#define JZ4755_CLK_CIM 30 +#define JZ4755_CLK_AUX_CPU 31 +#define JZ4755_CLK_AHB1 32 +#define JZ4755_CLK_IDCT 33 +#define JZ4755_CLK_DB 34 +#define JZ4755_CLK_ME 35 +#define JZ4755_CLK_MC 36 +#define JZ4755_CLK_TSSI 37 +#define JZ4755_CLK_IPU 38 + +#endif /* __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ */ From patchwork Sun Oct 16 15:01:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 3044 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp1051917wrs; Sun, 16 Oct 2022 08:05:01 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4kg/ajBQNOo3s4mHQkinkJbrISE8o64ruD9mFWts89Yo+0SsN7HvVPxf00YCxV807oifIN X-Received: by 2002:a17:902:aa84:b0:185:480a:85b6 with SMTP id d4-20020a170902aa8400b00185480a85b6mr7529410plr.170.1665932701132; Sun, 16 Oct 2022 08:05:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665932701; cv=none; d=google.com; s=arc-20160816; b=nMbv9CSCl8TSlLTJrXsJCvwESE6sqHZWAnif2yfjBDwD5WyilKc18mj8rptszs/Ogl 0THsimwghE0CA2iLygLmVR1PKDsnPPmJ5Y+kEtPhWt6Uaax6M0KC3iFGuvQ8uP7y9fD5 xsQdUW8OA/8j7PNzK6jExvpfxF6S6WjhBsx8+VN6JGEhf6Haq7PHr3pxz7fXIcV/7T62 ruxw8r0q3zyRmRBe52pP2j99WA41o5e8/Px4pFU4W9EVktMKBfVcqp5/Qnj3/p6PAXDw QMw9uOZif1K7Fj41aAmZTN9wZ+rny6w3nQ5Wso8XKO8RgiSi7wDBsuididhRsve/ul5S Lrgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=oicZhaFyYQwyfEJAZw8xjpjgeEJyH48EiK4Wz1kX8mo=; b=braJ8gwgXn7dHxv2WpnF3AnUn8ONGLZmz5kwa0WS4GhAw4Qp6dkMJEK8cfUT98rWgE 6JSCGOUiI3ocnK894ucLdWh7rKc2ivkguFoJnGPCHAokxjaJ5zBkiFDn+Ur5Rnq9xXsM 0sN3yGdIGFj7dkUPi7FaW+LsKadbI4XdGLKUxp/ZmKASQCGaGrUMVmKXalyliJLsjIC9 rzxq6fexEZYJIloFRhdgxNs3L/MsIdn1f3+5tdV/gnZDaaAvaxroNs8Qjd6i5oN+4rxg 4pPvx0u1q0hIa8lKWikqYMXz7ZF48v4YpTK+3MLWQG/YAgIPkKwYYhMEzXRjMgm9nMBR ggXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=gE5zkGQC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[37.212.7.39]) by smtp.gmail.com with ESMTPSA id u8-20020a17090657c800b0078c1e174e11sm4645699ejr.136.2022.10.16.08.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 08:03:15 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Thomas Bogendoerfer , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 4/4] clk: Add Ingenic JZ4755 CGU driver Date: Sun, 16 Oct 2022 18:01:09 +0300 Message-Id: <20221016150110.3020451-5-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221016150110.3020451-1-lis8215@gmail.com> References: <20221016150110.3020451-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746857047825303274?= X-GMAIL-MSGID: =?utf-8?q?1746857047825303274?= Add support for the clocks provided by the CGU in the Ingenic JZ4755 SoC. Signed-off-by: Siarhei Volkau --- drivers/clk/ingenic/Kconfig | 10 + drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/jz4755-cgu.c | 350 +++++++++++++++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 drivers/clk/ingenic/jz4755-cgu.c diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index 898f1bc47..f80ac4f29 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -15,6 +15,16 @@ config INGENIC_CGU_JZ4740 If building for a JZ4740 SoC, you want to say Y here. +config INGENIC_CGU_JZ4755 + bool "Ingenic JZ4755 CGU driver" + default MACH_JZ4755 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4755 + and compatible SoCs. + + If building for a JZ4755 SoC, you want to say Y here. + config INGENIC_CGU_JZ4725B bool "Ingenic JZ4725B CGU driver" default MACH_JZ4725B diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 9edfaf461..81d8e23c2 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c new file mode 100644 index 000000000..16728546a --- /dev/null +++ b/drivers/clk/ingenic/jz4755-cgu.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Ingenic JZ4755 SoC CGU driver + * Heavily based on JZ4725b CGU driver + * + * Copyright (C) 2022 Siarhei Volkau + * Author: Siarhei Volkau + */ + +#include +#include +#include + +#include + +#include "cgu.h" +#include "pm.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_LCR 0x04 +#define CGU_REG_CPPCR 0x10 +#define CGU_REG_CLKGR 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSCCDR 0x68 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7C + +/* bits within the LCR register */ +#define LCR_SLEEP BIT(0) + +static struct ingenic_cgu *cgu; + +static const s8 pll_od_encoding[4] = { + 0x0, 0x1, -1, 0x3, +}; + +static const u8 jz4755_cgu_cpccr_div_table[] = { + 1, 2, 3, 4, 6, 8, +}; + +static const u8 jz4755_cgu_pll_half_div_table[] = { + 2, 1, +}; + +static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = { + + /* External clocks */ + + [JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT }, + [JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, + + [JZ4755_CLK_PLL] = { + "pll", CGU_CLK_PLL, + .parents = { JZ4755_CLK_EXT, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_CPPCR, + .rate_multiplier = 1, + .m_shift = 23, + .m_bits = 9, + .m_offset = 2, + .n_shift = 18, + .n_bits = 5, + .n_offset = 2, + .od_shift = 16, + .od_bits = 2, + .od_max = 4, + .od_encoding = pll_od_encoding, + .stable_bit = 10, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 9, + .enable_bit = 8, + }, + }, + + /* Muxes & dividers */ + + [JZ4755_CLK_PLL_HALF] = { + "pll half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, + jz4755_cgu_pll_half_div_table, + }, + }, + + [JZ4755_CLK_EXT_HALF] = { + "ext half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0, + NULL, + }, + }, + + [JZ4755_CLK_CCLK] = { + "cclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H0CLK] = { + "hclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_PCLK] = { + "pclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_MCLK] = { + "mclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H1CLK] = { + "h1clk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_UDC] = { + "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 }, + .mux = { CGU_REG_CPCCR, 29, 1 }, + .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 10 }, + }, + + [JZ4755_CLK_LCD] = { + "lcd", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 9 }, + }, + + [JZ4755_CLK_MMC] = { + "mmc", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, + }, + + [JZ4755_CLK_I2S] = { + "i2s", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 }, + .mux = { CGU_REG_CPCCR, 31, 1 }, + .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, + }, + + [JZ4755_CLK_SPI] = { + "spi", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 4 }, + }, + + [JZ4755_CLK_TVE] = { + "tve", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, -1, -1 }, + .mux = { CGU_REG_LPCDR, 31, 1 }, + .gate = { CGU_REG_CLKGR, 18 }, + }, + + [JZ4755_CLK_RTC] = { + "rtc", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, -1, -1 }, + .mux = { CGU_REG_OPCR, 2, 1}, + .gate = { CGU_REG_CLKGR, 2 }, + }, + + [JZ4755_CLK_CIM] = { + "cim", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 8 }, + }, + + /* Gate-only clocks */ + + [JZ4755_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 0 }, + }, + + [JZ4755_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 14 }, + }, + + [JZ4755_CLK_UART2] = { + "uart2", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 15 }, + }, + + [JZ4755_CLK_ADC] = { + "adc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 7 }, + }, + + [JZ4755_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { JZ4755_CLK_I2S, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 5 }, + }, + + [JZ4755_CLK_I2C] = { + "i2c", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 3 }, + }, + + [JZ4755_CLK_BCH] = { + "bch", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MCLK/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + + [JZ4755_CLK_TCU] = { + "tcu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 1 }, + }, + + [JZ4755_CLK_DMA] = { + "dma", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 12 }, + }, + + [JZ4755_CLK_MMC0] = { + "mmc0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 6 }, + }, + + [JZ4755_CLK_MMC1] = { + "mmc1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 16 }, + }, + + [JZ4755_CLK_AUX_CPU] = { + "aux_cpu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 24 }, + }, + + [JZ4755_CLK_AHB1] = { + "ahb1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 23 }, + }, + + [JZ4755_CLK_IDCT] = { + "idct", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 22 }, + }, + + [JZ4755_CLK_DB] = { + "db", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 21 }, + }, + + [JZ4755_CLK_ME] = { + "me", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 20 }, + }, + + [JZ4755_CLK_MC] = { + "mc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 19 }, + }, + + [JZ4755_CLK_TSSI] = { + "tssi", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 17 }, + }, + + [JZ4755_CLK_IPU] = { + "ipu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 13 }, + }, + + [JZ4755_CLK_EXT512] = { + "ext/512", CGU_CLK_FIXDIV, + .parents = { JZ4755_CLK_EXT }, + + /* JZ4725b doc calls it EXT512, but it seems to be /256... + * Not sure if it applied to JZ4755 too, and which actual + * source is used EXT or EXT_HALF + */ + .fixdiv = { 256 }, + }, + + [JZ4755_CLK_UDC_PHY] = { + "udc_phy", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_OPCR, 6, true }, + }, +}; + +static void __init jz4755_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(jz4755_cgu_clocks, + ARRAY_SIZE(jz4755_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + + ingenic_cgu_register_syscore_ops(cgu); +} +CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init);