From patchwork Tue Jan 31 22:20:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 51054 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp63993wrn; Tue, 31 Jan 2023 14:21:52 -0800 (PST) X-Google-Smtp-Source: AK7set/Q1I+dtpt+vSPN4QbYanZw6X1hD4942Ti9lismFKSM1+qF7vHnOGSdsooZbuJjTwWxswy0 X-Received: by 2002:a05:6402:5192:b0:499:376e:6b35 with SMTP id q18-20020a056402519200b00499376e6b35mr476993edd.25.1675203712619; Tue, 31 Jan 2023 14:21:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675203712; cv=none; d=google.com; s=arc-20160816; b=b8QEH4MFyf9sl2SQ9wbA/WtYpd/didEKQRPAPdgMonjx/7FGUOGia4n3pSgzAxWfzY L61Y1GyYtGE8G21slSv8boUEwXbRoqLw4aQqQM4KvExbxO/2qY5sEq5N+oddIwiN11z+ XvgnUGWT/KPVBppH8W8fGyFxZIZO1y165lbPJCnwX4uOMusD1gH7VPx8HcvzY8Yk65x+ uLKTv0vT2GbLHNqTgzh0I6u1EoFj52T/OVe/qjsVcv0Y4iyiKQ0HGEu605qzVXGTMIdz WV28Rs/qXjUPAIwO3ADqw/XJukxFVtqsP627P0c8tXQOgMYttENK2QApnUDD1rkCXOW2 u5JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=rtN/4KxE7qoXcad5vITmD7BhsxmY7CmIMOwHhIhaFa0=; b=wjVR+oox/wPmaWTb1QuemY4j2XpjAF3wa/CG2WGsqCCgB6L24uDz/E67Nj8SnddLf5 +vXh1oJvFuJG12y+Jo6+FyEfnWSpUTM++gmkqe/Up7OqbRiJlW2FzIq9AIReiz92OWsk IZ00RMVgQhH5noQ8DFOcZ544amWXzgSWqHOOwqWAcR8ws+4/5q44tapI5WP4KJIvoQBZ FfKKu1reLYeLrnbodl7nQzTK80yZFlcp7ROhoqk6XwhO1pXodl9UZBWGcXJBpE7kSoKr d/8cTEcqr0PW6kzhoEdiBMdWcXoQMpxP/yW0kX3DoCrmfGUv+M72AnbixMIwGHbXq2vy D/fA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id x15-20020aa7d38f000000b0048ec063ea63si20922854edq.396.2023.01.31.14.21.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 14:21:52 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E388D3858028 for ; Tue, 31 Jan 2023 22:21:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by sourceware.org (Postfix) with ESMTPS id 4A1183858D33 for ; Tue, 31 Jan 2023 22:21:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4A1183858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp89t1675203659tzq9fqmg Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 01 Feb 2023 06:20:58 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: q+yjhizk/eJ0TuQrkiNLomH7uqee4/PKaE4oBmE2+5HG5mnysBjmoT+T5Ecw1 1uVkr/EW2H+4tOnlKxjVsXVc8WTnbFUhfs3T+goLNQbFTwe7GbBSnjYBpqMNe3Jox1PlB6O GmJVLa6g9ZDZK1IQne4+QD8YgmCUZBzHPcAL1vUcKGoDhLk4u6bD1TvqOpX6ltsGuzC1V70 PDcrzC1oglAO9EXa3GqIeBZaULr9f/f3P2yHGt1pG4gXDTcanV4tIQXjJqRmk4ymHoKcXZ2 A8gOtAlNbKvUH3DyEmnF7I6/5nGze6bWHJhIjNv7e0HKhyARi9j+y6ExN3d+gwuMijqBwRl NVA2xDHre2GN3bTVakJe0SCcmEAJRhQEn9/PakoDqMyLwvl9MI= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vsll.vx C++ API tests Date: Wed, 1 Feb 2023 06:20:56 +0800 Message-Id: <20230131222056.25127-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756577941757433493?= X-GMAIL-MSGID: =?utf-8?q?1756578408334414981?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vsll_vx-1.C: New test. * g++.target/riscv/rvv/base/vsll_vx-2.C: New test. * g++.target/riscv/rvv/base/vsll_vx-3.C: New test. * g++.target/riscv/rvv/base/vsll_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vsll_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vsll_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vsll_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vsll_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vsll_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vsll_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vsll_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vsll_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vsll_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vsll_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vsll_vx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vsll_vx-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsll_vx-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsll_vx-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsll_vx_mu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vsll_vx_mu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vsll_vx_mu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vsll_vx_tu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vsll_vx_tu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vsll_vx_tu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vsll_vx_tum-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vsll_vx_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vsll_vx_tum-3.C | 292 +++++++++ .../riscv/rvv/base/vsll_vx_tumu-1.C | 292 +++++++++ .../riscv/rvv/base/vsll_vx_tumu-2.C | 292 +++++++++ .../riscv/rvv/base/vsll_vx_tumu-3.C | 292 +++++++++ 15 files changed, 5238 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-1.C new file mode 100644 index 00000000000..ecd0e8798cc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll(vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsll(vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsll(vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint8m1_t test___riscv_vsll(vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint8m2_t test___riscv_vsll(vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint8m4_t test___riscv_vsll(vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint8m8_t test___riscv_vsll(vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsll(vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsll(vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint16m1_t test___riscv_vsll(vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint16m2_t test___riscv_vsll(vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint16m4_t test___riscv_vsll(vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint16m8_t test___riscv_vsll(vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsll(vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint32m1_t test___riscv_vsll(vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint32m2_t test___riscv_vsll(vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint32m4_t test___riscv_vsll(vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint32m8_t test___riscv_vsll(vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint64m1_t test___riscv_vsll(vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint64m2_t test___riscv_vsll(vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint64m4_t test___riscv_vsll(vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint64m8_t test___riscv_vsll(vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vsll(vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsll(vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsll(vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsll(vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsll(vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsll(vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsll(vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsll(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsll(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsll(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsll(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsll(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsll(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsll(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsll(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsll(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsll(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsll(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsll(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsll(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsll(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsll(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,vl); +} + + +vint8mf8_t test___riscv_vsll(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsll(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsll(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsll(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsll(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsll(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsll(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsll(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsll(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsll(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsll(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsll(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsll(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsll(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsll(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsll(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsll(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsll(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsll(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsll(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsll(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsll(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vsll(vbool64_t mask,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsll(vbool32_t mask,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsll(vbool16_t mask,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsll(vbool8_t mask,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsll(vbool4_t mask,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsll(vbool2_t mask,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsll(vbool1_t mask,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsll(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsll(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsll(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsll(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsll(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsll(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsll(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsll(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsll(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsll(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsll(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsll(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsll(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsll(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsll(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-2.C new file mode 100644 index 00000000000..deeac7d25f1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll(vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint8mf4_t test___riscv_vsll(vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint8mf2_t test___riscv_vsll(vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint8m1_t test___riscv_vsll(vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint8m2_t test___riscv_vsll(vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint8m4_t test___riscv_vsll(vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint8m8_t test___riscv_vsll(vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint16mf4_t test___riscv_vsll(vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint16mf2_t test___riscv_vsll(vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint16m1_t test___riscv_vsll(vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint16m2_t test___riscv_vsll(vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint16m4_t test___riscv_vsll(vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint16m8_t test___riscv_vsll(vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint32mf2_t test___riscv_vsll(vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint32m1_t test___riscv_vsll(vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint32m2_t test___riscv_vsll(vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint32m4_t test___riscv_vsll(vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint32m8_t test___riscv_vsll(vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint64m1_t test___riscv_vsll(vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint64m2_t test___riscv_vsll(vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint64m4_t test___riscv_vsll(vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint64m8_t test___riscv_vsll(vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint8mf8_t test___riscv_vsll(vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsll(vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsll(vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint8m1_t test___riscv_vsll(vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint8m2_t test___riscv_vsll(vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint8m4_t test___riscv_vsll(vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint8m8_t test___riscv_vsll(vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsll(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsll(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint16m1_t test___riscv_vsll(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint16m2_t test___riscv_vsll(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint16m4_t test___riscv_vsll(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint16m8_t test___riscv_vsll(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsll(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint32m1_t test___riscv_vsll(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint32m2_t test___riscv_vsll(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint32m4_t test___riscv_vsll(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint32m8_t test___riscv_vsll(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint64m1_t test___riscv_vsll(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint64m2_t test___riscv_vsll(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint64m4_t test___riscv_vsll(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vuint64m8_t test___riscv_vsll(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,31); +} + + +vint8mf8_t test___riscv_vsll(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsll(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsll(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint8m1_t test___riscv_vsll(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint8m2_t test___riscv_vsll(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint8m4_t test___riscv_vsll(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint8m8_t test___riscv_vsll(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsll(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsll(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint16m1_t test___riscv_vsll(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint16m2_t test___riscv_vsll(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint16m4_t test___riscv_vsll(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint16m8_t test___riscv_vsll(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsll(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint32m1_t test___riscv_vsll(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint32m2_t test___riscv_vsll(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint32m4_t test___riscv_vsll(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint32m8_t test___riscv_vsll(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint64m1_t test___riscv_vsll(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint64m2_t test___riscv_vsll(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint64m4_t test___riscv_vsll(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vint64m8_t test___riscv_vsll(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint8mf8_t test___riscv_vsll(vbool64_t mask,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsll(vbool32_t mask,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsll(vbool16_t mask,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsll(vbool8_t mask,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsll(vbool4_t mask,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsll(vbool2_t mask,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsll(vbool1_t mask,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsll(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsll(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsll(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsll(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsll(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsll(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsll(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsll(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsll(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsll(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsll(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsll(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsll(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsll(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsll(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-3.C new file mode 100644 index 00000000000..29268cf0598 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll(vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint8mf4_t test___riscv_vsll(vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint8mf2_t test___riscv_vsll(vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint8m1_t test___riscv_vsll(vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint8m2_t test___riscv_vsll(vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint8m4_t test___riscv_vsll(vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint8m8_t test___riscv_vsll(vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint16mf4_t test___riscv_vsll(vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint16mf2_t test___riscv_vsll(vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint16m1_t test___riscv_vsll(vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint16m2_t test___riscv_vsll(vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint16m4_t test___riscv_vsll(vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint16m8_t test___riscv_vsll(vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint32mf2_t test___riscv_vsll(vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint32m1_t test___riscv_vsll(vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint32m2_t test___riscv_vsll(vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint32m4_t test___riscv_vsll(vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint32m8_t test___riscv_vsll(vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint64m1_t test___riscv_vsll(vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint64m2_t test___riscv_vsll(vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint64m4_t test___riscv_vsll(vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint64m8_t test___riscv_vsll(vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint8mf8_t test___riscv_vsll(vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsll(vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsll(vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint8m1_t test___riscv_vsll(vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint8m2_t test___riscv_vsll(vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint8m4_t test___riscv_vsll(vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint8m8_t test___riscv_vsll(vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsll(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsll(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint16m1_t test___riscv_vsll(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint16m2_t test___riscv_vsll(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint16m4_t test___riscv_vsll(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint16m8_t test___riscv_vsll(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsll(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint32m1_t test___riscv_vsll(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint32m2_t test___riscv_vsll(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint32m4_t test___riscv_vsll(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint32m8_t test___riscv_vsll(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint64m1_t test___riscv_vsll(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint64m2_t test___riscv_vsll(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint64m4_t test___riscv_vsll(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vuint64m8_t test___riscv_vsll(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(op1,shift,32); +} + + +vint8mf8_t test___riscv_vsll(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsll(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsll(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint8m1_t test___riscv_vsll(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint8m2_t test___riscv_vsll(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint8m4_t test___riscv_vsll(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint8m8_t test___riscv_vsll(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsll(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsll(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint16m1_t test___riscv_vsll(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint16m2_t test___riscv_vsll(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint16m4_t test___riscv_vsll(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint16m8_t test___riscv_vsll(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsll(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint32m1_t test___riscv_vsll(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint32m2_t test___riscv_vsll(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint32m4_t test___riscv_vsll(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint32m8_t test___riscv_vsll(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint64m1_t test___riscv_vsll(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint64m2_t test___riscv_vsll(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint64m4_t test___riscv_vsll(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vint64m8_t test___riscv_vsll(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint8mf8_t test___riscv_vsll(vbool64_t mask,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsll(vbool32_t mask,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsll(vbool16_t mask,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsll(vbool8_t mask,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsll(vbool4_t mask,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsll(vbool2_t mask,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsll(vbool1_t mask,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsll(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsll(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsll(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsll(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsll(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsll(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsll(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsll(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsll(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsll(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsll(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsll(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsll(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsll(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsll(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-1.C new file mode 100644 index 00000000000..d905629e4a2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsll_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsll_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsll_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsll_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsll_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsll_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsll_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsll_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsll_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsll_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsll_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsll_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsll_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsll_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsll_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsll_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsll_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsll_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsll_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsll_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsll_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsll_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsll_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsll_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsll_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsll_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsll_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsll_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsll_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsll_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsll_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsll_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-2.C new file mode 100644 index 00000000000..3e1f67424c9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vsll_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vsll_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vsll_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint8m8_t test___riscv_vsll_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vsll_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vsll_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vsll_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint16m8_t test___riscv_vsll_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vsll_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vsll_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vsll_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint32m8_t test___riscv_vsll_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint64m1_t test___riscv_vsll_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint64m2_t test___riscv_vsll_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint64m4_t test___riscv_vsll_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vint64m8_t test___riscv_vsll_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsll_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsll_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsll_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsll_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsll_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsll_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsll_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsll_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsll_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsll_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsll_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsll_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsll_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsll_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsll_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsll_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-3.C new file mode 100644 index 00000000000..1ec760092f2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vsll_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vsll_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vsll_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint8m8_t test___riscv_vsll_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vsll_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vsll_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vsll_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint16m8_t test___riscv_vsll_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vsll_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vsll_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vsll_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint32m8_t test___riscv_vsll_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint64m1_t test___riscv_vsll_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint64m2_t test___riscv_vsll_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint64m4_t test___riscv_vsll_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vint64m8_t test___riscv_vsll_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsll_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsll_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsll_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsll_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsll_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsll_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsll_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsll_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsll_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsll_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsll_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsll_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsll_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsll_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsll_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsll_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-1.C new file mode 100644 index 00000000000..633e34baf0b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsll_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsll_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsll_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsll_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsll_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsll_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsll_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsll_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsll_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsll_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsll_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsll_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsll_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsll_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsll_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsll_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsll_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsll_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsll_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsll_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsll_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vsll_tu(vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsll_tu(vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsll_tu(vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsll_tu(vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsll_tu(vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsll_tu(vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsll_tu(vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsll_tu(vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsll_tu(vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsll_tu(vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsll_tu(vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsll_tu(vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsll_tu(vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsll_tu(vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsll_tu(vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsll_tu(vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsll_tu(vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsll_tu(vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsll_tu(vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsll_tu(vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsll_tu(vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsll_tu(vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-2.C new file mode 100644 index 00000000000..5300ff01abd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsll_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsll_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vsll_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vsll_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vsll_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint8m8_t test___riscv_vsll_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsll_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsll_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vsll_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vsll_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vsll_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint16m8_t test___riscv_vsll_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsll_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vsll_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vsll_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vsll_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint32m8_t test___riscv_vsll_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint64m1_t test___riscv_vsll_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint64m2_t test___riscv_vsll_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint64m4_t test___riscv_vsll_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vint64m8_t test___riscv_vsll_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint8mf8_t test___riscv_vsll_tu(vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsll_tu(vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsll_tu(vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsll_tu(vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsll_tu(vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsll_tu(vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsll_tu(vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsll_tu(vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsll_tu(vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsll_tu(vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsll_tu(vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsll_tu(vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsll_tu(vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsll_tu(vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsll_tu(vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsll_tu(vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsll_tu(vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsll_tu(vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsll_tu(vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsll_tu(vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsll_tu(vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsll_tu(vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-3.C new file mode 100644 index 00000000000..f267443b9c6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsll_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsll_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vsll_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vsll_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vsll_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint8m8_t test___riscv_vsll_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsll_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsll_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vsll_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vsll_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vsll_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint16m8_t test___riscv_vsll_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsll_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vsll_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vsll_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vsll_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint32m8_t test___riscv_vsll_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint64m1_t test___riscv_vsll_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint64m2_t test___riscv_vsll_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint64m4_t test___riscv_vsll_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vint64m8_t test___riscv_vsll_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint8mf8_t test___riscv_vsll_tu(vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsll_tu(vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsll_tu(vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsll_tu(vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsll_tu(vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsll_tu(vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsll_tu(vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsll_tu(vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsll_tu(vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsll_tu(vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsll_tu(vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsll_tu(vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsll_tu(vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsll_tu(vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsll_tu(vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsll_tu(vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsll_tu(vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsll_tu(vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsll_tu(vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsll_tu(vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsll_tu(vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsll_tu(vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-1.C new file mode 100644 index 00000000000..7143ae62ae5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsll_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsll_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsll_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsll_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsll_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsll_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsll_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsll_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsll_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsll_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsll_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsll_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsll_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsll_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsll_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsll_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsll_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsll_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsll_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsll_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsll_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsll_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsll_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsll_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsll_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsll_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsll_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsll_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsll_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsll_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsll_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsll_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-2.C new file mode 100644 index 00000000000..407425e7698 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vsll_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vsll_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vsll_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint8m8_t test___riscv_vsll_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vsll_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vsll_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vsll_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint16m8_t test___riscv_vsll_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vsll_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vsll_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vsll_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint32m8_t test___riscv_vsll_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint64m1_t test___riscv_vsll_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint64m2_t test___riscv_vsll_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint64m4_t test___riscv_vsll_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vint64m8_t test___riscv_vsll_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsll_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsll_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsll_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsll_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsll_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsll_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsll_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsll_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsll_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsll_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsll_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsll_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsll_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsll_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsll_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsll_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-3.C new file mode 100644 index 00000000000..4311a6be059 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vsll_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vsll_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vsll_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint8m8_t test___riscv_vsll_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vsll_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vsll_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vsll_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint16m8_t test___riscv_vsll_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vsll_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vsll_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vsll_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint32m8_t test___riscv_vsll_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint64m1_t test___riscv_vsll_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint64m2_t test___riscv_vsll_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint64m4_t test___riscv_vsll_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vint64m8_t test___riscv_vsll_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsll_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsll_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsll_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsll_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsll_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsll_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsll_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsll_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsll_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsll_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsll_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsll_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsll_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsll_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsll_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsll_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-1.C new file mode 100644 index 00000000000..aa6786082dc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-2.C new file mode 100644 index 00000000000..6334da4800a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-3.C new file mode 100644 index 00000000000..456cfdc124f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsll_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsll\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */