From patchwork Tue Jan 31 21:05:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 51038 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp33353wrn; Tue, 31 Jan 2023 13:07:02 -0800 (PST) X-Google-Smtp-Source: AK7set//F1Afa0513xcKYamSp/Qxb6a3kEr7YCTgxtNsAsQwOKW6f43OiJfwVBk8U2j26fM8uDsD X-Received: by 2002:a05:6402:34d4:b0:495:fa3d:1d72 with SMTP id w20-20020a05640234d400b00495fa3d1d72mr626508edc.8.1675199222160; Tue, 31 Jan 2023 13:07:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675199222; cv=none; d=google.com; s=arc-20160816; b=N5qeXTYZNTbdORhSeHFe7JDSVOPc7n4EQyZtWQG0DjRKqU92+l1XXy6dno6+IuIzVm +2aRFbmZF/FuQgYmYRRykjRkxs4fKZddqqU8hh4OxvCuioW9QcTDkisXh+qsa1oJu9E9 9EwzVw37CB5xEt6ca9KFxEN0Fu1AdFHYiMMBZ2sAs5T4AU6lF0OvZdQdPEMm3oBrqRyL 9gim67y78+VFU/Hl2gL5ZGMw1uq6SOHEwOF9QxZrFbxy2HvKCuEnjV77Y85Kh/aOJAF7 PzyOKxZ2TPBYnTzM3ReXL5iaMBfmSanMYFSmqGMM6V1PRgHRo28deD30HkoDmvRF6Zo5 L+fA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=1V5cuuwav3MMPhfUaTAvqss/U5kHMNq2CLWt809qYns=; b=lD7G8JuoSrCbwDlMtfQtkG1bNxPBEYXLuyVgauR/OicTxOPCSOWO4aXFeDdJePrSPJ n2swCTmOT1ukCXNVFzKs+nug9j8xF/eBXmvb5SlceqFmIxnBca89/L68E1axNn0/66nn aT8y2lg9+7f2n+7taqp3fOdpvylp1NDBIeD/bdJ1OnZRT2Zqg068W0KiRFpWxY+gLRxu lFHdrEulyTh9Gp1gZ0UhtY7srv22OIk0FK7xziv01GsQ5X8/VPICSI5YL2/By+mMzk8r 3Y2ELDXOf9UmYmJnIggYcJkvhC5t70dhrzU5reDOhEB9SXOvDkkS+axt2Ig5da2e6oAo A0Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=WgV2FwCk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y6-20020a056402440600b0046b2327bf88si24113739eda.76.2023.01.31.13.06.28; Tue, 31 Jan 2023 13:07:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=WgV2FwCk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231773AbjAaVFU (ORCPT + 99 others); Tue, 31 Jan 2023 16:05:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229876AbjAaVFQ (ORCPT ); Tue, 31 Jan 2023 16:05:16 -0500 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD8E0B1; Tue, 31 Jan 2023 13:05:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1675199113; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:references; bh=1V5cuuwav3MMPhfUaTAvqss/U5kHMNq2CLWt809qYns=; b=WgV2FwCk0FUAi8lZNNgSmYjvrJ+1V9pTMNi0J+ifSPY2TM8JVQzvH2MTGzI6kamryI53eR Y5xb7/2qAq+VIveHHqm6p6YSYOFm0nZcTKYxJXq1KIcAiWfAIs7rin8pymnc91kYYAu8QS EiQAdLdu8cPeO7wpwFR3gxl72Oruwdw= From: Paul Cercueil To: Linus Walleij Cc: linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, list@opendingux.net, Paul Cercueil Subject: [PATCH] pinctrl: ingenic: Add I2S pins for the JZ4760(B) and JZ4770 Date: Tue, 31 Jan 2023 21:05:08 +0000 Message-Id: <20230131210508.68775-1-paul@crapouillou.net> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=0.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, SUSPICIOUS_RECIPS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756573699493209917?= X-GMAIL-MSGID: =?utf-8?q?1756573699493209917?= Add the data structures to support the I2S pins of the JZ4760(B) and JZ4770 SoCs, which are mostly similar to the JZ4780 ones. Signed-off-by: Paul Cercueil --- drivers/pinctrl/pinctrl-ingenic.c | 57 +++++++++++++++++++++++-------- 1 file changed, 43 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 2f220a47b749..efcf6b9d88f3 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -901,7 +901,15 @@ static int jz4760_pwm_pwm5_pins[] = { 0x85, }; static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; static int jz4760_otg_pins[] = { 0x8a, }; - +static int jz4760_i2s_data_tx0_pins[] = { 0x87, }; +static int jz4760_i2s_data_tx1_pins[] = { 0x8b, }; +static int jz4760_i2s_data_tx2_pins[] = { 0x8c, }; +static int jz4760_i2s_data_tx3_pins[] = { 0x8d, }; +static int jz4760_i2s_data_rx_pins[] = { 0x86, }; +static int jz4760_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; +static int jz4760_i2s_sysclk_pins[] = { 0x85, }; + +static u8 jz4760_i2s_clk_txrx_funcs[] = { 1, 0, }; static u8 jz4760_uart3_data_funcs[] = { 0, 1, }; static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; @@ -1014,6 +1022,14 @@ static const struct group_desc jz4760_groups[] = { INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0), INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0), INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), + INGENIC_PIN_GROUP("i2s-data-tx0", jz4760_i2s_data_tx0, 0), + INGENIC_PIN_GROUP("i2s-data-tx1", jz4760_i2s_data_tx1, 0), + INGENIC_PIN_GROUP("i2s-data-tx2", jz4760_i2s_data_tx2, 0), + INGENIC_PIN_GROUP("i2s-data-tx3", jz4760_i2s_data_tx3, 0), + INGENIC_PIN_GROUP("i2s-data-rx", jz4760_i2s_data_rx, 0), + INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4760_i2s_clk_txrx, + jz4760_i2s_clk_txrx_funcs), + INGENIC_PIN_GROUP("i2s-sysclk", jz4760_i2s_sysclk, 2), }; static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; @@ -1074,6 +1090,10 @@ static const char *jz4760_pwm5_groups[] = { "pwm5", }; static const char *jz4760_pwm6_groups[] = { "pwm6", }; static const char *jz4760_pwm7_groups[] = { "pwm7", }; static const char *jz4760_otg_groups[] = { "otg-vbus", }; +static const char *jz4760_i2s_groups[] = { + "i2s-data-tx0", "i2s-data-tx1", "i2s-data-tx2", "i2s-data-tx3", + "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", +}; static const struct function_desc jz4760_functions[] = { { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, @@ -1105,6 +1125,7 @@ static const struct function_desc jz4760_functions[] = { { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, + { "i2s", jz4760_i2s_groups, ARRAY_SIZE(jz4760_i2s_groups), }, }; static const struct ingenic_chip_info jz4760_chip_info = { @@ -1249,6 +1270,7 @@ static int jz4770_mac_rmii_pins[] = { static int jz4770_mac_mii_pins[] = { 0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf, }; +static int jz4770_i2s_clk_rx_pins[] = { 0x88, 0x89, }; static const struct group_desc jz4770_groups[] = { INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), @@ -1351,6 +1373,15 @@ static const struct group_desc jz4770_groups[] = { INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0), INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0), INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0), + INGENIC_PIN_GROUP("i2s-data-tx0", jz4760_i2s_data_tx0, 0), + INGENIC_PIN_GROUP("i2s-data-tx1", jz4760_i2s_data_tx1, 0), + INGENIC_PIN_GROUP("i2s-data-tx2", jz4760_i2s_data_tx2, 0), + INGENIC_PIN_GROUP("i2s-data-tx3", jz4760_i2s_data_tx3, 0), + INGENIC_PIN_GROUP("i2s-data-rx", jz4760_i2s_data_rx, 0), + INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4760_i2s_clk_txrx, + jz4760_i2s_clk_txrx_funcs), + INGENIC_PIN_GROUP("i2s-sysclk", jz4760_i2s_sysclk, 2), + INGENIC_PIN_GROUP("i2s-clk-rx", jz4770_i2s_clk_rx, 1), }; static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; @@ -1412,6 +1443,10 @@ static const char *jz4770_pwm5_groups[] = { "pwm5", }; static const char *jz4770_pwm6_groups[] = { "pwm6", }; static const char *jz4770_pwm7_groups[] = { "pwm7", }; static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; +static const char *jz4770_i2s_groups[] = { + "i2s-data-tx0", "i2s-data-tx1", "i2s-data-tx2", "i2s-data-tx3", + "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", "i2s-clk-rx", +}; static const struct function_desc jz4770_functions[] = { { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, @@ -1445,6 +1480,7 @@ static const struct function_desc jz4770_functions[] = { { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), }, + { "i2s", jz4770_i2s_groups, ARRAY_SIZE(jz4770_i2s_groups), }, }; static const struct ingenic_chip_info jz4770_chip_info = { @@ -1780,16 +1816,9 @@ static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; -static int jz4780_i2s_data_tx_pins[] = { 0x87, }; -static int jz4780_i2s_data_rx_pins[] = { 0x86, }; -static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; -static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; -static int jz4780_i2s_sysclk_pins[] = { 0x85, }; static int jz4780_dmic_pins[] = { 0x32, 0x33, }; static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; -static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; - static const struct group_desc jz4780_groups[] = { INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0), INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0), @@ -1878,12 +1907,12 @@ static const struct group_desc jz4780_groups[] = { INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1), INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1), INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1), - INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0), - INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0), - INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx, - jz4780_i2s_clk_txrx_funcs), - INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1), - INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2), + INGENIC_PIN_GROUP("i2s-data-tx", jz4760_i2s_data_tx0, 0), + INGENIC_PIN_GROUP("i2s-data-rx", jz4760_i2s_data_rx, 0), + INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4760_i2s_clk_txrx, + jz4760_i2s_clk_txrx_funcs), + INGENIC_PIN_GROUP("i2s-clk-rx", jz4770_i2s_clk_rx, 1), + INGENIC_PIN_GROUP("i2s-sysclk", jz4760_i2s_sysclk, 2), INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1), INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0), INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),