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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id oz15-20020a1709077d8f00b0078dcc87b1c4si852854ejc.923.2022.10.15.21.43.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Oct 2022 21:43:09 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ndXnUrqn; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5A4B53857BB8 for ; Sun, 16 Oct 2022 04:43:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5A4B53857BB8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665895387; bh=5s8Rm6ZhfVPXlpXx4AArdo5xn4zgELsTk3xsBwovfVA=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=ndXnUrqnmGUavP1v9W0/FxY9hbQdcEIFHnM0bgwRZr9v/IIZtSNioB1ec5wKA0s6A m9TLlhxEXpeaPIK/6Xb6wlHs8+CncNAY9gRdN3NPz8wVf/e7lvdQ5b7A5hYKkCuo05 v0eiyakqmpUciTSMBp3X0DE/tmRNzAISWDDzJg8s= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by sourceware.org (Postfix) with ESMTPS id 67D563858295 for ; Sun, 16 Oct 2022 04:42:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 67D563858295 Received: by mail-pj1-x102c.google.com with SMTP id l1-20020a17090a72c100b0020a6949a66aso8261972pjk.1 for ; Sat, 15 Oct 2022 21:42:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-disposition:mime-version:message-id:subject:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5s8Rm6ZhfVPXlpXx4AArdo5xn4zgELsTk3xsBwovfVA=; b=VbqzVeFi3cQXzafwaNb31AjoHXY8bww+YBbk/umgIwxq+szeR0oEPSQmKCJUmTkkeQ 54Fvt9SO8/mDFGinBOPUG07VWGED+yT6WVdHPCdaLutTMoRUecUNd8Sj+OYHVrWpQwVD CUgn/zfD46I58XcuPEDye8Th2z/k1BIMfCD9haDlENG+a8Au3+kmmZgEvMMCMXmp6ImM ZD55FtwbA8ZsnSbrGxmubEFBth6pUQsW/REM+FJL/qfXZqZ/Y28wNzPrXRRyWOTKRFzs YK72Ax9vGlfSP3jks4q32OwiL4ncGQSAhvvgaLM7w59ri8QL/8OJ0yRkBd5kk7KWoKiJ B4lw== X-Gm-Message-State: ACrzQf2MMtfeFr08D0TuqNfvPPueBOistAdsAMqz30HpIc/Ti8Ft0BXl wthfzdi+ODIvteZEAQiBlCtmhQRWuNA= X-Received: by 2002:a17:902:dad1:b0:183:243c:d0d0 with SMTP id q17-20020a170902dad100b00183243cd0d0mr5566427plx.157.1665895376834; Sat, 15 Oct 2022 21:42:56 -0700 (PDT) Received: from squeak.grove.modra.org ([2406:3400:51d:8cc0:bac0:4bae:a946:4a1d]) by smtp.gmail.com with ESMTPSA id i3-20020aa796e3000000b005633a06ad67sm4326724pfq.64.2022.10.15.21.42.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Oct 2022 21:42:56 -0700 (PDT) Received: by squeak.grove.modra.org (Postfix, from userid 1000) id A19D11142DD1; Sun, 16 Oct 2022 15:12:53 +1030 (ACDT) Date: Sun, 16 Oct 2022 15:12:53 +1030 To: binutils@sourceware.org Subject: PowerPC se_rfmci and VLE, SPE2 and LSP insns with -many Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-3035.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alan Modra via Binutils From: Alan Modra Reply-To: Alan Modra Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746817924210425779?= X-GMAIL-MSGID: =?utf-8?q?1746817924210425779?= I noticed recently that se_rfmci, a VLE mode instruction, was being accepted by non-VLE cpus, and also that se_rfmci by itself in a section did not cause SHF_PPC_VLE to be set. ie. both testcases added by this patch fail without the changes to tc-ppc.c here. Also, VLE, SPE2 and LSP insns were not accepted by the assembler with -many nor were SPE2 and LSP being disassembled with -Many. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Wrap long lines. Add vle_opcodes when PPC_OPCODE_VLE or PPC_OPCODE_ANY. Simplify disassembler index segment checks. Add LSP and SPE2 opcodes when PPC_OPCODE_ANY too. (md_assemble): Correct logic adding PPC_APUINFO_VLE and SHF_PPC_VLE. * testsuite/gas/ppc/se_rfmci.s * testsuite/gas/ppc/se_rfmci.d, * testsuite/gas/ppc/se_rfmci_bad.d: New tests. * testsuite/gas/ppc/ppc.exp: Run them. opcodes/ * ppc-dis.c (print_insn_powerpc): Disassemble SPE2 and LSP insn when -Many. * ppc-opc.c (vle_opcodes ): Comment. diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 5077e055401..97ad782012c 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1694,10 +1694,12 @@ ppc_setup_opcodes (void) unsigned int new_opcode = PPC_OP (op[0].opcode); #ifdef PRINT_OPCODE_TABLE - printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", + printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx" + "\tmask: 0x%llx\tflags: 0x%llx\n", op->name, (unsigned int) (op - powerpc_opcodes), new_opcode, (unsigned long long) op->opcode, - (unsigned long long) op->mask, (unsigned long long) op->flags); + (unsigned long long) op->mask, + (unsigned long long) op->flags); #endif /* The major opcodes had better be sorted. Code in the disassembler @@ -1745,10 +1747,12 @@ ppc_setup_opcodes (void) unsigned int new_opcode = PPC_PREFIX_SEG (op[0].opcode); #ifdef PRINT_OPCODE_TABLE - printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", + printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx" + "\tmask: 0x%llx\tflags: 0x%llx\n", op->name, (unsigned int) (op - prefix_opcodes), new_opcode, (unsigned long long) op->opcode, - (unsigned long long) op->mask, (unsigned long long) op->flags); + (unsigned long long) op->mask, + (unsigned long long) op->flags); #endif /* The major opcodes had better be sorted. Code in the disassembler @@ -1775,43 +1779,42 @@ ppc_setup_opcodes (void) for (op = prefix_opcodes; op < op_end; op++) str_hash_insert (ppc_hash, op->name, op, 0); - op_end = vle_opcodes + vle_num_opcodes; - for (op = vle_opcodes; op < op_end; op++) + if ((ppc_cpu & (PPC_OPCODE_VLE | PPC_OPCODE_ANY)) != 0) { - if (ENABLE_CHECKING) + unsigned int prev_seg = 0; + unsigned int seg; + + op_end = vle_opcodes + vle_num_opcodes; + for (op = vle_opcodes; op < op_end; op++) { - unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); + if (ENABLE_CHECKING) + { + seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); #ifdef PRINT_OPCODE_TABLE - printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", - op->name, (unsigned int) (op - vle_opcodes), - (unsigned int) new_seg, (unsigned long long) op->opcode, - (unsigned long long) op->mask, (unsigned long long) op->flags); + printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx" + "\tmask: 0x%llx\tflags: 0x%llx\n", + op->name, (unsigned int) (op - vle_opcodes), + (unsigned int) seg, (unsigned long long) op->opcode, + (unsigned long long) op->mask, + (unsigned long long) op->flags); #endif - /* The major opcodes had better be sorted. Code in the disassembler - assumes the insns are sorted according to major opcode. */ - if (op != vle_opcodes - && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask))) - { - as_bad (_("major opcode is not sorted for %s"), op->name); - bad_insn = true; + if (seg < prev_seg) + { + as_bad (_("major opcode is not sorted for %s"), op->name); + bad_insn = true; + } + prev_seg = seg; + bad_insn |= insn_validate (op); } - bad_insn |= insn_validate (op); - } - - if ((ppc_cpu & op->flags) != 0 - && !(ppc_cpu & op->deprecated) - && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) - { - as_bad (_("duplicate %s"), op->name); - bad_insn = true; + str_hash_insert (ppc_hash, op->name, op, 0); } } /* LSP instructions */ - if ((ppc_cpu & PPC_OPCODE_LSP) != 0) + if ((ppc_cpu & (PPC_OPCODE_LSP | PPC_OPCODE_ANY)) != 0) { unsigned int prev_seg = 0; unsigned int seg; @@ -1835,46 +1838,27 @@ ppc_setup_opcodes (void) } /* SPE2 instructions */ - if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) + if ((ppc_cpu & (PPC_OPCODE_SPE2 | PPC_OPCODE_ANY)) != 0) { + unsigned int prev_seg = 0; + unsigned int seg; op_end = spe2_opcodes + spe2_num_opcodes; for (op = spe2_opcodes; op < op_end; op++) { if (ENABLE_CHECKING) { - if (op != spe2_opcodes) + seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); + if (seg < prev_seg) { - unsigned old_seg, new_seg; - - old_seg = VLE_OP (op[-1].opcode, op[-1].mask); - old_seg = VLE_OP_TO_SEG (old_seg); - new_seg = VLE_OP (op[0].opcode, op[0].mask); - new_seg = VLE_OP_TO_SEG (new_seg); - - /* The major opcodes had better be sorted. Code in the - disassembler assumes the insns are sorted according to - major opcode. */ - if (new_seg < old_seg) - { as_bad (_("major opcode is not sorted for %s"), op->name); bad_insn = true; - } } - + prev_seg = seg; bad_insn |= insn_validate (op); } - if ((ppc_cpu & op->flags) != 0 - && !(ppc_cpu & op->deprecated) - && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) - { - as_bad (_("duplicate %s"), op->name); - bad_insn = true; - } + str_hash_insert (ppc_hash, op->name, op, 0); } - - for (op = spe2_opcodes; op < op_end; op++) - str_hash_insert (ppc_hash, op->name, op, 0); } if (bad_insn) @@ -4035,7 +4019,7 @@ md_assemble (char *str) be set for VLE-only instructions or for VLE-only processors, however it'll remain clear for dual-mode instructions on dual-mode and, more importantly, standard-mode processors. */ - if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE) + if (ppc_cpu & opcode->flags & PPC_OPCODE_VLE) { ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1); if (elf_section_data (now_seg) != NULL) diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 1bfd375ccd6..ae8a7b61cde 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -87,6 +87,8 @@ run_dump_test "vle-simple-4" run_dump_test "vle-simple-5" run_dump_test "vle-simple-6" run_dump_test "vle-mult-ld-st-insns" +run_dump_test "se_rfmci" +run_dump_test "se_rfmci_bad" run_dump_test "lsp" run_dump_test "lsp-checks" run_dump_test "efs" diff --git a/gas/testsuite/gas/ppc/se_rfmci.d b/gas/testsuite/gas/ppc/se_rfmci.d new file mode 100644 index 00000000000..f43afe3061e --- /dev/null +++ b/gas/testsuite/gas/ppc/se_rfmci.d @@ -0,0 +1,9 @@ +#as: -a32 -mbig -mvle +#objdump: -d -Mvle + +.*: +file format elf.*-powerpc.* + +Disassembly of section \.text: + +0+00 <.*>: + 0: 00 0b se_rfmci diff --git a/gas/testsuite/gas/ppc/se_rfmci.s b/gas/testsuite/gas/ppc/se_rfmci.s new file mode 100644 index 00000000000..fd8a479bce0 --- /dev/null +++ b/gas/testsuite/gas/ppc/se_rfmci.s @@ -0,0 +1 @@ + se_rfmci diff --git a/gas/testsuite/gas/ppc/se_rfmci_bad.d b/gas/testsuite/gas/ppc/se_rfmci_bad.d new file mode 100644 index 00000000000..134f2d8a875 --- /dev/null +++ b/gas/testsuite/gas/ppc/se_rfmci_bad.d @@ -0,0 +1,3 @@ +#source: se_rfmci.s +#as: -a32 -mbig -me500mc +#error: .*unrecognized opcode.* diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index cc9328c106a..33a96701ca8 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -1016,6 +1016,10 @@ print_insn_powerpc (bfd_vma memaddr, opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY); if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) opcode = lookup_powerpc (insn, dialect); + if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) + opcode = lookup_spe2 (insn, dialect); + if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) + opcode = lookup_lsp (insn, dialect); } if (opcode != NULL) diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index e1b67647da6..b470ebd0aa9 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -9675,6 +9675,10 @@ const struct powerpc_opcode vle_opcodes[] = { {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, +/* PPCRFMCI in the following does not enable the instruction for any + PPC_OPCODE_RFMCI supporting cpu as vle_opcodes are all added to the + assembler hash table or searched by the disassembler under control + of PPC_OPCODE_VLE. It's there to set apuinfo. */ {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, {"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}}, {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, @@ -9746,7 +9750,7 @@ const struct powerpc_opcode vle_opcodes[] = { {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, -{"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, +{"e_stmvmcsrrw",OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, {"e_la", OP(7), OP_MASK, PPCVLE, EXT, {RT, D, RA0}}, {"e_sub16i", OP(7), OP_MASK, PPCVLE, EXT, {RT, RA, NSI}},