From patchwork Mon Jan 30 23:59:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 50553 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2463507wrn; Mon, 30 Jan 2023 16:03:16 -0800 (PST) X-Google-Smtp-Source: AK7set/xFS/ZsAf0vvaeYoNmD/WjsohpkmMOd0blutjrdZEa6qzKi7TZ04esouvi9RYTEOrzTMLL X-Received: by 2002:a17:903:2452:b0:196:4cbe:dfc5 with SMTP id l18-20020a170903245200b001964cbedfc5mr21284725pls.68.1675123396607; Mon, 30 Jan 2023 16:03:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675123396; cv=none; d=google.com; s=arc-20160816; b=zZIMYCd3BKJiDzpB6UAlS4o2oFzmQRv6+tQfevQxbSM56IS/CW3a9XwAtWGyyCVdE0 6Mg+HmtkJZ0howdvKkbYd68Yv5P27o1i+1G953XJFOuHVgF8bhl5pInOaHZzcG6iTv4y INNhgcBra+u0tm0m+ge21EMR2XrVkcDAPXcHR5LQG+mjHAXSrxiQv/a3A8bdix8u9hH0 sp1L2P2s94YKeWRJXPZS59HIcPnrut2Rzr0N4KDgImEPOzTA2Xk5rohaPjRgHHs2mB3Q T+HVRtSVEvedx61aoYQzQjam3hy/xVlHP+R4GcRjUO196LCkOSaLaeWHAIhNvThhTH7u wTTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NK0SKG71RZ4dw+5nnEyn5ShqdhAamRvl2RaxLYeTyWM=; b=VhYF6T8YJspn/qATj5XJMj8IMiK4Fi0a//cgrCBL7X+5mmKt6VfR+yYAYDtE2HBjrH xbo3a2jU8fuLkTIpZ+sD018RgcrD8xr16hJlp/ejOzZ8+mWs8uxlgjZRKTg131tQTvJG LRCRYVGPgqc+otzx43WZp7KaSPmHunuxJ/+Gn7ld7QCe+imje3/ZXGcdYVldLyBxetHW ClADOWODH70ReOI9ZgdSer0BCl7n0NfuZj5XT0cVc4zHzZMBklORjnAL/Tva2sqwqhY1 +wTqd3K6VWgfkxnrXZvBd+m3Ri61sn4JoyLBtJzrWBrOJebk+ODMb82jNHGmzFoJvwk+ jShA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ds+Afxgf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f19-20020a170902e99300b001948d2ef5b8si13228038plb.582.2023.01.30.16.03.03; Mon, 30 Jan 2023 16:03:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ds+Afxgf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231263AbjA3X7j (ORCPT + 99 others); Mon, 30 Jan 2023 18:59:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230481AbjA3X7i (ORCPT ); Mon, 30 Jan 2023 18:59:38 -0500 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1802D1CF6B for ; Mon, 30 Jan 2023 15:59:37 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id m8so3550914edd.10 for ; Mon, 30 Jan 2023 15:59:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NK0SKG71RZ4dw+5nnEyn5ShqdhAamRvl2RaxLYeTyWM=; b=Ds+Afxgf+WLba6Gy2WOS4g51/bZH2b9Kx8axvdSVrcpQPKh8wQ3Ksk1rrnyBtljdgO IZg0o6WMPPeylVznB8LufOQpUTYXnQ63/cCNM81XuWkrnQdDXALUyqVDbL+XAHluK7Dd aX4AaCq4VT+vm3o+p+BF1zjxTzD04w4smD/zhjSGznBdSm4fqO8k5r8i+0v0HLAzDESP XBqZOmxuUPEPydiRltZcChObSQJYZjd2qkYQzMuQsJRyGgiImbfzl3p6sKAhwtu1lArP lQTYAjUibT/mD9BelgSmYXwseWDWZfHWbXMc3AVxBISapFP8XKxzrTBuCaAMRxqNC6nq rzrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NK0SKG71RZ4dw+5nnEyn5ShqdhAamRvl2RaxLYeTyWM=; b=Np/ZGi8AdsYXidFmpoUQNbGJVPSaH9zAYcHHTzO3K3XAu1Rpo+KjLlnzfd3pghXugo HncPJaKcsSrRDgzF72NOfv6qh/EUhAu/6Y57ok+jU9ksna3iYce1nMmoOlWUWZMXDgbm 1WwluB8NF3ok7k9BEXo2Kyhp9ftHibgkbu37UvWhHW5vt4IZZ06KW6AAZv9GAqZ9uMCq MhFrvmhfRPlPvyXogDbwq1003s9KqRG3DAi6H1/loBXxmz7Wg3GZ68mL8bL/VtWgEBbt 43GkKnvd97DXq3EAD8eydq9yyLR/OqvZhWewvFk6H784HSisef/ZA/SasSRwpWQb2HJy lNxA== X-Gm-Message-State: AO0yUKUb2bNrYgvIqQ3/sePSXhFPPcbJ5DgDJ8CZgM8VB7SjvxBdB6pO Rf92LvSFndNh6bEMzre5QoNKIg== X-Received: by 2002:aa7:d858:0:b0:4a0:b7d6:57db with SMTP id f24-20020aa7d858000000b004a0b7d657dbmr21224156eds.33.1675123175668; Mon, 30 Jan 2023 15:59:35 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:35 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/8] clk: qcom: branch: Add helper functions for setting retain bits Date: Tue, 31 Jan 2023 00:59:19 +0100 Message-Id: <20230130235926.2419776-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756494190596357302?= X-GMAIL-MSGID: =?utf-8?q?1756494190596357302?= Most Qualcomm branch clocks come with a pretty usual set of bits that can enable memory retention by means of not turning off parts of the memory logic. Add them to the common header file and introduce helper functions for setting them instead of using magic writes. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-branch.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 17a58119165e..d8fc7b93ef6d 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -37,6 +37,29 @@ struct clk_branch { struct clk_regmap clkr; }; +/* Branch clock common bits for HLOS-owned clocks */ +#define CBCR_FORCE_MEM_CORE_ON BIT(14) +#define CBCR_FORCE_MEM_PERIPH_ON BIT(13) +#define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) + +static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, u32 reg, bool on) +{ + regmap_update_bits(regmap, reg, CBCR_FORCE_MEM_CORE_ON, + on ? CBCR_FORCE_MEM_CORE_ON : 0); +} + +static inline void qcom_branch_set_force_periph_on(struct regmap *regmap, u32 reg, bool on) +{ + regmap_update_bits(regmap, reg, CBCR_FORCE_MEM_PERIPH_ON, + on ? CBCR_FORCE_MEM_PERIPH_ON : 0); +} + +static inline void qcom_branch_set_force_periph_off(struct regmap *regmap, u32 reg, bool on) +{ + regmap_update_bits(regmap, reg, CBCR_FORCE_MEM_PERIPH_OFF, + on ? CBCR_FORCE_MEM_PERIPH_OFF : 0); +} + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; From patchwork Mon Jan 30 23:59:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 50556 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2464541wrn; Mon, 30 Jan 2023 16:05:31 -0800 (PST) X-Google-Smtp-Source: AK7set8zgoBBBFTO5fQMDZ3tceIBm/m3wO+sI1VXsLDmjCY/vPvVJctRFWkPADYB9peXK1yTjR/7 X-Received: by 2002:a05:6402:378b:b0:4a2:4abc:29be with SMTP id et11-20020a056402378b00b004a24abc29bemr5171455edb.35.1675123531595; Mon, 30 Jan 2023 16:05:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675123531; cv=none; d=google.com; s=arc-20160816; b=hSlr6CQ/3NYP8jgdXyJ11ck9cwWPF3uZIMfsf1ZhngKUoAvTYlEO+5aorVqy9A/YrK Q+V+Yrv1LqIP2d5FsmV4DGib3FPWQSQKnMz70jaZ79OacH3iW4Rlwkm13POMnsEOC9/r XIj+7gugKy2DeBsIG0e8m7B5Jh4yDb1/V22p6zrcHT+JQ4GPjGasskRPsY5WUQWlrOU8 krS7Dh7GHjzYvaBRGgOzoS1d+YK4fW8iDy+NT0fwFYTfQI74yqNPKkNU58lU9HzUdB+O PYwwcwyVzwKTlIr7ZBUISxyXeeuvRj1o35C1Qvg+dnUO5NInGbYC+YHMoV6TbWs2dd65 WDzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aWGy+d1x41QAHpHzB5Mf6KI/uH3br8ARPCTrkb+qZ2A=; b=AU8CQHFrnIMLgsokWngbqKAZKJs1RjYbjFdzAKeNF/3rkQ4tqtATbAGkKrvGFLVKHL 4RFjUaaiNgsaIfHj7ABH1eMAne83ux2v4rMj5bR6KvnZoUSlujIDmR+EyVSVNCJBuKQv UgINGEGPJZBrSnqS3a3fcZTfE6/qlcBS0f71WD8rDqcLGeONZtxMU5w5oDSFcJxR2tzM IZir3K2zgu3gQ6n2Pqb4lgdLWskrq6gbPExWJNBGzK7FnYuiCsVakSfcDI/zLJeADrNT KououSodEcfaYTd17f3Q/bMYiEhJKOVOh36IoYT/r4xsVV8FpzhfIL9nKMRROI+RBcw2 k30Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HwHIHYZ5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h25-20020aa7de19000000b0046b1d405d4asi15246261edv.206.2023.01.30.16.05.07; Mon, 30 Jan 2023 16:05:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HwHIHYZ5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229969AbjA3X7l (ORCPT + 99 others); Mon, 30 Jan 2023 18:59:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231272AbjA3X7j (ORCPT ); Mon, 30 Jan 2023 18:59:39 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D1D11CF6B for ; Mon, 30 Jan 2023 15:59:38 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id qw12so21014198ejc.2 for ; Mon, 30 Jan 2023 15:59:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aWGy+d1x41QAHpHzB5Mf6KI/uH3br8ARPCTrkb+qZ2A=; b=HwHIHYZ51hTrApQCxcPqlwjpY/C4bkSm1evdoWD0HfowfZl3UFnwuC8bP3nNMPAgCQ 0tD6Y291TuLrYBKVkrHcxZC+gVy3LCh2PjYgZreqhoEVvLZ5dZUJyNPMtSSs5Yy1LOe4 ghD/82FNbm/LWQZN/5yIOXEfIJXGEzi/0/aPk6wth3dmggXQu3HYXFISNNdIKQtFEt7F rRTlJmx1DZz6ftOoCO5XNhA/Dw3y2LMCyWL5VFGjESIPObwFN6Rr11zj1peSRrD1I/m6 Hkiy1BfWnCPMRlVumPy9lb7LHX/C4HB6CXDCvW/POXakY8bNbnDm+GyAGegdZtSb42cM KsnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aWGy+d1x41QAHpHzB5Mf6KI/uH3br8ARPCTrkb+qZ2A=; b=SruVQMWPSm7d/tyQyTCFcqPzRAFt90rbRkGMzcW7cYRpHgZIM5bTc/Bv4Rs3e/E8jJ WtJTYl+KdH0pG7G8DUQh3zAayIHfz4ua8H7Zst4i6EVICw74g8ST+95mtIJtEVw72msy ipYuWkgI/88NuG80lAcb5KsWyVtk0CvsBskvuSGe9jvqzhsL5QWUCCmlTvix3CY5mZ9o hn7YiWs/Zje5vH7/XqF+VDT7c5prEgpPoI6O+ZlkroOnivaMMjJLMIOZM76DtQDDMJdl Gkm6yrUnCzY8J0FkPx8ZtsQ7+sx/mDL3hartjpsUdhfk4LnExb8cm6iBF25Aof0U0hKs QBJA== X-Gm-Message-State: AO0yUKUHoj/SS0vuxMe0r0uhZWM2IQlKu+Kpa5divui3tlt9aB8+x622 rJf761E3ah/OpE1tZAVaB12I3Q== X-Received: by 2002:a17:907:728d:b0:88b:bf70:2e79 with SMTP id dt13-20020a170907728d00b0088bbf702e79mr1288223ejc.30.1675123177051; Mon, 30 Jan 2023 15:59:37 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:36 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/8] clk: qcom: branch: Add SLEEP/WAKE fields definitions Date: Tue, 31 Jan 2023 00:59:20 +0100 Message-Id: <20230130235926.2419776-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756494331948380331?= X-GMAIL-MSGID: =?utf-8?q?1756494331948380331?= HLOS-controlled branch clocks on non-ancient Qualcomm platforms feature SLEEP and WAKE fields which can be written to to configure how long the clock hardware should wait internally before being (un)gated. Some very sensitive clocks need to have these values programmed to prevent putting the hardware in a not-exactly-good state. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-branch.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index d8fc7b93ef6d..773f760a4590 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -41,6 +41,8 @@ struct clk_branch { #define CBCR_FORCE_MEM_CORE_ON BIT(14) #define CBCR_FORCE_MEM_PERIPH_ON BIT(13) #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) +#define CBCR_WAKEUP GENMASK(11, 8) +#define CBCR_SLEEP GENMASK(7, 4) static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, u32 reg, bool on) { From patchwork Mon Jan 30 23:59:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 50554 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2463765wrn; Mon, 30 Jan 2023 16:03:48 -0800 (PST) X-Google-Smtp-Source: AK7set82D/5uH7SQLbgu94j2bvgwX9zNZU+P5xADI1Iw8UA8RAHv5sg0nDL5AymGTYKiPjY7Xjoe X-Received: by 2002:a17:907:e8c:b0:88b:af3b:2a1a with SMTP id ho12-20020a1709070e8c00b0088baf3b2a1amr1809477ejc.49.1675123428608; Mon, 30 Jan 2023 16:03:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675123428; cv=none; d=google.com; s=arc-20160816; b=S5SJd6gtfWXM20ZL4iBMLaBcI5qQf5DivycIAuorNS1L66+3649jDeyoZ0pTGer1+H te+1/bpEsNpx/zEWB6p1GDIwep9tw6/A3Upp1uRI7SGB+0qIkQ+FQx0KByo9rM1GtrPQ B1LDPPY/e+Jjh/Sjgrc4ksfWnlzv0UieJqM8x50XjSDg5hgNTDSGOdKNUjl7wWTfuUbD i8MhzO2Lb4tmlfL+0GQ59jXyBqOhkY+EgVEsxGXvl4lzbnce768FW8jIm59BpLb5TwV3 CgAEwCoCIq9CEe1EamkNz0md2nlFFOc5qOoEouYOUhw37P0pqgeF5570R2n9vvrzY9o7 bqwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VsZqVss/r1fgDB1F0vcdkCl/uod+C4uxkkKM1hV8pW8=; b=jrF1u3WyVFIlENoVsyiCEOPnsRqoe0ZZXvxrVAdDpn85lQhqpmhQYrNZNBPDFcRauy fibIVrOvM7wDr9kReqAb0Fu+tQJ5f/qkWqbjbA+Q9lrVVRiZxn1eZQTLKLD1l7eVHmHA ETerG4U458WPt+iwRVHWtz+1guSAtlhAKydSt0juRUAXjNbxB14rnGxfGcHC//jKw+tV zO4kvb83bZmJVIocAsleckhALwiYnUNPG+eZQw0o0lcPLQpNfmofz5q+y4mzP93K/Fet ScMOScT7WUTKAKJRLFlar71C7lcaiQl8eAlOwgJXa+J5ym3qdfsWRVGr+XmJPgqHPQhf +20Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lk0UQt4R; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id jr23-20020a170906515700b00872733f3b95si15475126ejc.336.2023.01.30.16.03.14; Mon, 30 Jan 2023 16:03:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lk0UQt4R; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231373AbjA3X76 (ORCPT + 99 others); Mon, 30 Jan 2023 18:59:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231287AbjA3X7m (ORCPT ); Mon, 30 Jan 2023 18:59:42 -0500 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7204A241D0 for ; Mon, 30 Jan 2023 15:59:40 -0800 (PST) Received: by mail-ej1-x634.google.com with SMTP id mf7so18180479ejc.6 for ; Mon, 30 Jan 2023 15:59:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VsZqVss/r1fgDB1F0vcdkCl/uod+C4uxkkKM1hV8pW8=; b=Lk0UQt4Rrn4ycn3nVPnjAtH56NWzkGwokDqAsT5h41hiez3MuaFJgGIaGh+leF84jp OgLR+zYT1AGnJ2Jzc/dL8z15GxQtubC0/VjbGHG+rVKzgPMZgwL1525/6ak6/hSGrWW8 w5n034Vr52tRKmLI7rT2g0mirRr2HfqDisx6JGahP380s0RPR/4VII+hrbyA84BWCpuK lK6ZbQdcN3CrlSmVgNFcW1yMgpR5yftw6oDRtreiUTSDFncG5IKynXYYLv1k1sHNKO1M 4FV4yk7jxOEFvbiMG+jm0I1QoICYaIegOsQD2Uphya8/dP9pZxLtOCYVD5IVOAhRLHKD hIyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VsZqVss/r1fgDB1F0vcdkCl/uod+C4uxkkKM1hV8pW8=; b=u9Zau69LEraCer1KmFxtYiEUnZN0bP4M5S+lfRLpuF/MkTvnrKjIJRINIwhkCVgcjv N5x/OeJGBadMkthV62mGE3glxFluu6uwVgKEb1k98HF50zBD4MObTYqiC6xChzPTGQy4 6qVUIEV1mRgpCUbUPZbtXNsMquW+CG0wu3R4/ON0sAyBojH53z6SNX0x113LC/o21czD IGmNIhB2t2Mg8S1xjIk0261tddtaXGZ1iEfo3/5kNrvortvNvAazqvduvk0ZXppVDCrw By9+ojgC/55l4P3IiuqkOJueN7KSrZZVZ/1iAJZlS1bQQO6H5MHgkIyW4b4EMBDnomq8 SbTA== X-Gm-Message-State: AO0yUKWyqiT05gEHadmS0potGxe0Zqq8tqtvNaYRdUfNgw9IamFHEya2 p87ykXggHPAAT/rdaDyyJMOIMA== X-Received: by 2002:a17:906:168a:b0:87d:f3e2:7f4d with SMTP id s10-20020a170906168a00b0087df3e27f4dmr13709753ejd.25.1675123179035; Mon, 30 Jan 2023 15:59:39 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:38 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/8] dt-bindings: clock: Add Qcom SM6125 GPUCC Date: Tue, 31 Jan 2023 00:59:21 +0100 Message-Id: <20230130235926.2419776-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756494224075910417?= X-GMAIL-MSGID: =?utf-8?q?1756494224075910417?= Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6125 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,sm6125-gpucc.yaml | 64 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6125-gpucc.h | 31 +++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6125-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml new file mode 100644 index 000000000000..374a1844a159 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6125 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6125-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6125-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6125-gpucc.h b/include/dt-bindings/clock/qcom,sm6125-gpucc.h new file mode 100644 index 000000000000..ce5bd920f2c4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6125-gpucc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H + +/* Clocks */ +#define GPU_CC_PLL0_OUT_AUX2 0 +#define GPU_CC_PLL1_OUT_AUX2 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GFX3D_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_SLEEP_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_AHB_CLK 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Mon Jan 30 23:59:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 50560 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2465138wrn; Mon, 30 Jan 2023 16:06:48 -0800 (PST) X-Google-Smtp-Source: AK7set8jnElzALfiX8ZNqi4CT9IUdKgw9YLY01EfRXGCyjqi2VH4XX3eO4WTFCt7YSg84+0FmzPC X-Received: by 2002:a17:907:1c0b:b0:877:61e8:915a with SMTP id nc11-20020a1709071c0b00b0087761e8915amr1675814ejc.75.1675123608085; Mon, 30 Jan 2023 16:06:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675123608; cv=none; d=google.com; s=arc-20160816; b=XHcBwYStI0g2NthryNTfGUO1lQHfs6/UhDBgrKMWvmGilJ2+jFHhoqcSflewF0W6B5 RmzelKkQ2hpWA2TOkg3en1/n7+pZLFoKn8LxCwkFGWm83d2XkSwK/eEI4KfwqsLM6u95 47451qcfYXQ8cUfbTYSOYbcvj1/49tp1FqvEue0RJOp7Scyge1T99J3Gft+qwwcOJ6SW jQN6uISvRHp2jA+RaNB1jhHPpv5/Vweh+jCdHRRRSBb4tjHPsjZ624z1Q1OZ4QhuSzNI uPY+d5J7DFDWtjAugz7wDJuD3WecrnYlefgacwGVQR+k0whjmCoskGW2AqPFDhTYGAgl 5YyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KmLISckY9dpbRHrENtP9yvVD2LawOuRJeOo8N5+lz+I=; b=Yrm0pdlB0nMteVqFBKshjWd84RE0iIbH/TAvha5ZrlAsEopTTF0I40Jf9euknWaKPj ICIRedRxswIoc7XIkNtk6VvcYK3MpvQdkVkM1W/sO7GgzSo1htlV6WEJxxzsTermkZZL lfvfBlrqambLvMw8iNZm3MRiHg5IUUCrWr+WR5NFzg77ZuiyD+JPqABiXyxY/1bkXFHX g7MTzh4RXnvJMNIWt4OcGJvK4yqAMFYH6esLWHblg6FgGm5mUjTowbUOSYC6tZofzR1Y Nu08dzyXnBLdhH86saLkwxLsL4VaCzsrd8MEW6eb9BDuyT7ZS+MaH/qdiogB2yNLulYb 7rtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kajPB5O3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u14-20020a170906108e00b0086d67b0615esi17567906eju.242.2023.01.30.16.06.16; Mon, 30 Jan 2023 16:06:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kajPB5O3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230495AbjAaAAE (ORCPT + 99 others); Mon, 30 Jan 2023 19:00:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231297AbjA3X7n (ORCPT ); Mon, 30 Jan 2023 18:59:43 -0500 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B23BD2B2A2 for ; Mon, 30 Jan 2023 15:59:41 -0800 (PST) Received: by mail-ej1-x631.google.com with SMTP id hx15so17374842ejc.11 for ; Mon, 30 Jan 2023 15:59:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KmLISckY9dpbRHrENtP9yvVD2LawOuRJeOo8N5+lz+I=; b=kajPB5O3Tt6udRjFQKW/1RWyQnTTvExXrdUna6VnqJ7HP4hV1NYnckgOdB40Jd6Z6g toPk3J8VkcJDQR3zSwhOEAZ069kVrI2zWRulVJoiOnyASg3pS7f9hE4VWFwH2rKvlHji PRoLKnsebwZwUkDqBKJrY2F99T2bcJt2oYbXdL07UuNC0yDOEFaO1DOyw4ycaUKLZjnp EOt+TnMd3TywKAjLF4w1XbXGBqdwiVsGIDuTP3IW3XBjClAw77TSF9ha1InxTuBC015p IfKNAHgFZ1iXFHOf9m2JT4RlJo41deiqxf0oo1saVbHNcP1aUHn2e3UNcYZU6u7ZsmgG yIVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KmLISckY9dpbRHrENtP9yvVD2LawOuRJeOo8N5+lz+I=; b=fA5fFuCJIivRjhsq2TomfsJZB/PoMD00ExVmC0S8bjHeDLax1sm2NHGl05mxtcKi/f uo99JqTklCbRo9L2RoyYLQaVJgmYkUhhM0hkaVCyW60kFHurP0zNhdJJQiPFm/MzZ4dh /D/7qOLp87o66ampayx0ccTQIB2pIf6QVfGBGhFfAX3dZtJyABFW3MrziSHS93K/erEE 0hjaD9jMxwOyo/tBZvxuznijbY5Hp+iRFfwazZPuVk+Uvaq1ZJYPN+V8/4J2hvv3V2J6 /kI+elA7xWhapoQtkVv6hJ8ukle8l6qy3lBKe9hlNmG93H2GaFnqjeRrmrNq6van9kPx 2dHg== X-Gm-Message-State: AO0yUKUmkERnQntoy61ecr6/tBBMO/ls/MVrRYZ2W+V7obdb22LVOqEx t8jiOBGpeQzsBrgUwDcxNPVIDw== X-Received: by 2002:a17:907:c1f:b0:7bd:43e9:d3ab with SMTP id ga31-20020a1709070c1f00b007bd43e9d3abmr1705351ejc.52.1675123181179; Mon, 30 Jan 2023 15:59:41 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:40 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Dmitry Baryshkov , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 4/8] clk: qcom: Add GPU clock controller driver for SM6125 Date: Tue, 31 Jan 2023 00:59:22 +0100 Message-Id: <20230130235926.2419776-5-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756494412479454226?= X-GMAIL-MSGID: =?utf-8?q?1756494412479454226?= Add support for the GPU clock controller found on SM6125. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6125.c | 424 ++++++++++++++++++++++++++++++++ 3 files changed, 434 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6125.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ca6c7d2ada6c..4ee1bf151ee2 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -798,6 +798,15 @@ config SM_GCC_8550 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_GPUCC_6125 + tristate "SM6125 Graphics Clock Controller" + select SM_GCC_6125 + depends on ARM64 || COMPILE_TEST + help + Support for the graphics clock controller on SM6125 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_6350 tristate "SM6350 Graphics Clock Controller" select SM_GCC_6350 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e41ea0efe8c4..14405ccf1992 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o +obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c new file mode 100644 index 000000000000..5ddaf45b6e0b --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6125.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPU_CC_PLL0_2X_CLK, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL1_OUT_AUX, + P_GPU_CC_PLL1_OUT_AUX2, +}; + +static struct pll_vco gpu_cc_pll_vco[] = { + { 1000000000, 2000000000, 0 }, + { 500000000, 1000000000, 2 }, +}; + +/* 1020MHz configuration */ +static const struct alpha_pll_config gpu_pll0_config = { + .l = 0x35, + .config_ctl_val = 0x4001055b, + .alpha_hi = 0x20, + .alpha = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x0 << 20, + .vco_mask = 0x3 << 20, + .aux2_output_mask = BIT(2), +}; + +/* 930MHz configuration */ +static const struct alpha_pll_config gpu_pll1_config = { + .l = 0x30, + .config_ctl_val = 0x4001055b, + .alpha_hi = 0x70, + .alpha = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .aux2_output_mask = BIT(2), +}; + +static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = { + .offset = 0x0, + .vco_table = gpu_cc_pll_vco, + .num_vco = ARRAY_SIZE(gpu_cc_pll_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0_out_aux2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = { + .offset = 0x100, + .vco_table = gpu_cc_pll_vco, + .num_vco = ARRAY_SIZE(gpu_cc_pll_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1_out_aux2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL1_OUT_AUX2, 4 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0_out_aux2.clkr.hw }, + { .hw = &gpu_cc_pll1_out_aux2.clkr.hw }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(320000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0), + F(465000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0), + F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk = { + .halt_reg = 0x1088, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gx_gfx3d_clk.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .pd = { + .name = "gpu_gx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm6125_clocks[] = { + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr, + [GPU_CC_PLL1_OUT_AUX2] = &gpu_cc_pll1_out_aux2.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static struct gdsc *gpucc_sm6125_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm6125_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm6125_desc = { + .config = &gpu_cc_sm6125_regmap_config, + .clks = gpu_cc_sm6125_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm6125_clocks), + .gdscs = gpucc_sm6125_gdscs, + .num_gdscs = ARRAY_SIZE(gpucc_sm6125_gdscs), +}; + +static const struct of_device_id gpu_cc_sm6125_match_table[] = { + { .compatible = "qcom,sm6125-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm6125_match_table); + +static int gpu_cc_sm6125_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm6125_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap, &gpu_pll0_config); + clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap, &gpu_pll1_config); + + /* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, CBCR_WAKEUP, 0xf); + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, CBCR_SLEEP, 0xf); + + qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk.halt_reg, true); + qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk.halt_reg, true); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap); +} + +static struct platform_driver gpu_cc_sm6125_driver = { + .probe = gpu_cc_sm6125_probe, + .driver = { + .name = "gpucc-sm6125", + .of_match_table = gpu_cc_sm6125_match_table, + }, +}; +module_platform_driver(gpu_cc_sm6125_driver); + +MODULE_DESCRIPTION("QTI GPUCC SM6125 Driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Jan 30 23:59:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 50559 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2465137wrn; Mon, 30 Jan 2023 16:06:48 -0800 (PST) X-Google-Smtp-Source: AMrXdXtb0wgTM4M8sXwT2bQqn/VKTtwDYxnlvUjnVBdRDRd/S3dAbemkR3zX02fkWAZt5v/WIrux X-Received: by 2002:a05:6402:197:b0:481:420e:206d with SMTP id r23-20020a056402019700b00481420e206dmr51602043edv.42.1675123607932; Mon, 30 Jan 2023 16:06:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675123607; cv=none; d=google.com; s=arc-20160816; b=YnjPe7K/oPnla26s6vu5LbvFf+AmaNalrFgwUHXkzGPJVz8mEC1UXstLI/mccqJXu9 V7uUdopP+MY5e6IoLSVW1A0VCayREha+auLxgNiVnEZvhKiXbxgvy+2MaZudHLBj63X2 wifq6mCauHuObrjvdnUZIXU+Zy0NMPyVlc2sQDYeztCeRDJ726WtMkV/VlHrTMO1r+1l iDLiQizGr0gKmnS4Gew1oSwMwUX3b+VJ150RDAmuiTY6aLKnbOCVDFThA6h7kzZlhMM8 5DYRKeoEPIh9pZwRTPS2DhckOmAlq2o6En79IK1aIszMrIE6gnCWMjz8014/4EBcevSL ORHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MjPN7pBI5UqQh3zYwpXxa2DpIw4tZgUWZdbUG7h3884=; b=xaQ+7Gb1J4R5U2aD5ESUkieMgrqfn+xxqXHZ4qpVmIUD9F0/FsDdSB6kcRmBoNLihI 9RWouB5ZuYEw4T/POs+tbDA9FQnc6BAgO3rZTX17mOLQCm9h2fsvNqkOYGy2OTmyULdE EGrLF+ZjiO7uvpfVGDNG/auvfaGUT0K7JWCHdSjSbtm5v6gyYb1v+ycIOqxKbnGukL7U XXf9z7FedbsFpgy1SS6xNyZg9C5hCsOcw19ITyruXET9JS61Wumnq2uOmc7eXOUYOxkf UjuC07RHKX6eMZBIOMHNVZD9wk3CvoddnGECmLiWrsSSb9VXxOlt4ZD/LPJc2JEVACtc IgSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OLrdnLOz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e15-20020a50ec8f000000b004a0e5c32c17si14874325edr.212.2023.01.30.16.06.15; Mon, 30 Jan 2023 16:06:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OLrdnLOz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231311AbjAaAAI (ORCPT + 99 others); Mon, 30 Jan 2023 19:00:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231408AbjA3X7r (ORCPT ); Mon, 30 Jan 2023 18:59:47 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0570265A7 for ; Mon, 30 Jan 2023 15:59:44 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id gr7so12312650ejb.5 for ; Mon, 30 Jan 2023 15:59:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MjPN7pBI5UqQh3zYwpXxa2DpIw4tZgUWZdbUG7h3884=; b=OLrdnLOzIkECvzt95wsqIhyo24/uSrgDF8q5Bvv0vkVC1f8PcjmrnFHpJtSjG161ih 7H7+bgvKNhypgoAMtLTsK2oLxVamvl7BQqDrfXflzsBCdCFo/z7KN2O2nmTysf3IRjNs M2yzxS5WCXSYDIIt9wZiPWwJsoFjrrWSzMAeJ1UM7v9k8WToNvIoRREBeannx2TJneYr ++nv61VGF6ibNoItFTJcxOoyjLcJUXRv0yT/9rfkDMhF3o9uridjDBxPqf4xag8rgwGB DprbW5I4P6weCnbKNnmNtQFLokJ3WhiWVSGu6lFMCGBtqO2g0D0wQ/v98OwKTCvdrJCo p+fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MjPN7pBI5UqQh3zYwpXxa2DpIw4tZgUWZdbUG7h3884=; b=0PlmQI36VUOQ783Dh7tHcozXCP8Yorkvw0OXKx5V94JNdq+1G70J28oE2GqXyyx8bF HOSamA36kOEyGmdpsvPk+4Xs3T+ujv/DNNMxVd92LCu5C7ZOKwK41DyI+xstRGfpUsIb KNhyCHHBFK7rkUIX2H+/bF/fpvXsQSvJjXNO1qGsaUhk90boqpCO0slG30Wi+Sf5Wr9y FDRR2gJ5o+BV9BvTeNIjMssGnuKzbz7a9HbIgh4nO2ceVTwb/T+uWfw86+GZgJLMiiET 0eiIKCuIFkw5wboqHCToAxX8U5m0PUGsC+6uHRMioznmhHAeq2W83uI87iRgUfyLMAVs LKbg== X-Gm-Message-State: AFqh2krt6S7wEWR4l8jrrx8wzSG5JoRdh6yOT58rUFIh4EyKSIWrKn1k gHwVS4gd2QQj/Vrur9rhxvRTGg== X-Received: by 2002:a17:906:3741:b0:861:eb6e:8019 with SMTP id e1-20020a170906374100b00861eb6e8019mr49525879ejc.69.1675123183202; Mon, 30 Jan 2023 15:59:43 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:42 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/8] dt-bindings: clock: Add Qcom SM6375 GPUCC Date: Tue, 31 Jan 2023 00:59:23 +0100 Message-Id: <20230130235926.2419776-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756494412113703464?= X-GMAIL-MSGID: =?utf-8?q?1756494412113703464?= Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6375 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,sm6375-gpucc.yaml | 60 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6375-gpucc.h | 36 +++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6375-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml new file mode 100644 index 000000000000..b480ead5bd69 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6375-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6375-gpucc.h b/include/dt-bindings/clock/qcom,sm6375-gpucc.h new file mode 100644 index 000000000000..0887ac03825e --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6375-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H + +/* GPU CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_CXO_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_SLEEP_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +/* Resets */ +#define GPU_GX_BCR 0 +#define GPU_ACD_BCR 1 +#define GPU_GX_ACD_MISC_BCR 2 + +#endif From patchwork Mon Jan 30 23:59:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 50557 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2465006wrn; Mon, 30 Jan 2023 16:06:27 -0800 (PST) X-Google-Smtp-Source: AK7set+/HNUmzon6V4K4IK12i8TtGh1pEiY4B3Q/JeaFqxgnEAHv6ZYJ+CAu7ySowdBU3nsVsm8Y X-Received: by 2002:aa7:d30f:0:b0:4a2:46f3:467e with SMTP id p15-20020aa7d30f000000b004a246f3467emr5994788edq.30.1675123587426; Mon, 30 Jan 2023 16:06:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675123587; cv=none; d=google.com; s=arc-20160816; b=wNYWL8x2Py6vLMwkrzVxuuM/B+XJpKglLFS86Gq7zZeLbcEXNhC/YxSPiylulsLuRW 9dyJ7dF64QVtxaoJdF8A0YU9mEvdJwFQMqqOTeZZttebs8CpC/0CALD14Ws/Fj/83nbO WsYA9nMriWKFKq4ZgqmSZ7mtv11aln54f01F0Fzt7N0xUyC9kbDAHUs2+WQDuG/ouT5G xs+x8pDRymRCZUUH9YLv74NtIKl3Ta6mmNIZ+Ao+0jUvseZcWuLpgo4uZvcBzwRlCMkP 1GLtUpg4osAJ0E+lrxJS2puOTOBOiDcDQf6YzRBUvo4GyoLYtlfIRMVlI8nOQ1JfCH9P DqYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=J/92gzTJ3wWFFNAaVNbE0CSJ241qRiQlJaJTUJDPclg=; b=qddYOsaYafy3lTeqaOmr1Pb1JNHze5V1aT5vdynCNtpRaBdVHV6wAOMM749sbAh209 EPfhYp7w3xnR21bEP+xAMbz2abKOv6WIiykvx7DMqJi1F3eOG4r16HQVQ9kjK+LEcyuf cOxDiYqZDYyositAH0QQSZnYlUudilvExeTP98cBgY+KjknvepFPPggDtJoINyJjGD/7 0HVxqoX6h4147G6Yivy2He1O+u1As1V4w/oZtns2byirz6v1N8ayJs9zdN6gENKrxrH6 XsDFeMuNQHIzcrWPDb1GbLvOU0dwebWYYLD2AQ7lM8+AQbzxTl0oYCWMWXDylLPYUoxM 49wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sos2DU9a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m18-20020a50c192000000b004a25afddd0dsi2352286edf.471.2023.01.30.16.06.03; Mon, 30 Jan 2023 16:06:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sos2DU9a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231344AbjAaAAK (ORCPT + 99 others); Mon, 30 Jan 2023 19:00:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231439AbjA3X7s (ORCPT ); Mon, 30 Jan 2023 18:59:48 -0500 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C083223D90 for ; Mon, 30 Jan 2023 15:59:45 -0800 (PST) Received: by mail-ej1-x634.google.com with SMTP id bk15so36877076ejb.9 for ; Mon, 30 Jan 2023 15:59:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J/92gzTJ3wWFFNAaVNbE0CSJ241qRiQlJaJTUJDPclg=; b=Sos2DU9aJJRf0kDflkWqW2yFg+LVCCy5yzO5ldYS899F0OL3dpmyXQa0vMEiuKqbA2 ikJtZ+0kaeypJDxWOOI0pEszzr0+KqVegiNmtj5DNnIjNopfu7K/YFOWIfenydI1miDv p4lM5M9mmwQ7jk1xt+nAzQPArs7m+cT1O+jOSW9NXay4dNXR5hpvpWSI5lwH412DTrQc cLfgWmmmH1fw4c1KHwGyNyyXnF6MUoD4qcDwwfaNrA0HPPYJqF0WzF2gy5Vn2sEysH6W mA2GFonHOrPX+aUQhwJaJV1iu7YR6KX3SJgJppSFnQFKU93HOF0bxDrJ8wFxZ0yd+tgf QQcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J/92gzTJ3wWFFNAaVNbE0CSJ241qRiQlJaJTUJDPclg=; b=qVusDknMxBp6mVYxWiaoxVe3C0uHDsZhCRpX5KxQFNdnSe+Gi4cyJVbdHxPZ8thVAP KIhXd0zX/A97IhM8JtIxlfnz2X9Da4Z1WEJZsa629qkoFNhBJxTMVkLWI+7x23WXEXOX tK4uQPppD07ku6wZGfVnQ0N2bRZOlAoRtyhmkTimKWAV2wBRsuEoMqm+ISNUxyl+QUva 29K/GBodkx36hnkzMKArGXCELypdsdZokeHRoc2Fl9Wu+TjR1io+o53mFUnQXxYiNd0e xa4rONRxffgBJW/6j7CIP2BDMreRUMI4vaLnMQyBd1V0mwRo4fbnZRRKx4qJMQgLSMhA A8lg== X-Gm-Message-State: AO0yUKVwDKEVJTCmR7gFI2fqSfQz3PZGTC5NqKDVPY7DOon/34PUW6/B I0IocmMQrWMBahGGMvRwZdhb2Q== X-Received: by 2002:a17:906:d29b:b0:888:42ed:e4d4 with SMTP id ay27-20020a170906d29b00b0088842ede4d4mr6912924ejb.18.1675123185270; Mon, 30 Jan 2023 15:59:45 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:45 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 6/8] clk: qcom: Add GPU clock controller driver for SM6375 Date: Tue, 31 Jan 2023 00:59:24 +0100 Message-Id: <20230130235926.2419776-7-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756494390611561242?= X-GMAIL-MSGID: =?utf-8?q?1756494390611561242?= Add support for the GPU clock controller found on SM6375. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6375.c | 469 ++++++++++++++++++++++++++++++++ 3 files changed, 479 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6375.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 4ee1bf151ee2..a5995ede04e9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -807,6 +807,15 @@ config SM_GPUCC_6125 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_GPUCC_6375 + tristate "SM6375 Graphics Clock Controller" + select SM_GCC_6375 + depends on ARM64 || COMPILE_TEST + help + Support for the graphics clock controller on SM6375 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_6350 tristate "SM6350 Graphics Clock Controller" select SM_GCC_6350 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 14405ccf1992..5a1b65b2ac05 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -114,6 +114,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o +obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c new file mode 100644 index 000000000000..eb9ffa956950 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, + DT_GCC_GPU_SNOC_DVM_GFX_CLK, +}; + +enum { + P_BI_TCXO, + P_GCC_GPU_GPLL0_CLK_SRC, + P_GCC_GPU_GPLL0_DIV_CLK_SRC, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, + P_GPU_CC_PLL1_OUT_EVEN, + P_GPU_CC_PLL1_OUT_MAIN, + P_GPU_CC_PLL1_OUT_ODD, +}; + +static struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +/* 532MHz Configuration */ +static const struct alpha_pll_config gpucc_pll0_config = { + .l = 0x1b, + .alpha = 0xb555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329a299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpucc_pll0 = { + .offset = 0x0, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpucc_pll0", + .parent_data = &(const struct clk_parent_data){ + .index = P_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +/* 514MHz Configuration */ +static const struct alpha_pll_config gpucc_pll1_config = { + .l = 0x1a, + .alpha = 0xc555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329a299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpucc_pll1 = { + .offset = 0x100, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpucc_pll1", + .parent_data = &(const struct clk_parent_data){ + .index = P_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +static const struct parent_map gpucc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, + { P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 }, +}; + +static const struct clk_parent_data gpucc_parent_data_0[] = { + { .index = P_BI_TCXO }, + { .hw = &gpucc_pll0.clkr.hw }, + { .hw = &gpucc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpucc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_EVEN, 1 }, + { P_GPU_CC_PLL0_OUT_ODD, 2 }, + { P_GPU_CC_PLL1_OUT_EVEN, 3 }, + { P_GPU_CC_PLL1_OUT_ODD, 4 }, + { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, +}; + +static const struct clk_parent_data gpucc_parent_data_1[] = { + { .index = P_BI_TCXO }, + { .hw = &gpucc_pll0.clkr.hw }, + { .hw = &gpucc_pll0.clkr.hw }, + { .hw = &gpucc_pll1.clkr.hw }, + { .hw = &gpucc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, +}; + +static const struct parent_map gpucc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, + { P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 }, +}; + +static const struct clk_parent_data gpucc_parent_data_2[] = { + { .index = P_BI_TCXO }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct freq_tbl ftbl_gpucc_gmu_clk_src[] = { + F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpucc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_0, + .freq_tbl = ftbl_gpucc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpucc_gmu_clk_src", + .parent_data = gpucc_parent_data_0, + .num_parents = ARRAY_SIZE(gpucc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpucc_gx_gfx3d_clk_src[] = { + F(266000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(390000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(490000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(770000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(840000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_1, + .freq_tbl = ftbl_gpucc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_gfx3d_clk_src", + .parent_data = gpucc_parent_data_1, + .num_parents = ARRAY_SIZE(gpucc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpucc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_gfx3d_slv_clk = { + .halt_reg = 0x10a8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_gfx3d_slv_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_snoc_dvm_clk", + .parent_data = &(const struct clk_parent_data){ + .index = DT_GCC_GPU_SNOC_DVM_GFX_CLK, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gx_cxo_clk = { + .halt_reg = 0x1060, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_cxo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gx_gmu_clk = { + .halt_reg = 0x1064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gpucc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .resets = (unsigned int []){ GPU_GX_BCR, GPU_ACD_BCR, GPU_GX_ACD_MISC_BCR }, + .reset_count = 3, + .pd = { + .name = "gpu_gx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | SW_RESET | AON_RESET, +}; + +static struct clk_regmap *gpucc_sm6375_clocks[] = { + [GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpucc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr, + [GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr, + [GPU_CC_PLL0] = &gpucc_pll0.clkr, + [GPU_CC_PLL1] = &gpucc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpucc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpucc_sm6375_resets[] = { + [GPU_GX_BCR] = { 0x1008 }, + [GPU_ACD_BCR] = { 0x1160 }, + [GPU_GX_ACD_MISC_BCR] = { 0x8004 }, +}; + +static struct gdsc *gpucc_sm6375_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpucc_sm6375_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpucc_sm6375_desc = { + .config = &gpucc_sm6375_regmap_config, + .clks = gpucc_sm6375_clocks, + .num_clks = ARRAY_SIZE(gpucc_sm6375_clocks), + .resets = gpucc_sm6375_resets, + .num_resets = ARRAY_SIZE(gpucc_sm6375_resets), + .gdscs = gpucc_sm6375_gdscs, + .num_gdscs = ARRAY_SIZE(gpucc_sm6375_gdscs), +}; + +static const struct of_device_id gpucc_sm6375_match_table[] = { + { .compatible = "qcom,sm6375-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table); + +static int gpucc_sm6375_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); + clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); +} + +static struct platform_driver gpucc_sm6375_driver = { + .probe = gpucc_sm6375_probe, + .driver = { + .name = "gpucc-sm6375", + .of_match_table = gpucc_sm6375_match_table, + }, +}; +module_platform_driver(gpucc_sm6375_driver); + +MODULE_DESCRIPTION("QTI GPUCC SM6375 Driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Jan 30 23:59:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 50558 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2465115wrn; Mon, 30 Jan 2023 16:06:44 -0800 (PST) X-Google-Smtp-Source: AK7set+WP70r++AGGrtby6eaR6/vP0uAdKLkxVrK51mNtFAEDaVNIJ90wQ4EwY5+4GSjw0zdottF X-Received: by 2002:a05:6a20:6f92:b0:be:e0c3:5003 with SMTP id gv18-20020a056a206f9200b000bee0c35003mr191270pzb.5.1675123604270; Mon, 30 Jan 2023 16:06:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675123604; cv=none; d=google.com; s=arc-20160816; b=X3hlUhNWVn9EV6LzUsgiaDRP1QRRejCOAWZ0xiLd26Zs0UEcZv6GkGMa7iNYsqtzfj OZS3KE1cUTwyPXaNifxK01xtseegPk0eWnZqFoS2kxa2375M8D1ZAczLIvUWodbdNOoj LnPQ6Sl3Tph1yDJnVBN+Jm3kuYVG3uff4GF/pHzC3g00ZZnIkuRW1NEqUJPmtbQeoOTe agylay1C55eU0TNNjiAfeY/Wp6x1BymSkkM1UmFrYtY05wiyzxSIHiyBUkfqE3e3x+Ay gt4ldvNaH/qqr60LT/arpXhjppo/2YpxZdDW6EgGG5m4pdGfueyT/i160ta2b4XBYzh1 exnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CDoOdjfsWKmLJAB94hSuPuVJscqgiA2qYQ0HfGwlM14=; b=ncqDESFYMQ5fJAc+eH9sAc52VCdrE7FFkjgGuBU+uae/A883/vK9c8lLVM7r5/i1Q6 oc4msGDBE3gUqTXEvAb8WX10CCBMNaIEsNKAMFkropExtK/Nj+BYZ/Ceox0qE8yBrq2F tmhIrNfUu12V1PRQk6L1Gf68ineSkjqRVrVRCWD7rMRs/RtK8dF2uq33Lcw8tVICq3vj gDH1qL6hhSg4SGb0FB+r18cK88H8RJ+fHzR1UWdo6Axh0mJr/eoEfQZmC1J+AKVn4kXn +Wr3SpcWliU3Z9EjwV/JK/F8rcTr9tFMghcjEbQbSKZVe3hJ76eVhTXplE60qjl18Eem bEvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zoyMpp6M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q23-20020a656a97000000b004dab94e3f03si14039592pgu.758.2023.01.30.16.06.24; Mon, 30 Jan 2023 16:06:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zoyMpp6M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231515AbjAaAAO (ORCPT + 99 others); Mon, 30 Jan 2023 19:00:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231531AbjA3X7x (ORCPT ); Mon, 30 Jan 2023 18:59:53 -0500 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1384241EB for ; Mon, 30 Jan 2023 15:59:48 -0800 (PST) Received: by mail-ej1-x62a.google.com with SMTP id k4so31439909eje.1 for ; Mon, 30 Jan 2023 15:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CDoOdjfsWKmLJAB94hSuPuVJscqgiA2qYQ0HfGwlM14=; b=zoyMpp6Mw+IHu+8pRT4ByKS6CEL8Oce2qDWrBO8hJwrcv/2e8dYzGpI15NGI82Thps dCmxAy30En9Rd3j3SiAtYVC+TdAs7V1E0IRG4t0WL6SbwIvMNZPOKOOy982SQLYdCvVv KYiKAc72zusfWG7C6QPKS6y/rrXrDM0wxtDyiPztjRNlfcoSzY/VYcchuTZ71q0N/66y yX/YkTlj1+Ts6UUaTW7/bSnLC6WTm/99flXNYicRVsa64lRZKd7TqEUPFKEuwbKjjTy8 D+cc3DMM5Yp3d+LvZkhZkAF+Ufb3R+0axI1ObSghkxANaKCcoCEWPx9aCq1L/zJeN+7X tC/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CDoOdjfsWKmLJAB94hSuPuVJscqgiA2qYQ0HfGwlM14=; b=CasuaxYKcBDFTIV+TUK2l+VfOsF2ALWzuSNl81jWOTDIXdptpwZGnFW7c1HQ09XJXn m6Q2rWDCNvob4x82SppOy9fgDduxAO2P4+cZ2v/4k8z7IuuPd9q/Yjad+aDVL0BpFGYp XZfi1t/XH5MsRTg4UxW6S7lBLZsDSxU3lTYiHop+qifogWluHZE0j5asiNoNM/G0wWfI YCgyBvIU+q2p1MNmuyeMYsUVFFBUT8vfPaJRz2vVDQUTq2yMTCh8EGOxl6vdL1XWKPJZ 3o5ZH6iMtf6A5pzuzhATcXBFRqMf9j5w6YTYaAMoQ3xotVr3z/v+UH7k/4yi9SGJ2xMi JZhQ== X-Gm-Message-State: AO0yUKVER//00An3xK5xcfrsTC67mx0svzwJZXZkaSD2sd0jrtgNml4G jFzCD2gPMCC0z291Okak/jRL9Q== X-Received: by 2002:a17:907:a0d2:b0:871:dd2:4afb with SMTP id hw18-20020a170907a0d200b008710dd24afbmr1421405ejc.42.1675123187287; Mon, 30 Jan 2023 15:59:47 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:47 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 7/8] dt-bindings: clock: Add Qcom SM6115 GPUCC Date: Tue, 31 Jan 2023 00:59:25 +0100 Message-Id: <20230130235926.2419776-8-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756494408281974783?= X-GMAIL-MSGID: =?utf-8?q?1756494408281974783?= Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6115 SoCs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- v3 -> v4: - Use unevaluatedProperties instead of additionalProperties .../bindings/clock/qcom,sm6115-gpucc.yaml | 58 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml new file mode 100644 index 000000000000..cf19f44af774 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6115 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6115-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 main div source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6115-gpucc.h b/include/dt-bindings/clock/qcom,sm6115-gpucc.h new file mode 100644 index 000000000000..945f21a7d745 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_AUX2 1 +#define GPU_CC_PLL1 2 +#define GPU_CC_PLL1_OUT_AUX 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CRC_AHB_CLK 5 +#define GPU_CC_CX_GFX3D_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_CXO_CLK 12 +#define GPU_CC_GX_GFX3D_CLK 13 +#define GPU_CC_GX_GFX3D_CLK_SRC 14 +#define GPU_CC_SLEEP_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Mon Jan 30 23:59:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 50555 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2464467wrn; Mon, 30 Jan 2023 16:05:23 -0800 (PST) X-Google-Smtp-Source: AK7set9e7tZ5aJhFDhQm4hktYAFqHyvlq0W9YMpvj8tTb30pma6y1wQo/LYzKhwronk3Z0vqcpH8 X-Received: by 2002:a17:90b:3a84:b0:22c:52a0:c2a2 with SMTP id om4-20020a17090b3a8400b0022c52a0c2a2mr11359404pjb.16.1675123523458; Mon, 30 Jan 2023 16:05:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675123523; cv=none; d=google.com; s=arc-20160816; b=Fbcedn/IdUoON0PDtLyTiOD72hDUDrCInC8fCMWbnihEZEPXdmRHH3m6OeFZshkrkE uMfwcNytBsdp/KHix3xpbIpH6rjQmuGz3QdPftDE3OgbYn0Xh+JcFli6omgPJE+VXbLl hdXzRt75AymblSrio2OpMmf0gTh9aiUbzqn+VTJTMz0zRG7wxxfcAPUS0izmmn8gGgzG OjDmE5EYOvcAVSZpGkomtdaUo5VB1kNPN+5hGtX9GeuhTd1c8T+EYFtwifNi9oxY99Zj v2ByqZl5qMhp3i8sqJaSI0fZN058wCAaKqx4WP71YjURdLP8wi1kjmIj1BDoBTrnjBfs BFiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=S8yOsvXNT0wYZs16RDglK3sp3e+Qo59M+SSIlkFjXoA=; b=QZNZ0XCKEE60b6peoQSTkXqtgr//+JUP8KbtDYKG/KRjTCbI1bTBCICdfGTIYxWgJL cGT0xU3knyGejlJHIhqVagMBd838ShnMC4P7JeIKsGtJJFRR0+jMuWm5wUUwRDU5J/lh DLcXEekePd3qAollyDif7NrJPMCd2Enjb6BzGqQ9vp9ReorCP+5QzaLY7fGYTujXL8Cd esjJd9oI0Q2+/mYNq756WAM3nHFIiJay+4Ma2ISmu37LMLoxfDx598L/UuvSGv+PFZlF H0S/iYUPbtJkPJIFNXQpmcP+MYUfOMWB4b4cDUpCz0fyULK+l+h9NfnAHhFPEi4IR0bo 0pGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ql/ZR4vP"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bb24-20020a17090b009800b0021918bc9a47si14339772pjb.174.2023.01.30.16.05.00; Mon, 30 Jan 2023 16:05:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ql/ZR4vP"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231569AbjAaAAR (ORCPT + 99 others); Mon, 30 Jan 2023 19:00:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231336AbjA3X77 (ORCPT ); Mon, 30 Jan 2023 18:59:59 -0500 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 069751CF6B for ; Mon, 30 Jan 2023 15:59:51 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id p26so25699290ejx.13 for ; Mon, 30 Jan 2023 15:59:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S8yOsvXNT0wYZs16RDglK3sp3e+Qo59M+SSIlkFjXoA=; b=ql/ZR4vPxFMeVS/rUDsykCPRShV/75/pAYjGL4rEk7XfCuAof0LCFETFTH6Nl4dltv VZzIPZ89S4a0bekKWuQ2O2MNlLmquHDulpjFGGhx69jWPNA1dSM7fml2y++YsvFUFTti Xc/QgLIJeYinyXh8qfaquSKxELLs7EqoGy/JIWTxM5EXYWaOfANYRiWhAMpCZZCH5htz nmCAix1DSuSHa6vg3t5rk+zTxAA/zw2ioxd2AKP6mikbDsMEe9t9cuwbCM4RfGm9OunF I7w6uZvhJQ32yQnjqeqR4eRPxY2gPQGNzGhWPNX8xrcwHUvXilkZrrYESilC32cLXS95 IYgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S8yOsvXNT0wYZs16RDglK3sp3e+Qo59M+SSIlkFjXoA=; b=2RtJTYTvC/DLykW/FyE9ZM2F4cTZiAVt4cMD8VO44dKx1dAmv68wPGMoGQztgT4VQM 0B8iP/OJTwfo32PGnM/ElpvmPUN9rVARjJm42/MHvxFHbk3qcv7836HwhUbCPnF221yQ xBLnLz2uf0UYA0Azuex54PsjnEZLXlWK/UzEHO79p3G4SDVV1wGBnwUX+bXjnyEz1KR+ XYwiN/ARfFz2Cj6BbEMbY181PZb+lIdYvoM/YKvqYvJOKUdum74YQa8Xao76qWuvSZFn O5Wa9jr99f+GrMDvyEBMPEU5QHFqRU5KPCXSQmj/sdAxHSg8wjhkgDeVlVPEIINrI35L zK6g== X-Gm-Message-State: AO0yUKV9W9UXnUwjlGJU0X0vp+rAeXSS6pd3xcqn0+LPAn082yvi5EDv 3yvF+2Z5tsrpQc+vZ5L83YXOoQ== X-Received: by 2002:a17:906:a411:b0:878:72f7:bd99 with SMTP id l17-20020a170906a41100b0087872f7bd99mr17016784ejz.6.1675123189330; Mon, 30 Jan 2023 15:59:49 -0800 (PST) Received: from localhost.localdomain (abyl20.neoplus.adsl.tpnet.pl. [83.9.31.20]) by smtp.gmail.com with ESMTPSA id jr23-20020a170906515700b0086f4b8f9e42sm7577751ejc.65.2023.01.30.15.59.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 15:59:49 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 8/8] clk: qcom: Add GPU clock controller driver for SM6115 Date: Tue, 31 Jan 2023 00:59:26 +0100 Message-Id: <20230130235926.2419776-9-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230130235926.2419776-1-konrad.dybcio@linaro.org> References: <20230130235926.2419776-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756494323805179906?= X-GMAIL-MSGID: =?utf-8?q?1756494323805179906?= Add support for the GPU clock controller found on SM6115. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6115.c | 512 ++++++++++++++++++++++++++++++++ 3 files changed, 522 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6115.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a5995ede04e9..825701084323 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -798,6 +798,15 @@ config SM_GCC_8550 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_GPUCC_6115 + tristate "SM6125 Graphics Clock Controller" + select SM_GCC_6115 + depends on ARM64 || COMPILE_TEST + help + Support for the graphics clock controller on SM6115 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_6125 tristate "SM6125 Graphics Clock Controller" select SM_GCC_6125 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 5a1b65b2ac05..9f6b93698ef2 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o +obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c new file mode 100644 index 000000000000..2f54298ed255 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +#define CX_GMU_CBCR_SLEEP_MASK 0xf +#define CX_GMU_CBCR_SLEEP_SHIFT 4 +#define CX_GMU_CBCR_WAKE_MASK 0xf +#define CX_GMU_CBCR_WAKE_SHIFT 8 + +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_AUX, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static struct pll_vco default_vco[] = { + { 1000000000, 2000000000, 0 }, +}; + +static struct pll_vco pll1_vco[] = { + { 500000000, 1000000000, 2 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x3e, + .alpha = 0, + .alpha_hi = 0x80, + .vco_val = 0x0 << 20, + .vco_mask = GENMASK(21, 20), + .alpha_en_mask = BIT(24), + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .aux2_output_mask = BIT(2), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +/* 1200MHz configuration */ +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = default_vco, + .num_vco = ARRAY_SIZE(default_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_aux2[] = { + { 0x0, 1 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_aux2 = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_gpu_cc_pll0_out_aux2, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_aux2), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0_out_aux2", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +/* 640MHz configuration */ +static const struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x21, + .alpha = 0x55555555, + .alpha_hi = 0x55, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = GENMASK(21, 20), + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x100, + .vco_table = pll1_vco, + .num_vco = ARRAY_SIZE(pll1_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll1_out_aux[] = { + { 0x0, 1 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_aux = { + .offset = 0x100, + .post_div_shift = 15, + .post_div_table = post_div_table_gpu_cc_pll1_out_aux, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll1_out_aux), + .width = 3, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1_out_aux", + .parent_hws = (const struct clk_hw*[]) { + &gpu_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = P_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL1_OUT_AUX, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = P_BI_TCXO }, + { .hw = &gpu_cc_pll0_out_aux2.clkr.hw }, + { .hw = &gpu_cc_pll1_out_aux.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(320000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0), + F(465000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0), + F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(980000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_cxo_clk = { + .halt_reg = 0x1060, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_cxo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .resets = (unsigned int []){ GPU_GX_BCR }, + .reset_count = 1, + .pd = { + .name = "gpu_gx_gdsc", + }, + .parent = &gpu_cx_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | SW_RESET | VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm6115_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_PLL1_OUT_AUX] = &gpu_cc_pll1_out_aux.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sm6115_resets[] = { + [GPU_GX_BCR] = { 0x1008 }, +}; + +static struct gdsc *gpu_cc_sm6115_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm6115_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm6115_desc = { + .config = &gpu_cc_sm6115_regmap_config, + .clks = gpu_cc_sm6115_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm6115_clocks), + .resets = gpu_cc_sm6115_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm6115_resets), + .gdscs = gpu_cc_sm6115_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm6115_gdscs), +}; + +static const struct of_device_id gpu_cc_sm6115_match_table[] = { + { .compatible = "qcom,sm6115-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table); + +static int gpu_cc_sm6115_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + unsigned int value, mask; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ + mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; + mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; + value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, mask, value); + + /* Set up PERIPH/MEM retain on the GPU core clock */ + regmap_update_bits(regmap, gpu_cc_gx_gfx3d_clk.halt_reg, + (BIT(14) | BIT(13)), (BIT(14) | BIT(13))); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); +} + +static struct platform_driver gpu_cc_sm6115_driver = { + .probe = gpu_cc_sm6115_probe, + .driver = { + .name = "sm6115-gpucc", + .of_match_table = gpu_cc_sm6115_match_table, + }, +}; +module_platform_driver(gpu_cc_sm6115_driver); + +MODULE_DESCRIPTION("QTI GPU_CC SM6115 Driver"); +MODULE_LICENSE("GPL");