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Sun, 29 Jan 2023 16:57:28 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sun, 29 Jan 2023 16:57:27 -0800 Received: from SDONTHINENI-DESKTOP.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Sun, 29 Jan 2023 16:57:27 -0800 From: Shanker Donthineni To: Thomas Gleixner , Marc Zyngier , Michael Walle CC: Sebastian Andrzej Siewior , Hans de Goede , Wolfram Sang , Shanker Donthineni , Subject: [PATCH 1/5] genirq: Use hlist for managing resend handlers Date: Sun, 29 Jan 2023 18:57:21 -0600 Message-ID: <20230130005725.3517597-2-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230130005725.3517597-1-sdonthineni@nvidia.com> References: <20230130005725.3517597-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EF:EE_|DS7PR12MB8252:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d464cdb-3107-40a0-498d-08db025cf908 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2023 00:57:34.0280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d464cdb-3107-40a0-498d-08db025cf908 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8252 X-Spam-Status: No, score=-0.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756407069113121876?= X-GMAIL-MSGID: =?utf-8?q?1756407069113121876?= The current implementation utilizes a bitmap for managing IRQ resend handlers, which is allocated based on the SPARSE_IRQ/NR_IRQS macros. However, this method may not efficiently utilize memory during runtime, particularly when IRQ_BITMAP_BITS is large. This proposed patch aims to address this issue by using hlist to manage IRQ resend handlers instead of relying on static memory allocation. Additionally, a new function, clear_irq_resend(), is introduced and called from irq_shutdown to ensure a graceful teardown of IRQD. Signed-off-by: Shanker Donthineni --- include/linux/irqdesc.h | 3 +++ kernel/irq/chip.c | 1 + kernel/irq/internals.h | 1 + kernel/irq/irqdesc.c | 6 ++++++ kernel/irq/resend.c | 36 +++++++++++++++++++++--------------- 5 files changed, 32 insertions(+), 15 deletions(-) diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h index 844a8e30e6de..d9451d456a73 100644 --- a/include/linux/irqdesc.h +++ b/include/linux/irqdesc.h @@ -102,6 +102,9 @@ struct irq_desc { int parent_irq; struct module *owner; const char *name; +#ifdef CONFIG_HARDIRQS_SW_RESEND + struct hlist_node resend_node; +#endif } ____cacheline_internodealigned_in_smp; #ifdef CONFIG_SPARSE_IRQ diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 49e7bc871fec..2eac5532c3c8 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -306,6 +306,7 @@ static void __irq_disable(struct irq_desc *desc, bool mask); void irq_shutdown(struct irq_desc *desc) { if (irqd_is_started(&desc->irq_data)) { + clear_irq_resend(desc); desc->depth = 1; if (desc->irq_data.chip->irq_shutdown) { desc->irq_data.chip->irq_shutdown(&desc->irq_data); diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 5fdc0b557579..2fd17057ed4b 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -113,6 +113,7 @@ irqreturn_t handle_irq_event(struct irq_desc *desc); /* Resending of interrupts :*/ int check_irq_resend(struct irq_desc *desc, bool inject); +void clear_irq_resend(struct irq_desc *desc); bool irq_wait_for_poll(struct irq_desc *desc); void __irq_wake_thread(struct irq_desc *desc, struct irqaction *action); diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index fd0996274401..21a968bc468b 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -415,6 +415,9 @@ static struct irq_desc *alloc_desc(int irq, int node, unsigned int flags, desc_set_defaults(irq, desc, node, affinity, owner); irqd_set(&desc->irq_data, flags); kobject_init(&desc->kobj, &irq_kobj_type); +#ifdef CONFIG_HARDIRQS_SW_RESEND + INIT_HLIST_NODE(&desc->resend_node); +#endif return desc; @@ -581,6 +584,9 @@ int __init early_irq_init(void) mutex_init(&desc[i].request_mutex); init_waitqueue_head(&desc[i].wait_for_threads); desc_set_defaults(i, &desc[i], node, NULL, NULL); +#ifdef CONFIG_HARDIRQS_SW_RESEND + INIT_HLIST_NODE(&desc->resend_node); +#endif } return arch_early_irq_init(); } diff --git a/kernel/irq/resend.c b/kernel/irq/resend.c index 0c46e9fe3a89..f2b23871cbef 100644 --- a/kernel/irq/resend.c +++ b/kernel/irq/resend.c @@ -21,8 +21,9 @@ #ifdef CONFIG_HARDIRQS_SW_RESEND -/* Bitmap to handle software resend of interrupts: */ -static DECLARE_BITMAP(irqs_resend, IRQ_BITMAP_BITS); +/* hlist_head to handle software resend of interrupts: */ +static HLIST_HEAD(irq_resend_list); +static DEFINE_RAW_SPINLOCK(irq_resend_lock); /* * Run software resends of IRQ's @@ -30,18 +31,16 @@ static DECLARE_BITMAP(irqs_resend, IRQ_BITMAP_BITS); static void resend_irqs(struct tasklet_struct *unused) { struct irq_desc *desc; - int irq; - - while (!bitmap_empty(irqs_resend, nr_irqs)) { - irq = find_first_bit(irqs_resend, nr_irqs); - clear_bit(irq, irqs_resend); - desc = irq_to_desc(irq); - if (!desc) - continue; + struct hlist_node *n; + + raw_spin_lock_irq(&irq_resend_lock); + hlist_for_each_entry_safe(desc, n, &irq_resend_list, resend_node) { + hlist_del_init(&desc->resend_node); local_irq_disable(); desc->handle_irq(desc); local_irq_enable(); } + raw_spin_unlock_irq(&irq_resend_lock); } /* Tasklet to handle resend: */ @@ -49,8 +48,6 @@ static DECLARE_TASKLET(resend_tasklet, resend_irqs); static int irq_sw_resend(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); - /* * Validate whether this interrupt can be safely injected from * non interrupt context @@ -70,16 +67,25 @@ static int irq_sw_resend(struct irq_desc *desc) */ if (!desc->parent_irq) return -EINVAL; - irq = desc->parent_irq; } - /* Set it pending and activate the softirq: */ - set_bit(irq, irqs_resend); + /* Add to resend_list and activate the softirq: */ + raw_spin_lock(&irq_resend_lock); + hlist_add_head(&desc->resend_node, &irq_resend_list); + raw_spin_unlock(&irq_resend_lock); tasklet_schedule(&resend_tasklet); return 0; } +void clear_irq_resend(struct irq_desc *desc) +{ + raw_spin_lock(&irq_resend_lock); + hlist_del_init(&desc->resend_node); + raw_spin_unlock(&irq_resend_lock); +} #else +void clear_irq_resend(struct irq_desc *desc) {} + static int irq_sw_resend(struct irq_desc *desc) { return -EINVAL; From patchwork Mon Jan 30 00:57:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 50083 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1952852wrn; Sun, 29 Jan 2023 17:18:07 -0800 (PST) X-Google-Smtp-Source: AK7set/ehmXolnCF1g41vI8bOMgLqvSZAcZ1Bofv9y9M4qGkeIIQXJTWfaUN18MYouckG6w5tpFP X-Received: by 2002:a05:6a20:a692:b0:bc:b98c:a8aa with SMTP id ba18-20020a056a20a69200b000bcb98ca8aamr5636477pzb.39.1675041487618; Sun, 29 Jan 2023 17:18:07 -0800 (PST) ARC-Seal: i=2; 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Instead, allocate the necessary NR_IRQ descriptors during the boot time in early_irq_init(). Signed-off-by: Shanker Donthineni --- kernel/irq/irqdesc.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 21a968bc468b..a4911f7ebb07 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -556,27 +556,24 @@ int __init early_irq_init(void) #else /* !CONFIG_SPARSE_IRQ */ -struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = { - [0 ... NR_IRQS-1] = { - .handle_irq = handle_bad_irq, - .depth = 1, - .lock = __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock), - } -}; +static struct irq_desc *irq_descs; int __init early_irq_init(void) { - int count, i, node = first_online_node; + int i, node = first_online_node; struct irq_desc *desc; init_irq_default_affinity(); printk(KERN_INFO "NR_IRQS: %d\n", NR_IRQS); - desc = irq_desc; - count = ARRAY_SIZE(irq_desc); + desc = kmalloc_array(NR_IRQS, sizeof(*desc), GFP_KERNEL | __GFP_ZERO); + if (desc == NULL) + return -ENOMEM; + + irq_descs = desc; - for (i = 0; i < count; i++) { + for (i = 0; i < NR_IRQS; i++) { desc[i].kstat_irqs = alloc_percpu(unsigned int); alloc_masks(&desc[i], node); raw_spin_lock_init(&desc[i].lock); @@ -593,7 +590,7 @@ int __init early_irq_init(void) struct irq_desc *irq_to_desc(unsigned int irq) { - return (irq < NR_IRQS) ? irq_desc + irq : NULL; + return (irq < NR_IRQS) ? irq_descs + irq : NULL; } EXPORT_SYMBOL(irq_to_desc); From patchwork Mon Jan 30 00:57:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 50079 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1946527wrn; Sun, 29 Jan 2023 16:59:01 -0800 (PST) X-Google-Smtp-Source: AMrXdXurDVjUkrKSs3Pq64odN8msGUpsLcsNGc9QUlxfZySa70yDLrVOU+jdSQHYB2fnJsKJc0TU X-Received: by 2002:a62:1488:0:b0:586:b33c:be2 with SMTP id 130-20020a621488000000b00586b33c0be2mr45562057pfu.26.1675040341352; Sun, 29 Jan 2023 16:59:01 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675040341; cv=pass; d=google.com; s=arc-20160816; b=j4ltCu2iPgNR2bPnvc/eAdUJGGFexK2aFtrvCZYOmmVv/7ObjJtBVGh/pJWjHFfyuo zMQhbCI8bBH8tk/d89wWZ6dX3VJQtBRiwQwyM3gKwUz4EdHBhbPgJSjSEPLPjTlsqgKz 1/NUpzLvIOFHU8wRvuY9axQo2dGNK6d8pXOyTBX4+xg5OSTFhUDTl0Np90NE5ifcdFX8 iRB62z5YCsntv7Od3J91MVwdyRArVq0EahZnEOfxA2BQsVf2H43eS21P1j3TX9dEHLkD kALc0NjnewPvD7Q+VOr0vTYKecWPR1BiDu7QI1XVSYtk0eFGHa9lRoZoIMZGN8aEo38t 9nOw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NhmD9vN4o0O4nOaFm8xTn+HlOYw/61BbKs+8PhsBJr4=; b=fht3D+7UIvQyqUwU36bb1QabSM34nYlFrQVjtP09Ba0Lw8bvF8HTV6IPzyWlbTcPLC jnKWHj8P5VXbZJg0ZPRvVXE4YcXdSG6XdmMXD5ATQOJMi5x6oCGQlgRo1qd40kggs6/v x2VO2pumtUheNVJssoEh4ROjkQzSTDWJ75pylh7o16DY9wLuDiupciVgb7/dCwe4emgh XMmaB9vwfGLBQcwrH/UrwfabJoW26mw+RBVp4BOP4zPveY1pSlIvPDg/4cu+1Df/omRI 8OqvLmuKECAPmi1XRhkQ3HXcHoewnaegt21cY+HhqHWuzG1szsw0a9MIT4JHtYAW+vje dYAQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=TNnSEtlx; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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The first function is used to locate available free space for a new IRQ, and the second one is used to find the next valid IRQ. These helper functions will be later modified to utilize the Maple data structure in a later patch. Additionally, in order to align the moving to the new data structure, the IRQ_BITMAP_BITS is renamed to MAX_SPARSE_IRQS. Signed-off-by: Shanker Donthineni --- kernel/irq/internals.h | 4 ++-- kernel/irq/irqdesc.c | 28 +++++++++++++++++++--------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 2fd17057ed4b..5d741b0e7d5e 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -12,9 +12,9 @@ #include #ifdef CONFIG_SPARSE_IRQ -# define IRQ_BITMAP_BITS (NR_IRQS + 8196) +# define MAX_SPARSE_IRQS (NR_IRQS + 8196) #else -# define IRQ_BITMAP_BITS NR_IRQS +# define MAX_SPARSE_IRQS NR_IRQS #endif #define istate core_internal_state__do_not_mess_with_it diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index a4911f7ebb07..aacfb4826c5e 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -131,7 +131,18 @@ int nr_irqs = NR_IRQS; EXPORT_SYMBOL_GPL(nr_irqs); static DEFINE_MUTEX(sparse_irq_lock); -static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS); +static DECLARE_BITMAP(allocated_irqs, MAX_SPARSE_IRQS); + +static int irq_find_free_area(unsigned int from, unsigned int cnt) +{ + return bitmap_find_next_zero_area(allocated_irqs, MAX_SPARSE_IRQS, + from, cnt, 0); +} + +static unsigned int irq_find_next_irq(unsigned int offset) +{ + return find_next_bit(allocated_irqs, nr_irqs, offset); +} #ifdef CONFIG_SPARSE_IRQ @@ -519,7 +530,7 @@ static int alloc_descs(unsigned int start, unsigned int cnt, int node, static int irq_expand_nr_irqs(unsigned int nr) { - if (nr > IRQ_BITMAP_BITS) + if (nr > MAX_SPARSE_IRQS) return -ENOMEM; nr_irqs = nr; return 0; @@ -537,11 +548,11 @@ int __init early_irq_init(void) printk(KERN_INFO "NR_IRQS: %d, nr_irqs: %d, preallocated irqs: %d\n", NR_IRQS, nr_irqs, initcnt); - if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS)) - nr_irqs = IRQ_BITMAP_BITS; + if (WARN_ON(nr_irqs > MAX_SPARSE_IRQS)) + nr_irqs = MAX_SPARSE_IRQS; - if (WARN_ON(initcnt > IRQ_BITMAP_BITS)) - initcnt = IRQ_BITMAP_BITS; + if (WARN_ON(initcnt > MAX_SPARSE_IRQS)) + initcnt = MAX_SPARSE_IRQS; if (initcnt > nr_irqs) nr_irqs = initcnt; @@ -813,8 +824,7 @@ __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, mutex_lock(&sparse_irq_lock); - start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS, - from, cnt, 0); + start = irq_find_free_area(from, cnt); ret = -EEXIST; if (irq >=0 && start != irq) goto unlock; @@ -839,7 +849,7 @@ EXPORT_SYMBOL_GPL(__irq_alloc_descs); */ unsigned int irq_get_next_irq(unsigned int offset) { - return find_next_bit(allocated_irqs, nr_irqs, offset); + return irq_find_next_irq(offset); } struct irq_desc * From patchwork Mon Jan 30 00:57:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 50080 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1947190wrn; Sun, 29 Jan 2023 17:01:06 -0800 (PST) X-Google-Smtp-Source: AK7set/dmFGkn9USrvMx/OaoJrXAUY+J5/hC3sD7zqziFWwStcF08Gw4woqloMBon5w7vVYVWPBS X-Received: by 2002:a05:6a20:12c3:b0:af:dd76:4f0d with SMTP id v3-20020a056a2012c300b000afdd764f0dmr9185789pzg.33.1675040465829; Sun, 29 Jan 2023 17:01:05 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675040465; cv=pass; d=google.com; s=arc-20160816; b=OtUCNJUUiNZ4DdzMKgCQVxfCeVZtey4IycMCvGIoKRO/NG2vahqrnqJgkzg2J7BJMF dR0ksE93dK172zOeTtIaeyOE5zka+3sgUooveo26le5298hr1jgL6ez4lpNQ5Us1BKuA a24oLJOslz7Gq5RmNut4qczPlYB4gR9yq2o0HFMwT0CgkJ/e0m3Sl8h8dyn4ejjg80po lYNlpqWSfzveBKERgU/Ak73JVGfgZGBXLMaSQG7qgxRefThKX2zpGu48AhxSYTTR9+TK HIQH1eO6+mqsP/B1fsUw/fMbxCGt5fvHFMfgwxhJsUH1LfY5Lylk1MgEu2Mbi2pvNfNB WRCw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aul/Qf7cN6yY2oVjkqrNPbt3USVR3a1xYMDesa8HJDM=; b=Rz1SfaBvjy5YuPAtrEWXzE51QhjhO5+jL3pZxDGv9wpKv1DxgMlFO2NCe/GHHYj6mv 22Ucq91tuAUPts/uwChEcb0tDSkFxISsoPJt0byAE2FLoHNKHBM5yYnSC3F0rc3t34uE LAH/bGE7jbTwW22X9COD9dDaFQ4WVnMyCRuD6IgNniF8pOTG3u36gj6uSfVWVNq0RM6U V98kK4zg52sKdD6xDNzJ9fvzG7wnUHqnO5B/PPpClfgYDIsug8ilq7sNs3dryVE+K2Lp wrqaynikmkX1LZDFTzSNGCl6BJQ1IJYaXVGwgNCjFa8Id7QOQhds4tGLcouWv0ev1fku rMDQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=KqJqmywA; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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However, the SPARSEIRQ version of the function can be safely used in both cases, as nr_irqs = MAX_SPARSE_IRQS = NR_IRQS. Signed-off-by: Shanker Donthineni --- kernel/irq/irqdesc.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index aacfb4826c5e..247a0718d028 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -144,6 +144,14 @@ static unsigned int irq_find_next_irq(unsigned int offset) return find_next_bit(allocated_irqs, nr_irqs, offset); } +static int irq_expand_nr_irqs(unsigned int nr) +{ + if (nr > MAX_SPARSE_IRQS) + return -ENOMEM; + nr_irqs = nr; + return 0; +} + #ifdef CONFIG_SPARSE_IRQ static void irq_kobj_release(struct kobject *kobj); @@ -528,14 +536,6 @@ static int alloc_descs(unsigned int start, unsigned int cnt, int node, return -ENOMEM; } -static int irq_expand_nr_irqs(unsigned int nr) -{ - if (nr > MAX_SPARSE_IRQS) - return -ENOMEM; - nr_irqs = nr; - return 0; -} - int __init early_irq_init(void) { int i, initcnt, node = first_online_node; @@ -630,11 +630,6 @@ static inline int alloc_descs(unsigned int start, unsigned int cnt, int node, return start; } -static int irq_expand_nr_irqs(unsigned int nr) -{ - return -ENOMEM; -} - void irq_mark_irq(unsigned int irq) { mutex_lock(&sparse_irq_lock); From patchwork Mon Jan 30 00:57:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 50081 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1951104wrn; Sun, 29 Jan 2023 17:12:35 -0800 (PST) X-Google-Smtp-Source: AK7set/31qg5Qp08Tn0rb56A6odVqC1mPFsfSLqBEp4NuGgtYvux/+bntrShOO6OQHno5IScGkF/ X-Received: by 2002:a17:902:d4cf:b0:194:d1ee:954 with SMTP id o15-20020a170902d4cf00b00194d1ee0954mr7484448plg.7.1675041154670; Sun, 29 Jan 2023 17:12:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675041154; cv=pass; d=google.com; s=arc-20160816; b=Zl2/s3TlZ1rZJLE4/AwOz1W+jzHpH/f6PRM0smuC8RgFBpfXSDy4v9p/mH5IVc6uo8 bKrgdzvNcxqQ0Uxa9f9yBKo/yti3eM+zNjbhLivaVa7JKOhXymrtOp91KvAIpA6RMyAO iVHACf6K/8GcOeVe+Rz94sQ8ahgsv7gwpZ/sRbwMeFnKI7Nf0vGXkb/HFnNhb2bh2a4c Zc0Vre5/Oq/C9WBsSbZ2skBzaQs1dyK2lDf09oMQdb1Ybx1j0wAwtOnuqnmOY1jXTBE+ AY0ne2MSZGV2XyIxONFKk9Zbaj/ZmVousMcBr3aIZZPi2qGgBIuYAEwftsi1FxQwQhCt SwOA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9v9WfyT8WB4VHt8ZMWtIo74b8GKNJCGheVaBwTRAisw=; b=A8TMUMIkt7jYBm9SCs2Bo3peDukuXe0Iz3kxkhWD0XR2sndcw2yKO+03WMuYBbNUSi 1xIq8BOsRyAU7K7tyskdN88WN4xk/xloJJwKlYKnq7+Jo2ipqwK1zn7UrOoSpZ5w2IMs aicSN6rYZAvO2YJ+xz49OPpCagxapD4ShXn2STR7kZPHZv+C+vVmj/OrzU+yEt0JPF+4 zmi4CGy/XyFd8sNedCrjviqXqeB3vnbbQn/tLLVK2Ib+PVFaLXARDULPYs3y/DZyKF0D Z922HlNEC491hoYx0Of94cKIVkNnLKQ8n9Gi81z2GqjQ7eWZzCPYwKi+VVLiyGhgt7XP H/1w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=jqnTxu+I; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2023 00:57:41.8921 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85e95a8d-3bdd-4ca5-ccf8-08db025cfdc1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4254 X-Spam-Status: No, score=-0.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756407953959206193?= X-GMAIL-MSGID: =?utf-8?q?1756407953959206193?= The current implementation uses a static bitmap and a radix tree to manage IRQ allocation and irq_desc pointer store respectively. However, the size of the bitmap is constrained by the build time macro MAX_SPARSE_IRQS, which may not be sufficient to support the high-end servers, particularly those with GICv4.1 hardware, which require a large interrupt space to cover LPIs and vSGIs The maple tree is a highly efficient data structure for storing non-overlapping ranges and can handle a large number of entries, up to ULONG_MAX. It can be utilized for both storing IRQD and identifying available free spaces. The IRQD management can be simplified by switching to a maple tree data structure, which offers greater flexibility and scalability. To support modern servers, the maximum number of IRQs has been increased to INT_MAX, which provides a more adequate value than the previous limit of NR_IRQS+8192. Signed-off-by: Shanker Donthineni Signed-off-by: Thomas Gleixner --- kernel/irq/internals.h | 2 +- kernel/irq/irqdesc.c | 51 ++++++++++++++++++++++++------------------ 2 files changed, 30 insertions(+), 23 deletions(-) diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 5d741b0e7d5e..e35de737802c 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -12,7 +12,7 @@ #include #ifdef CONFIG_SPARSE_IRQ -# define MAX_SPARSE_IRQS (NR_IRQS + 8196) +# define MAX_SPARSE_IRQS INT_MAX #else # define MAX_SPARSE_IRQS NR_IRQS #endif diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 247a0718d028..06be5f924a7c 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "internals.h" @@ -131,17 +132,37 @@ int nr_irqs = NR_IRQS; EXPORT_SYMBOL_GPL(nr_irqs); static DEFINE_MUTEX(sparse_irq_lock); -static DECLARE_BITMAP(allocated_irqs, MAX_SPARSE_IRQS); +static struct maple_tree sparse_irqs = MTREE_INIT_EXT(sparse_irqs, + MT_FLAGS_ALLOC_RANGE | + MT_FLAGS_LOCK_EXTERN | + MT_FLAGS_USE_RCU, sparse_irq_lock); static int irq_find_free_area(unsigned int from, unsigned int cnt) { - return bitmap_find_next_zero_area(allocated_irqs, MAX_SPARSE_IRQS, - from, cnt, 0); + MA_STATE(mas, &sparse_irqs, 0, 0); + + if (mas_empty_area(&mas, from, MAX_SPARSE_IRQS, cnt)) + return -ENOSPC; + return mas.index; } static unsigned int irq_find_next_irq(unsigned int offset) { - return find_next_bit(allocated_irqs, nr_irqs, offset); + struct irq_desc *desc = mt_next(&sparse_irqs, offset, nr_irqs); + + return desc ? irq_desc_get_irq(desc) : nr_irqs; +} + +static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) +{ + MA_STATE(mas, &sparse_irqs, irq, irq); + WARN_ON(mas_store_gfp(&mas, desc, GFP_KERNEL) != 0); +} + +static void delete_irq_desc(unsigned int irq) +{ + MA_STATE(mas, &sparse_irqs, irq, irq); + mas_erase(&mas); } static int irq_expand_nr_irqs(unsigned int nr) @@ -363,26 +384,14 @@ static void irq_sysfs_del(struct irq_desc *desc) {} #endif /* CONFIG_SYSFS */ -static RADIX_TREE(irq_desc_tree, GFP_KERNEL); - -static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) -{ - radix_tree_insert(&irq_desc_tree, irq, desc); -} - struct irq_desc *irq_to_desc(unsigned int irq) { - return radix_tree_lookup(&irq_desc_tree, irq); + return mtree_load(&sparse_irqs, irq); } #ifdef CONFIG_KVM_BOOK3S_64_HV_MODULE EXPORT_SYMBOL_GPL(irq_to_desc); #endif -static void delete_irq_desc(unsigned int irq) -{ - radix_tree_delete(&irq_desc_tree, irq); -} - #ifdef CONFIG_SMP static void free_masks(struct irq_desc *desc) { @@ -527,7 +536,6 @@ static int alloc_descs(unsigned int start, unsigned int cnt, int node, irq_sysfs_add(start + i, desc); irq_add_debugfs_entry(start + i, desc); } - bitmap_set(allocated_irqs, start, cnt); return start; err: @@ -559,7 +567,6 @@ int __init early_irq_init(void) for (i = 0; i < initcnt; i++) { desc = alloc_desc(i, node, 0, NULL, NULL); - set_bit(i, allocated_irqs); irq_insert_desc(i, desc); } return arch_early_irq_init(); @@ -613,6 +620,7 @@ static void free_desc(unsigned int irq) raw_spin_lock_irqsave(&desc->lock, flags); desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL, NULL); raw_spin_unlock_irqrestore(&desc->lock, flags); + delete_irq_desc(irq); } static inline int alloc_descs(unsigned int start, unsigned int cnt, int node, @@ -625,15 +633,15 @@ static inline int alloc_descs(unsigned int start, unsigned int cnt, int node, struct irq_desc *desc = irq_to_desc(start + i); desc->owner = owner; + irq_insert_desc(start + i, desc); } - bitmap_set(allocated_irqs, start, cnt); return start; } void irq_mark_irq(unsigned int irq) { mutex_lock(&sparse_irq_lock); - bitmap_set(allocated_irqs, irq, 1); + irq_insert_desc(irq, irq_descs + irq); mutex_unlock(&sparse_irq_lock); } @@ -777,7 +785,6 @@ void irq_free_descs(unsigned int from, unsigned int cnt) for (i = 0; i < cnt; i++) free_desc(from + i); - bitmap_clear(allocated_irqs, from, cnt); mutex_unlock(&sparse_irq_lock); } EXPORT_SYMBOL_GPL(irq_free_descs);