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Wed, 25 Jan 2023 22:54:19 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-trace-kernel@vger.kernel.org, linux-kernel@vger.kernel.org, mhiramat@kernel.org, rostedt@goodmis.org, alistair@popple.id.au, joel@jms.id.au, jk@ozlabs.org, andrew@aj.id.au, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, eajames@linux.ibm.com Subject: [PATCH v2 1/2] dt-bindings: fsi: Document the IBM I2C Responder virtual FSI master Date: Wed, 25 Jan 2023 16:54:15 -0600 Message-Id: <20230125225416.4074040-2-eajames@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230125225416.4074040-1-eajames@linux.ibm.com> References: <20230125225416.4074040-1-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: kSOOYgWDy8O8nncf1lF0VFBXtiL_klMa X-Proofpoint-ORIG-GUID: kSOOYgWDy8O8nncf1lF0VFBXtiL_klMa X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-25_13,2023-01-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301250200 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756037052570736321?= X-GMAIL-MSGID: =?utf-8?q?1756037052570736321?= The I2C Responder translates I2C commands to CFAM or SCOM operations, effectively implementing an FSI master. Signed-off-by: Eddie James --- .../bindings/fsi/ibm,i2cr-fsi-master.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml diff --git a/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml b/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml new file mode 100644 index 000000000000..fa768e773adc --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/ibm,i2cr-fsi-master.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/ibm,i2cr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM I2C Responder virtual FSI master + +maintainers: + - Eddie James + +description: | + The I2C Responder (I2CR) is a an I2C device that's connected to an FSI CFAM + (see fsi.txt). The I2CR translates I2C bus operations to FSI CFAM reads and + writes or SCOM operations, thereby acting as an FSI master. + +properties: + compatible: + enum: + - ibm,i2cr-fsi-master + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + }; + }; From patchwork Wed Jan 25 22:54:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 48407 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp525993wrn; Wed, 25 Jan 2023 14:56:29 -0800 (PST) X-Google-Smtp-Source: AMrXdXuqgRVs98G3Lmxfbg5nfqOcKWqfBTYYfzY5h/4UpvQw/+X0cOsBD3m9GLiBPZN2rdegVLLa X-Received: by 2002:a17:906:bc58:b0:872:2cc4:6882 with SMTP id s24-20020a170906bc5800b008722cc46882mr37850119ejv.58.1674687389839; Wed, 25 Jan 2023 14:56:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674687389; cv=none; d=google.com; s=arc-20160816; b=CrGhjlIjsaKANXyGHo5JPqY5yko6UT7NFa0NCrii/nR+FU3dw6tvu0MEcRVUNSU4Yz Vl+39CJj7LOkwDRD/cNZD6V5Y7SZEVtf+JUVhcqPvS4HIg4swhjAWbf6rLsr6MslQ9M7 ImuEXoBhUrXBCGbI2MFT5VvIoLjxlrP2EzUZZ5v+Ocipv6GHtxgKfgRwXFT65tVImGM3 ZaUhRVKvtdC/d8/tschE/khz9JEnXQGRnzdEVlm2WKvO8HRWGxY3EzKdYXBJgehUiKA3 NlKwUfzBPF50uVcOhN2vENwkS1z6sPuugh63YIeHb5vMaRlhtqXzxYqhx+vVQqdMB7b8 nH5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QwlJo+ZY/eY+rklSkxDhRuRP/i9uG3s2ks085YAnBfQ=; b=xcoi8jkj5ltmAMjuDEpCh5U+UYg00puPJQOWsDHA5gu7gmF7FzOBtV2/SU2+qNjqKU JkoJ9tjKH6OjjgNq+AgOrLzJo/pyx1ZVkWUlaaJM7IWu6nlr23ADFY32xgKcjmjPmmoT xINxaynitIhLagtMxF0JzeK0OQRBy0Z12Y48B7ks7LjXUDhSVbuIopxqsZv4NDq79CJx xDa/mJnIhqC+kS2EMQbnFX2KK2ia2+7SGYGY1s9J2jmgqZYDnlVeRDx0ICyjQbsnV6j/ 8UBEItV8oSilx6661vj9VR0sufNyjlXJwyU+D+Od+3gDqhVLZFa0a574ZDIyZ8lEm+Un dk7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=HUKi1d+a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from out1.vger.email (out1.vger.email. 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Wed, 25 Jan 2023 22:54:21 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-trace-kernel@vger.kernel.org, linux-kernel@vger.kernel.org, mhiramat@kernel.org, rostedt@goodmis.org, alistair@popple.id.au, joel@jms.id.au, jk@ozlabs.org, andrew@aj.id.au, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, eajames@linux.ibm.com Subject: [PATCH v2 2/2] fsi: Add IBM I2C Responder virtual FSI master Date: Wed, 25 Jan 2023 16:54:16 -0600 Message-Id: <20230125225416.4074040-3-eajames@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230125225416.4074040-1-eajames@linux.ibm.com> References: <20230125225416.4074040-1-eajames@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: HLvZkAnHh_ZjV0PMnKuxU1p2Q2Zr8XRK X-Proofpoint-ORIG-GUID: HLvZkAnHh_ZjV0PMnKuxU1p2Q2Zr8XRK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-25_13,2023-01-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 malwarescore=0 mlxscore=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301250200 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755474123291047604?= X-GMAIL-MSGID: =?utf-8?q?1756037004419261499?= The I2C Responder (I2CR) is an I2C device that translates I2C commands to CFAM or SCOM operations, effectively implementing an FSI master and bus. Signed-off-by: Eddie James --- drivers/fsi/Kconfig | 9 + drivers/fsi/Makefile | 1 + drivers/fsi/fsi-master-i2cr.c | 225 +++++++++++++++++++++++++ include/trace/events/fsi_master_i2cr.h | 96 +++++++++++ 4 files changed, 331 insertions(+) create mode 100644 drivers/fsi/fsi-master-i2cr.c create mode 100644 include/trace/events/fsi_master_i2cr.h diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig index e6668a869913..999be82720c5 100644 --- a/drivers/fsi/Kconfig +++ b/drivers/fsi/Kconfig @@ -62,6 +62,15 @@ config FSI_MASTER_ASPEED Enable it for your BMC kernel in an OpenPower or IBM Power system. +config FSI_MASTER_I2CR + tristate "IBM I2C Responder virtual FSI master" + depends on I2C + help + This option enables a virtual FSI master in order to access a CFAM + behind an IBM I2C Responder (I2CR) chip. The I2CR is an I2C device + that translates I2C commands to CFAM or SCOM operations, effectively + implementing an FSI master and bus. + config FSI_SCOM tristate "SCOM FSI client device driver" help diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile index da218a1ad8e1..34dbaa1c452e 100644 --- a/drivers/fsi/Makefile +++ b/drivers/fsi/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_FSI) += fsi-core.o obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o obj-$(CONFIG_FSI_MASTER_ASPEED) += fsi-master-aspeed.o obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o +obj-$(CONFIG_FSI_MASTER_I2CR) += fsi-master-i2cr.o obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o obj-$(CONFIG_FSI_SCOM) += fsi-scom.o obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o diff --git a/drivers/fsi/fsi-master-i2cr.c b/drivers/fsi/fsi-master-i2cr.c new file mode 100644 index 000000000000..0eadc9b26063 --- /dev/null +++ b/drivers/fsi/fsi-master-i2cr.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) IBM Corporation 2023 */ + +#include +#include +#include +#include +#include +#include + +#include "fsi-master.h" + +#define CREATE_TRACE_POINTS +#include + +#define I2CR_ADDRESS_CFAM(a) ((a) >> 2) +#define I2CR_STATUS 0x30001 +#define I2CR_STATUS_ERR BIT_ULL(61) +#define I2CR_ERROR 0x30002 + +struct fsi_master_i2cr { + struct fsi_master master; + struct mutex lock; /* protect HW access */ + struct i2c_client *client; +}; + +static bool i2cr_check_parity(u32 v, bool parity) +{ + u32 i; + + for (i = 0; i < 32; ++i) { + if (v & (1 << i)) + parity = !parity; + } + + return parity; +} + +static __be32 i2cr_get_command(u32 address, bool parity) +{ + __be32 command; + + address <<= 1; + + if (i2cr_check_parity(address, parity)) + address |= 1; + + command = cpu_to_be32(address); + trace_i2cr_command((__force uint32_t)command); + + return command; +} + +static int i2cr_transfer(struct i2c_client *client, u32 address, __be64 *data) +{ + struct i2c_msg msgs[2]; + __be32 command; + int ret; + + command = i2cr_get_command(address, true); + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(command); + msgs[0].buf = (__u8 *)&command; + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = sizeof(*data); + msgs[1].buf = (__u8 *)data; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret == 2) + return 0; + + trace_i2cr_i2c_error(ret); + + if (ret < 0) + return ret; + + return -EIO; +} + +static int i2cr_check_status(struct i2c_client *client) +{ + __be64 status_be = 0; + u64 status; + int ret; + + ret = i2cr_transfer(client, I2CR_STATUS, &status_be); + if (ret) + return ret; + + status = be64_to_cpu(status_be); + if (status & I2CR_STATUS_ERR) { + __be64 error_be = 0; + u64 error; + + i2cr_transfer(client, I2CR_ERROR, &error_be); + error = be64_to_cpu(error_be); + trace_i2cr_status_error(status, error); + dev_err(&client->dev, "status:%016llx error:%016llx\n", status, error); + return -EREMOTEIO; + } + + trace_i2cr_status(status); + return 0; +} + +static int i2cr_read(struct fsi_master *master, int link, uint8_t id, uint32_t addr, void *val, + size_t size) +{ + struct fsi_master_i2cr *i2cr = container_of(master, struct fsi_master_i2cr, master); + __be64 data = 0; + int ret; + + if (link || id || (addr & 0xffff0000) || !(size == 1 || size == 2 || size == 4)) + return -EINVAL; + + mutex_lock(&i2cr->lock); + + ret = i2cr_transfer(i2cr->client, I2CR_ADDRESS_CFAM(addr), &data); + if (ret) + goto unlock; + + ret = i2cr_check_status(i2cr->client); + if (ret) + goto unlock; + + trace_i2cr_read(addr, size, (__force uint32_t)data); + memcpy(val, &data, size); + +unlock: + mutex_unlock(&i2cr->lock); + return ret; +} + +static int i2cr_write(struct fsi_master *master, int link, uint8_t id, uint32_t addr, + const void *val, size_t size) +{ + struct fsi_master_i2cr *i2cr = container_of(master, struct fsi_master_i2cr, master); + struct { + __be32 command; + u32 val; + u32 rsvd; + } __packed data = { 0, 0, 0 }; + int ret; + + if (link || id || (addr & 0xffff0000) || !(size == 1 || size == 2 || size == 4)) + return -EINVAL; + + memcpy(&data.val, val, size); + data.command = i2cr_get_command(I2CR_ADDRESS_CFAM(addr), + i2cr_check_parity(data.val, true)); + + mutex_lock(&i2cr->lock); + + ret = i2c_master_send(i2cr->client, (const char *)&data, sizeof(data)); + if (ret == sizeof(data)) { + ret = i2cr_check_status(i2cr->client); + if (!ret) + trace_i2cr_write(addr, size, data.val); + } else { + trace_i2cr_i2c_error(ret); + + if (ret >= 0) + ret = -EIO; + } + + mutex_unlock(&i2cr->lock); + return ret; +} + +static int i2cr_probe(struct i2c_client *client) +{ + struct fsi_master_i2cr *i2cr; + int ret; + + i2cr = devm_kzalloc(&client->dev, sizeof(*i2cr), GFP_KERNEL); + if (!i2cr) + return -ENOMEM; + + i2cr->master.dev.parent = &client->dev; + i2cr->master.dev.of_node = of_node_get(dev_of_node(&client->dev)); + + i2cr->master.n_links = 1; + i2cr->master.read = i2cr_read; + i2cr->master.write = i2cr_write; + + mutex_init(&i2cr->lock); + i2cr->client = client; + + ret = fsi_master_register(&i2cr->master); + if (ret) + return ret; + + i2c_set_clientdata(client, i2cr); + return 0; +} + +static void i2cr_remove(struct i2c_client *client) +{ + struct fsi_master_i2cr *i2cr = i2c_get_clientdata(client); + + fsi_master_unregister(&i2cr->master); +} + +static const struct of_device_id i2cr_i2c_ids[] = { + { .compatible = "ibm,i2cr-fsi-master", }, + { } +}; +MODULE_DEVICE_TABLE(of, i2cr_i2c_ids); + +static struct i2c_driver i2cr_driver = { + .probe_new = i2cr_probe, + .remove = i2cr_remove, + .driver = { + .name = "fsi-master-i2cr", + .of_match_table = i2cr_i2c_ids, + }, +}; + +module_i2c_driver(i2cr_driver) + +MODULE_AUTHOR("Eddie James "); +MODULE_DESCRIPTION("IBM I2C Responder virtual FSI master driver"); +MODULE_LICENSE("GPL"); diff --git a/include/trace/events/fsi_master_i2cr.h b/include/trace/events/fsi_master_i2cr.h new file mode 100644 index 000000000000..7b53c6a35bc7 --- /dev/null +++ b/include/trace/events/fsi_master_i2cr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM fsi_master_i2cr + +#if !defined(_TRACE_FSI_MASTER_I2CR_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_FSI_MASTER_I2CR_H + +#include + +TRACE_EVENT(i2cr_command, + TP_PROTO(uint32_t command), + TP_ARGS(command), + TP_STRUCT__entry( + __field(uint32_t, command) + ), + TP_fast_assign( + __entry->command = command; + ), + TP_printk("command:%08x", __entry->command) +); + +TRACE_EVENT(i2cr_i2c_error, + TP_PROTO(int rc), + TP_ARGS(rc), + TP_STRUCT__entry( + __field(int, rc) + ), + TP_fast_assign( + __entry->rc = rc; + ), + TP_printk("rc:%d", __entry->rc) +); + +TRACE_EVENT(i2cr_read, + TP_PROTO(uint32_t addr, size_t size, uint64_t result), + TP_ARGS(addr, size, result), + TP_STRUCT__entry( + __field(uint32_t, addr) + __field(size_t, size) + __field(uint64_t, result) + ), + TP_fast_assign( + __entry->addr = addr; + __entry->size = size; + __entry->result = result; + ), + TP_printk("addr:%08x size:%zu result:%016llx", __entry->addr, __entry->size, + __entry->result) +); + +TRACE_EVENT(i2cr_status, + TP_PROTO(uint64_t status), + TP_ARGS(status), + TP_STRUCT__entry( + __field(uint32_t, status) + ), + TP_fast_assign( + __entry->status = status >> 32; + ), + TP_printk("status:%08x", __entry->status) +); + +TRACE_EVENT(i2cr_status_error, + TP_PROTO(uint64_t status, uint64_t error), + TP_ARGS(status, error), + TP_STRUCT__entry( + __field(uint64_t, error) + __field(uint32_t, status) + ), + TP_fast_assign( + __entry->error = error; + __entry->status = status >> 32; + ), + TP_printk("status:%08x error:%016llx", __entry->status, __entry->error) +); + +TRACE_EVENT(i2cr_write, + TP_PROTO(uint32_t addr, uint32_t val, size_t size), + TP_ARGS(addr, val, size), + TP_STRUCT__entry( + __field(uint32_t, addr) + __field(uint32_t, val) + __field(size_t, size) + ), + TP_fast_assign( + __entry->addr = addr; + __entry->val = val; + __entry->size = size; + ), + TP_printk("addr:%08x val:%08x size:%zu", __entry->addr, __entry->val, __entry->size) +); + +#endif + +#include