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Signed-off-by: Bernhard Rosenkränzer Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 2275e5d93721b..ae12b1cab9fbd 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -244,6 +244,10 @@ properties: - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8365-evk + - const: mediatek,mt8365 - items: - enum: - mediatek,mt8516-pumpkin From patchwork Wed Jan 25 14:34:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 48164 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:fc46:0:0:0:0:0 with SMTP id e6csp335498wrs; Wed, 25 Jan 2023 06:36:44 -0800 (PST) X-Google-Smtp-Source: AMrXdXvRqrzH795QqoVaGiYGAccFtrzHjeAv8Hs4bxav9ph4XJ7T0je4Z82cQnddUs8gAUyYDS/8 X-Received: by 2002:aa7:9259:0:b0:58d:948f:2acd with SMTP id 25-20020aa79259000000b0058d948f2acdmr32630996pfp.33.1674657403196; Wed, 25 Jan 2023 06:36:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674657403; cv=none; d=google.com; s=arc-20160816; b=CljWT459+/twlvzUzzWYXGd76KJ7RolLBQORk+G5VZUYmWggGtmIcmrYjAmwSNkYj3 Q7SQ2zs4qnmg18hFXxPGA5UZ9NHozfB8XBILc8ebmhSdr3/7CsPEpPhrUynsKRO+T3/9 Ot457vxJJXEmYvxrLT1LNpt6Yh37K7Fu4/O5g4cGqwDVRXmM5QMY4pDdO665yBGyEm+S YeQirnPRNQjOKk9YDbswQMHcoxL3fWKz7emGik+x7cpeXt6VzyqSG6Yn0MOdDK4/PQrp hgd6btzQ9fndV3AVFtkmlErbrO9scXgmM8GoIV+E3t2GJ9mCfWMFGO3QNugqXCji6D19 DgGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bNAP8XOhS4LLuKpYRGvk3aTC1kcIWQVhxMWfMNAmKbo=; b=c/d5KQVbogk3BuT4JINZSLUsuuGf2712n/rmuZewSIlcsiB83Rf/DPslCCqpzJNZiP G1Q87GiDbuIYehU994TWMcMLME1NredO7/rb78PK+rb6MOp9UwCqA0kItsZxEXZd/L/c +j0/MuJFehR7PWmSBDcHR+4S9aKiQ6N1Ev18SxA/+zhf18wQH4iHCbpydGudUpaKAJOO PvuQLqR81tJmqmiVERaD8dtUp22dDmQ+YEAokiEAVuSlXmxTroaxQlTZplPoVisZebxQ CqvCpkSFRP9EjE9kwUOjhfg0bK/oe6AEJHh/CK4ERBCYXD1HzqMV/EEdLtuyMiYrEYhC WVVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=XI56FY3z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bernhard Rosenkränzer Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 84ced3f4179b9..3ffc60184e445 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -25,6 +25,7 @@ Required properties: "mediatek,mt6577-sysirq": for MT6577 "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 + "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. - reg: Physical base address of the intpol registers and length of memory From patchwork Wed Jan 25 14:34:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 48166 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp307111wrn; Wed, 25 Jan 2023 06:37:03 -0800 (PST) X-Google-Smtp-Source: AMrXdXt38ejjac8SQEdKr3gmeHLe9eWeT8WRuKg+Aq5vk5rFdKzB9uBKj1vBP/amdx9NnoixO6zt X-Received: by 2002:a05:6a00:4c0b:b0:58d:acc6:fd2a with SMTP id ea11-20020a056a004c0b00b0058dacc6fd2amr34886277pfb.25.1674657423494; Wed, 25 Jan 2023 06:37:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674657423; cv=none; d=google.com; s=arc-20160816; b=WKa9ItKbC3/Cu4RQSdiDI/JPTwtBnc5E2zt7M7phMdUslvjHzGmuISQvoemAycelS+ 8+6rxD1RUjh0EKUAmwDFw4Sx47zLTAB4IyJWnA/s7RyEK9yVFcETcOCbmhVHLQR0yU3c ef3bTY0E1gvIr/K28RwqbcCAs+6DTFX+TMUC1EfNYLm+N3zggkxeqAMLYBg6waFxbHXj PrCuaZlRARbRq3gixlS6GUUF3gBC0YOxnEVDWe/lYPidU2d20wJWvR01U151q5Ach3JQ 0kh4yF/lvstMlievkBajaoZ+9tKiSnmx41HJbHCS51NjYC8kPyu2k1plgwK4t/EKzylM AlYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tN16lN3tQI1TVAWs7NSp7WntR2GpAGJj0GT7j6mK3Fw=; b=EDzaLtRBHx7VCY+7q+YZXKF+W0ysx8nBwioiNc26CXFYEnsAz9E4FjyUmVitOYgugI /SkCrWIuPv4JLetHFfnhKlmG4O7ww81ZzvV9AlH2rVhfiKr7jJQTwv/mDXKU2pUVQibo Jm+mUph2NVStyP8qFReG+dF5mXbdwCVHkNSa2WScdDSP08mfKh8o0gXDySMbNk+YfLjv Tu1WF0RldzhfCpjKYPo2iI9gY0KsD3Q8pwaWNG1LuhVLkiMwr/UpaAKff6za2F+x+p1a FgR9E6Z5Jfk57RRmDZkPEmr4mFBBRfTSKFLGa8GHf7VI6i0nNfGj8QdQOtt4HazLDFU0 YUcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=of6sbOD2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bernhard Rosenkränzer Reviewed-by: Rob Herring --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 197 ++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml new file mode 100644 index 0000000000000..4b96884a1afc7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao + - Bernhard Rosenkränzer + +description: | + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + "-pins$": + type: object + additionalProperties: false + patternProperties: + "pins$": + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in -pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pull up + settings for 2 pull resistors, R0 and R1. User can configure those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty cycle + when asserted (high pulse width adjustment). Valid arguments are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + pio-pins { + pins { + pinmux = , ; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + bias-pull-up; + }; + }; + }; + }; From patchwork Wed Jan 25 14:34:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 48165 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp307107wrn; Wed, 25 Jan 2023 06:37:03 -0800 (PST) X-Google-Smtp-Source: AK7set8C3x6RKDd/kUtFSAFAYZOPQ4CN4y+AUn42k7l5pQKAp29YgngHvTy7HIOQ9xzm3HfmCMJH X-Received: by 2002:a62:5e86:0:b0:590:7558:5ad6 with SMTP id s128-20020a625e86000000b0059075585ad6mr339833pfb.30.1674657422782; Wed, 25 Jan 2023 06:37:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674657422; cv=none; d=google.com; s=arc-20160816; b=kJ9OQWmDrEgBLQ4LtKsjHukkcrTSZZGJrdD4IQySRm4Qzf3MAe8RWwzEQ84vozGmRw yS/LtAr+CI38AexL/BJq6Ky2i7hzvtdZQSr9PEJ18LlAhqgcGGM38e94z+QkDI9rbgcN nuwnrkrwasmSOw+4wxSS5N6UIVlvGki23WgfL+KRsSNndt5CEplNMOclFwl550BJkJrm NHlGhuEOHsViL8L9/zbEVwG0r18zWMkd5N6LeFDQOY71oNr6buACG4e0TzgbkTi/xwM5 FYTtw4X2Wq0a+2nGMV4somhMrEjEP5Dy7OVLh/2E73R1AJUsz6sWfYBK02xT4bEKA0tL msBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mwIzfbsFdCDai/q3cnqayXJcFTx4vajk+OuUztkusTY=; b=KzwrOYKhyqLkSr3MfIAEsfPsBkv4Uvvtn4Aw+vR5we/R3cwxC3PdMTfW7cMusCZFl4 steK9TaivswsAVRmJg6azQPmnf2MzURjhJkLXORea5HNy+VP9JsU6RpincN2C03mHq+r wYy+2+sHg0a42w/OBYWri+IwDYwyHcjFRqhj7YcSo+jGs6blUmo6kfX8qcJ+QEmIQOU1 /kgO5G7Rj8kLTOcFQB4MD+ATJs39FlLd3pkHUy0HvRGj1HPjGZyprbPGuDzQHG0YwdGz xnskvY3wIAXDrkQ9yqo48Wm/2/HdQ+UF3d2tbN9on2j08il6+HyfYTTIC63aYOOABLyj zb/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=qRmANpnH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkränzer Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chunfeng Yun --- Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml index 7168110e2f9de..d2655173e108c 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8188-mtu3 - mediatek,mt8192-mtu3 - mediatek,mt8195-mtu3 + - mediatek,mt8365-mtu3 - const: mediatek,mtu3 reg: From patchwork Wed Jan 25 14:35:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 48168 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp307121wrn; Wed, 25 Jan 2023 06:37:05 -0800 (PST) X-Google-Smtp-Source: AMrXdXtQeSwqu0QDLED6OLcnBS3jjex/errSz1+6DhJf9F1agS1olcY2a6glZtArXsNzhxGIuQa4 X-Received: by 2002:a05:6a20:4392:b0:9d:efbf:48d7 with SMTP id i18-20020a056a20439200b0009defbf48d7mr37625969pzl.27.1674657425388; Wed, 25 Jan 2023 06:37:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674657425; cv=none; d=google.com; s=arc-20160816; b=E6UiRUX15uTiDToPfMD4HwRpC2c2NWKtGUGUZ7EDzF33odPxmGCgTwaUepc+e5bcpP O6b1CyN0gGcAOgM4Zm6irKV4Bbz7WLhp42Osu+B6Hvg0F4KTPVbhylMBeLRC/7eWZwdV AM3ZU/iNL/+/hlM9RV1EZtxMAKs4BwOvWheIKyRiyHUYpobKxLL10UJN6m3NsPlGxJs4 Ts07XEgwC7evTjIS9xrK2rQoC2wzvb+FhuaFpPuh0Xoq2iZqAY59lhzJCBGTxNTQxeuS lbZn9zBOamqlKCKdecksehOqzM6eQ8MYrKgLh55KD6Uh9uKRVPC6W2pVeWHlmYO6lvHA Phhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=O5xBfE/ZGOPJTnop+MEy0u8c1qaCOncm13Ltk1p/JL4=; b=NHkaEE1UXNR0tAde7mJKu5vJ6vAx9dUHoljkxcW0S+CsTTF6HdRYMvJFYO9sDR9xvK CY6V8fX3LnxENwgbH+YVHi8TFcXdVDI5HsCc+BzsqMiM8i5UnxyOvftVc+qb3hydVeET 9mI1ZISTwkdR9AF89PhZ8yXOOLsvYJIs2izcWbn1Rcx/v42Gwxvi1nuklzuhOvWjgsmQ +WTuqPMwPJ2biogwEyOC/49z1tX+k2PlmkCqmLFH0Ml06AAyVO6dSzwkLjOs6nLA3558 bHNLtECoerIobq2Vh0x+aVg6AwtgWzNec+4Wl9Z5kbyqJVwMtq5/pduBB/bIzng92Q1A Yzrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=RCcY4EJr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Fabien Parent [bero@baylibre.com: Cleanups suggested by reviewers] Signed-off-by: Bernhard Rosenkränzer Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Reviewed-by: Chunfeng Yun --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index a3c37944c6305..c119caa9ad168 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt8188-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci reg: From patchwork Wed Jan 25 14:35:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 48170 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp307428wrn; Wed, 25 Jan 2023 06:37:45 -0800 (PST) X-Google-Smtp-Source: AMrXdXvhLLCYpykKembLJlTo4zIwrg05oUAEXYy8IcbQKmBnT4lv+1mFyPT1TSXLAQKzu8wRpk8P X-Received: by 2002:a17:90a:1285:b0:229:679b:bf9c with SMTP id g5-20020a17090a128500b00229679bbf9cmr34070810pja.9.1674657465317; Wed, 25 Jan 2023 06:37:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674657465; cv=none; d=google.com; s=arc-20160816; b=h8hdfBr9QBvTH2N+KrIbJSXKRH3oCGYtFQUHnCDMVkg9kpRJ9vz2KGkE2GglnxWD6J B65rp3IbyBTrO3muk9672oSFg5CY4IahifnAblhRpSVVvtOKKGR74cA6mTjF6lnd45k8 Zdp6aeILBZIA75hJ3HuCNvRgOZdsfuAU70fgvEvRiw6edY8rK1a3/feJWdiKZoxhvDz+ lCilqpf3UUmmM+MrUi4pLxuU86VKAUOre41Rp/IeUmsfTBpijVBaduHH692Ln2ujOfk+ 3ucVe1yy0zCEWsVak3bSYTU5YYK1XbMmao4DErAHM+Kfih2Su0AVkOKfNdUA5dkUWqZ8 L/fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=B2giSoKpmUMBjrMl9HUkga8ekHANL68RCzLpYCFzHvs=; b=uifynCcezyYlcW+j8s1WWs1LlgaChMVKkHCi2vLp1/xFDhd7fHvqBYdLZ+XDjMfM9c Z/L94bkGMsFVX730uVOuQKzHSMLqkeG0+NKXCJ/ExjbSHynnDY54B3xyRMF1gT5KvKon HnjhEauvgJuYBE6bhlF2DT4cbo/7uJVzsT+RpwKyPiXIax8jdBPfKG11PXtTUosryZS7 mTkgK7G2J83TpjsVYYzM9/VOrQMfskCVhNR+w2IaPZatnZM6mpRkp2FrcJ22cVs+hiGs Vkzz7iFL8MUDNPIqHu3oQzH/0BFomglClfAJ9m/WSni4Blh3c/kc2+SnwsYMyEg3TPgj e+pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=kQ6L5xYg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d14-20020a63734e000000b00478e3c07ee0si5666692pgn.385.2023.01.25.06.38.39; Wed, 25 Jan 2023 06:38:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=YayUVbnl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235850AbjAYOgw (ORCPT + 99 others); Wed, 25 Jan 2023 09:36:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235844AbjAYOgK (ORCPT ); Wed, 25 Jan 2023 09:36:10 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A94E2568A2 for ; Wed, 25 Jan 2023 06:35:40 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id kt14so48213513ejc.3 for ; Wed, 25 Jan 2023 06:35:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tOiRWymI4rd5WlsVYIaIq9NoZeWymaeFEkgKA/Uo35w=; b=YayUVbnlxoaVRKYH90E4Pp6J/ospChaNFYmXvVklwZkydkwFE8AhRwOx7ep9skBU+t HII1j71ESkai6nYl14m4JWkpGawmy7obefyz5JO0tQ4Jq4tyRF36iEoyXrGbMyqkkBm3 fvh9s7TPzNCllVBrxerh/fHn+8sHVLcuGKJTd/6k2fS9xKQ3L894d51bGinlUXskepDj /lw0vca8RxfccearHt0cZHABnlvUKayoOH2ZPCjjb9+stM5aMK7OE3UDoNFfKtaTqw4J TIwGmg2iC6jGA5AVCeYEipM8zfSQt6H4H/1H3jx7FVxkc4sAopTtxmPXztzcPYc9/8vC 4kCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tOiRWymI4rd5WlsVYIaIq9NoZeWymaeFEkgKA/Uo35w=; b=qCWWJKO4k8KDXptJQhq7k2n3IU9Ca5TsxwQaRn874Wy5fzMBEIXp5PY1tmH3w3Lsju +Q/2qr6PglXhiwCOBRqOfz8dE3bNAzQ5YgCDs91hVqQ41o1HOh0MtZtfBsiq5q2wgrIZ 5hC84Lu9Xv6ZdrA6JdLreDIaWe923ZhSXg9duyyspZNHKDVsEe4CaumvBm8p6+vsGX35 cd2m4Pq34s5teMjdpfc74DC+ksiaHXUj4LoRAXYYXkCGZb7GWYGInTPAF9uy6XT76cTF k0sPu5MBXp0+SK2oSnpUFKTz8QgAS8v30q5ALTsmJeEwk3ScQqYySp0F6s+girmdmYAX K5yw== X-Gm-Message-State: AFqh2kozh2n2lPbtlnLHMh3RnZGGKYz139fJGOxwRTo1yOVlDyzu0RdQ l/GO6Tu2rb6wXVGllIaTF04iQw== X-Received: by 2002:a17:906:fb09:b0:859:aca8:fe4d with SMTP id lz9-20020a170906fb0900b00859aca8fe4dmr30524138ejb.46.1674657316956; Wed, 25 Jan 2023 06:35:16 -0800 (PST) Received: from c64.fritz.box ([81.221.122.240]) by smtp.gmail.com with ESMTPSA id gx2-20020a1709068a4200b0082000f8d871sm2437789ejc.152.2023.01.25.06.35.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 06:35:16 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, tglx@linutronix.de, maz@kernel.org, lee@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, chunfeng.yun@mediatek.com, angelogioacchino.delregno@collabora.com, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, sean.wang@mediatek.com, zhiyong.tao@mediatek.com Subject: [PATCH v9 9/9] arm64: dts: mediatek: Initial mt8365-evk support Date: Wed, 25 Jan 2023 15:35:03 +0100 Message-Id: <20230125143503.1015424-10-bero@baylibre.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230125143503.1015424-1-bero@baylibre.com> References: <20230125143503.1015424-1-bero@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756005696988411784?= X-GMAIL-MSGID: =?utf-8?q?1756005696988411784?= From: Fabien Parent This adds minimal support for the Mediatek 8365 SOC and the EVK reference board, allowing the board to boot to initramfs with serial port I/O. Signed-off-by: Fabien Parent [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups, add CPU cache layout, add systimer, fix GIC] Signed-off-by: Bernhard Rosenkränzer Tested-by: Kevin Hilman Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 168 +++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 377 ++++++++++++++++++++ 3 files changed, 546 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 813e735c5b96d..d78523c5a7dd6 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -47,4 +47,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts new file mode 100644 index 0000000000000..4683704ea2355 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021-2022 BayLibre, SAS. + * Authors: + * Fabien Parent + * Bernhard Rosenkränzer + */ + +/dts-v1/; + +#include +#include +#include +#include "mt8365.dtsi" + +/ { + model = "MediaTek MT8365 Open Platform EVK"; + compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-volume-up { + gpios = <&pio 24 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x20000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&pio { + gpio_keys: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + }; + }; + + usb_pins: usb-pins { + id-pins { + pinmux = ; + input-enable; + bias-pull-up; + }; + + usb0-vbus-pins { + pinmux = ; + output-high; + }; + + usb1-vbus-pins { + pinmux = ; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux = , + ; + }; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi new file mode 100644 index 0000000000000..15ac4c1f09661 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) 2018 MediaTek Inc. + * Copyright (C) 2022 BayLibre SAS + * Fabien Parent + * Bernhard Rosenkränzer + */ +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8365"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + }; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x10000>, /* GICD */ + <0 0x0c080000 0 0x80000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = ; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8365-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8365-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible = "mediatek,mt8365-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8365-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + keypad: keypad@10010000 { + compatible = "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts = ; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible = "mediatek,mt8365-mcucfg", "syscon"; + reg = <0 0x10200000 0 0x2000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200a80 0 0x20>; + }; + + infracfg_nao: infracfg@1020e000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x1020e000 0 0x1000>; + #clock-cells = <1>; + }; + + rng: rng@1020f000 { + compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_IFR_TRNG>; + clock-names = "rng"; + }; + + apdma: dma-controller@11000280 { + compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; + reg = <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts = , + , + , + , + , + ; + dma-requests = <6>; + clocks = <&infracfg CLK_IFR_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt8365-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + spi: spi@1100a000 { + compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; + reg = <0 0x1100a000 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + ssusb: usb@11201000 { + compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: usb@11200000 { + compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = ; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status = "disabled"; + }; + }; + + u3phy: t-phy@11cc0000 { + compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11cc0000 0x9000>; + + u2port0: usb-phy@0 { + reg = <0x0 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u2port1: usb-phy@1000 { + reg = <0x1000 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8365-systimer", "mediatek,mt6795-systimer"; + reg = <0 0x10017000 0 0x10>; + interrupts = ; + clocks = <&system_clk>; + clock-names = "clk13m"; + }; +};