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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ka13-20020a170907920d00b0086fc8c8d8a7si5889525ejb.76.2023.01.25.03.38.31; Wed, 25 Jan 2023 03:38:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="hij5w/8d"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235675AbjAYLgz (ORCPT + 99 others); Wed, 25 Jan 2023 06:36:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235517AbjAYLgo (ORCPT ); Wed, 25 Jan 2023 06:36:44 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2340C58298; Wed, 25 Jan 2023 03:36:08 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZY7b006819; Wed, 25 Jan 2023 05:35:34 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674646534; bh=f9wcw001IhEHK2H3HH91V0grvH9sbrdQbxg2owu8m3s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hij5w/8dQJGkWASOpQr91S1Yn5ppY0jWBCGfQWAuu7ZA9XbUPexlfYyHL9eztSLkT wXQFL++JROa4WeMbYNZ21OsQHfHya4xoc0bnLMGalcgqDPkvqLpoqy6M/y/uBrK47L mEczKAT/fCHN+czB5piJcKJZKCBbkRqj+Eq3je/I= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30PBZXfO013260 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Jan 2023 05:35:33 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 25 Jan 2023 05:35:33 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 25 Jan 2023 05:35:33 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZWVm114738; Wed, 25 Jan 2023 05:35:32 -0600 From: Aradhya Bhatia To: Rob Herring , Krzysztof Kozlowski , Tomi Valkeinen , Jyri Sarha , David Airlie , Daniel Vetter CC: DRI Development List , Devicetree List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Rahul T R , Devarsh Thakkar , Jai Luthra , Jayesh Choudhary , Aradhya Bhatia Subject: [PATCH v7 1/6] drm/tidss: Remove Video Port to Output Port coupling Date: Wed, 25 Jan 2023 17:05:24 +0530 Message-ID: <20230125113529.13952-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230125113529.13952-1-a-bhatia1@ti.com> References: <20230125113529.13952-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755994375028154950?= X-GMAIL-MSGID: =?utf-8?q?1755994375028154950?= Make DSS Video Ports agnostic of output bus types. DSS controllers have had a 1-to-1 coupling between its VPs and its output ports. This no longer stands true for the new AM625 DSS. This coupling, hence, has been removed by renaming the 'vp_bus_type' to 'output_port_bus_type' because the VPs are essentially agnostic of the bus type and it is the output ports which have a bus type. The AM625 DSS has 2 VPs but requires 3 output ports to support its Dual-Link OLDI video output coming from a single VP. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 47 +++++++++++++++++------------ drivers/gpu/drm/tidss/tidss_dispc.h | 21 +++++++------ drivers/gpu/drm/tidss/tidss_drv.h | 5 +-- drivers/gpu/drm/tidss/tidss_irq.h | 2 +- drivers/gpu/drm/tidss/tidss_kms.c | 12 ++++---- 5 files changed, 48 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 165365b515e1..c1c4faccbddc 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -61,7 +61,7 @@ const struct dispc_features dispc_k2g_feats = { .min_pclk_khz = 4375, .max_pclk_khz = { - [DISPC_VP_DPI] = 150000, + [DISPC_PORT_DPI] = 150000, }, /* @@ -96,7 +96,6 @@ const struct dispc_features dispc_k2g_feats = { .vp_name = { "vp1" }, .ovr_name = { "ovr1" }, .vpclk_name = { "vp1" }, - .vp_bus_type = { DISPC_VP_DPI }, .vp_feat = { .color = { .has_ctm = true, @@ -109,6 +108,9 @@ const struct dispc_features dispc_k2g_feats = { .vid_name = { "vid1" }, .vid_lite = { false }, .vid_order = { 0 }, + + .num_output_ports = 1, + .output_port_bus_type = { DISPC_PORT_DPI }, }; static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { @@ -140,8 +142,8 @@ static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { const struct dispc_features dispc_am65x_feats = { .max_pclk_khz = { - [DISPC_VP_DPI] = 165000, - [DISPC_VP_OLDI] = 165000, + [DISPC_PORT_DPI] = 165000, + [DISPC_PORT_OLDI] = 165000, }, .scaling = { @@ -171,7 +173,6 @@ const struct dispc_features dispc_am65x_feats = { .vp_name = { "vp1", "vp2" }, .ovr_name = { "ovr1", "ovr2" }, .vpclk_name = { "vp1", "vp2" }, - .vp_bus_type = { DISPC_VP_OLDI, DISPC_VP_DPI }, .vp_feat = { .color = { .has_ctm = true, @@ -185,6 +186,9 @@ const struct dispc_features dispc_am65x_feats = { .vid_name = { "vid", "vidl1" }, .vid_lite = { false, true, }, .vid_order = { 1, 0 }, + + .num_output_ports = 2, + .output_port_bus_type = { DISPC_PORT_OLDI, DISPC_PORT_DPI }, }; static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { @@ -229,8 +233,8 @@ static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { const struct dispc_features dispc_j721e_feats = { .max_pclk_khz = { - [DISPC_VP_DPI] = 170000, - [DISPC_VP_INTERNAL] = 600000, + [DISPC_PORT_DPI] = 170000, + [DISPC_PORT_INTERNAL] = 600000, }, .scaling = { @@ -260,9 +264,7 @@ const struct dispc_features dispc_j721e_feats = { .vp_name = { "vp1", "vp2", "vp3", "vp4" }, .ovr_name = { "ovr1", "ovr2", "ovr3", "ovr4" }, .vpclk_name = { "vp1", "vp2", "vp3", "vp4" }, - /* Currently hard coded VP routing (see dispc_initial_config()) */ - .vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI, - DISPC_VP_INTERNAL, DISPC_VP_DPI, }, + .vp_feat = { .color = { .has_ctm = true, .gamma_size = 1024, @@ -273,6 +275,11 @@ const struct dispc_features dispc_j721e_feats = { .vid_name = { "vid1", "vidl1", "vid2", "vidl2" }, .vid_lite = { 0, 1, 0, 1, }, .vid_order = { 1, 3, 0, 2 }, + + .num_output_ports = 4, + /* Currently hard coded VP routing (see dispc_initial_config()) */ + .output_port_bus_type = { DISPC_PORT_INTERNAL, DISPC_PORT_DPI, + DISPC_PORT_INTERNAL, DISPC_PORT_DPI, }, }; static const u16 *dispc_common_regmap; @@ -287,12 +294,12 @@ struct dispc_device { void __iomem *base_common; void __iomem *base_vid[TIDSS_MAX_PLANES]; - void __iomem *base_ovr[TIDSS_MAX_PORTS]; - void __iomem *base_vp[TIDSS_MAX_PORTS]; + void __iomem *base_ovr[TIDSS_MAX_VPS]; + void __iomem *base_vp[TIDSS_MAX_VPS]; struct regmap *oldi_io_ctrl; - struct clk *vp_clk[TIDSS_MAX_PORTS]; + struct clk *vp_clk[TIDSS_MAX_VPS]; const struct dispc_features *feat; @@ -300,7 +307,7 @@ struct dispc_device { bool is_enabled; - struct dss_vp_data vp_data[TIDSS_MAX_PORTS]; + struct dss_vp_data vp_data[TIDSS_MAX_VPS]; u32 *fourccs; u32 num_fourccs; @@ -851,7 +858,7 @@ int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, return -EINVAL; } - if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && + if (dispc->feat->output_port_bus_type[hw_videoport] != DISPC_PORT_OLDI && fmt->is_oldi_fmt) { dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", __func__, dispc->feat->vp_name[hw_videoport]); @@ -955,7 +962,7 @@ void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, if (WARN_ON(!fmt)) return; - if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { + if (dispc->feat->output_port_bus_type[hw_videoport] == DISPC_PORT_OLDI) { dispc_oldi_tx_power(dispc, true); dispc_enable_oldi(dispc, hw_videoport, fmt); @@ -1014,7 +1021,7 @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, align = true; /* always use DE_HIGH for OLDI */ - if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) + if (dispc->feat->output_port_bus_type[hw_videoport] == DISPC_PORT_OLDI) ieo = false; dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, @@ -1040,7 +1047,7 @@ void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) { - if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { + if (dispc->feat->output_port_bus_type[hw_videoport] == DISPC_PORT_OLDI) { dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0); dispc_oldi_tx_power(dispc, false); @@ -1116,10 +1123,10 @@ enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, const struct drm_display_mode *mode) { u32 hsw, hfp, hbp, vsw, vfp, vbp; - enum dispc_vp_bus_type bus_type; + enum dispc_port_bus_type bus_type; int max_pclk; - bus_type = dispc->feat->vp_bus_type[hw_videoport]; + bus_type = dispc->feat->output_port_bus_type[hw_videoport]; max_pclk = dispc->feat->max_pclk_khz[bus_type]; diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index e49432f0abf5..30fb44158347 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -50,11 +50,11 @@ struct dispc_errata { bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */ }; -enum dispc_vp_bus_type { - DISPC_VP_DPI, /* DPI output */ - DISPC_VP_OLDI, /* OLDI (LVDS) output */ - DISPC_VP_INTERNAL, /* SoC internal routing */ - DISPC_VP_MAX_BUS_TYPE, +enum dispc_port_bus_type { + DISPC_PORT_DPI, /* DPI output */ + DISPC_PORT_OLDI, /* OLDI (LVDS) output */ + DISPC_PORT_INTERNAL, /* SoC internal routing */ + DISPC_PORT_MAX_BUS_TYPE, }; enum dispc_dss_subrevision { @@ -65,7 +65,7 @@ enum dispc_dss_subrevision { struct dispc_features { int min_pclk_khz; - int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE]; + int max_pclk_khz[DISPC_PORT_MAX_BUS_TYPE]; struct dispc_features_scaling scaling; @@ -74,15 +74,16 @@ struct dispc_features { const char *common; const u16 *common_regs; u32 num_vps; - const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ - const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ - const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ - const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; + const char *vp_name[TIDSS_MAX_VPS]; /* Should match dt reg names */ + const char *ovr_name[TIDSS_MAX_VPS]; /* Should match dt reg names */ + const char *vpclk_name[TIDSS_MAX_VPS]; /* Should match dt clk names */ struct tidss_vp_feat vp_feat; u32 num_planes; const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ bool vid_lite[TIDSS_MAX_PLANES]; u32 vid_order[TIDSS_MAX_PLANES]; + u32 num_output_ports; + const enum dispc_port_bus_type output_port_bus_type[TIDSS_MAX_OUTPUT_PORTS]; }; extern const struct dispc_features dispc_k2g_feats; diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h index d7f27b0b0315..0ce7ee5ccd5b 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.h +++ b/drivers/gpu/drm/tidss/tidss_drv.h @@ -9,8 +9,9 @@ #include -#define TIDSS_MAX_PORTS 4 +#define TIDSS_MAX_VPS 4 #define TIDSS_MAX_PLANES 4 +#define TIDSS_MAX_OUTPUT_PORTS 4 typedef u32 dispc_irq_t; @@ -22,7 +23,7 @@ struct tidss_device { struct dispc_device *dispc; unsigned int num_crtcs; - struct drm_crtc *crtcs[TIDSS_MAX_PORTS]; + struct drm_crtc *crtcs[TIDSS_MAX_VPS]; unsigned int num_planes; struct drm_plane *planes[TIDSS_MAX_PLANES]; diff --git a/drivers/gpu/drm/tidss/tidss_irq.h b/drivers/gpu/drm/tidss/tidss_irq.h index b512614d5863..a753f5e3ce15 100644 --- a/drivers/gpu/drm/tidss/tidss_irq.h +++ b/drivers/gpu/drm/tidss/tidss_irq.h @@ -35,7 +35,7 @@ #define DSS_IRQ_VP_BIT_N(ch, bit) (4 + 4 * (ch) + (bit)) #define DSS_IRQ_PLANE_BIT_N(plane, bit) \ - (DSS_IRQ_VP_BIT_N(TIDSS_MAX_PORTS, 0) + 1 * (plane) + (bit)) + (DSS_IRQ_VP_BIT_N(TIDSS_MAX_VPS, 0) + 1 * (plane) + (bit)) #define DSS_IRQ_VP_BIT(ch, bit) BIT(DSS_IRQ_VP_BIT_N((ch), (bit))) #define DSS_IRQ_PLANE_BIT(plane, bit) \ diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c index ad2fa3c3d4a7..d449131935d2 100644 --- a/drivers/gpu/drm/tidss/tidss_kms.c +++ b/drivers/gpu/drm/tidss/tidss_kms.c @@ -118,16 +118,16 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss) }; const struct dispc_features *feat = tidss->feat; - u32 max_vps = feat->num_vps; + u32 output_ports = feat->num_output_ports; u32 max_planes = feat->num_planes; - struct pipe pipes[TIDSS_MAX_PORTS]; + struct pipe pipes[TIDSS_MAX_VPS]; u32 num_pipes = 0; u32 crtc_mask; /* first find all the connected panels & bridges */ - for (i = 0; i < max_vps; i++) { + for (i = 0; i < output_ports; i++) { struct drm_panel *panel; struct drm_bridge *bridge; u32 enc_type = DRM_MODE_ENCODER_NONE; @@ -148,12 +148,12 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss) dev_dbg(dev, "Setting up panel for port %d\n", i); - switch (feat->vp_bus_type[i]) { - case DISPC_VP_OLDI: + switch (feat->output_port_bus_type[i]) { + case DISPC_PORT_OLDI: enc_type = DRM_MODE_ENCODER_LVDS; conn_type = DRM_MODE_CONNECTOR_LVDS; break; - case DISPC_VP_DPI: + case DISPC_PORT_DPI: enc_type = DRM_MODE_ENCODER_DPI; conn_type = DRM_MODE_CONNECTOR_DPI; break; From patchwork Wed Jan 25 11:35:25 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id vf22-20020a170907239600b00870ab2b9d6csi5571855ejb.62.2023.01.25.03.39.18; Wed, 25 Jan 2023 03:39:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="NYIU/mG6"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235589AbjAYLgv (ORCPT + 99 others); Wed, 25 Jan 2023 06:36:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235523AbjAYLgo (ORCPT ); Wed, 25 Jan 2023 06:36:44 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6623A56ED3; Wed, 25 Jan 2023 03:36:10 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZZHX120927; Wed, 25 Jan 2023 05:35:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674646535; bh=spu8mpkf0idGKiowTQ//ULeRb5yOrGVsyubCEwvDS40=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NYIU/mG6JGxw0IMqcyncZC78JuVW6Tnmo5NM4zl+Yq8vcW436JoyHbixQTX5A0acH EZYDuRaEnjMbE57f2Mxe49HmHVvhoscRvYv3ENRlOzX6K7wX7+npNKSzvKhAkyLB9T zMuUv7f/miO2tVqbQgHMwapTREOxvWExijflmaxw= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30PBZZAW113558 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Jan 2023 05:35:35 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 25 Jan 2023 05:35:35 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 25 Jan 2023 05:35:35 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZYHl074765; Wed, 25 Jan 2023 05:35:34 -0600 From: Aradhya Bhatia To: Rob Herring , Krzysztof Kozlowski , Tomi Valkeinen , Jyri Sarha , David Airlie , Daniel Vetter CC: DRI Development List , Devicetree List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Rahul T R , Devarsh Thakkar , Jai Luthra , Jayesh Choudhary , Aradhya Bhatia Subject: [PATCH v7 2/6] dt-bindings: display: ti,am65x-dss: Add support for am625 dss Date: Wed, 25 Jan 2023 17:05:25 +0530 Message-ID: <20230125113529.13952-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230125113529.13952-1-a-bhatia1@ti.com> References: <20230125113529.13952-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755994425223821441?= X-GMAIL-MSGID: =?utf-8?q?1755994425223821441?= The DSS controller on TI's AM625 SoC is an update from that on TI's AM65X SoC. The former has an additional OLDI TX on its first video port (VP0) that helps output cloned video or WUXGA (1920x1200@60fps) resolution video output over a dual-link mode to reduce the required OLDI clock output. Add the new controller's compatible and a port property for the 2nd OLDI TX (OLDI TX 1). Signed-off-by: Aradhya Bhatia Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rahul T R --- .../bindings/display/ti/ti,am65x-dss.yaml | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 5c7d2cbc4aac..55ec91f11577 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -19,7 +19,9 @@ description: | properties: compatible: - const: ti,am65x-dss + enum: + - ti,am625-dss + - ti,am65x-dss reg: description: @@ -80,13 +82,18 @@ properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: - The DSS OLDI output port node form video port 1 + The DSS OLDI output port node form video port 1 (OLDI TX 0). port@1: $ref: /schemas/graph.yaml#/properties/port description: The DSS DPI output port node from video port 2 + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + The DSS OLDI output port node form video port 1 (OLDI TX 1). + ti,am65x-oldi-io-ctrl: $ref: "/schemas/types.yaml#/definitions/phandle" description: @@ -102,6 +109,18 @@ properties: Input memory (from main memory to dispc) bandwidth limit in bytes per second +allOf: + - if: + properties: + compatible: + contains: + const: ti,am65x-dss + then: + properties: + ports: + properties: + port@2: false + required: - compatible - reg From patchwork Wed Jan 25 11:35:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 48122 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp226854wrn; Wed, 25 Jan 2023 03:38:57 -0800 (PST) X-Google-Smtp-Source: AMrXdXt191xWkJFeUrTjEWXCTYl0CPTzkJtJ9CIwBfsO+QUfWgOEuTA44v1Q/V/FkKBm+Igi9oXS X-Received: by 2002:a17:906:3e51:b0:7c1:932c:96d7 with SMTP id t17-20020a1709063e5100b007c1932c96d7mr29879990eji.58.1674646737309; Wed, 25 Jan 2023 03:38:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674646737; cv=none; d=google.com; s=arc-20160816; b=JzP5i7qHu+a3vKhDGI54GFop+//MV4p/iZBoGgSId7yrRwFhQGjmwGyiHa39VqeIps dlKl+spVkkneMF3MuwHBqgQXLfW99HfbVMrq+N9caSBzb/t3bJihDE/R423EpxF7vJdl tjfa+xJLZX6FptstRZcrKWanNrRdcsuX0EdB3Ly2Vj9TjWQI8VUGCu0+lWyNuWz32JH4 5RbtgWkWvNjKnU4o3Vj2e8qHytO+e8IPcHCcozmDyTthRBWs98CKo/e+AKhRrNsleLNc H7oVDszuzqvVw8zBUrajOtbdJFWnc0Fl9O+QBNu6SnHM8XeR9bYK3j4Kvm0C8s8yedrl EWlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xdh95E/zriEpwXRNgrK0urLgwz9fTz+KTg1FFi2xwbI=; b=Xr24GGOQ25OAnoqT+kmZz3hGYvzHcLzCrOFDQ6aUSzqjrj4IA+wD4K9CFLoBjMR/3E DP8irLmcflXtHJMjuq3lq0lMoZ9wCNpL9T/Y9rjFKPthXaiFUOyPbWJzY88zMyCpRWbX VbaLNEBxj4NMj3BWlY6q94ZDLZYX2uahbcgCLmECqYFhUmaBadoB/4K+C+iNueGZ4DKw ZF82yAjDBZH8jLgIE5DvL3aeuc61a/6WIWp2TqWyd0I80Xf/3vA2aDlrNpYdYebPjiT5 TVXqXHwK2N4Vr+U9gCz4Ea+TgDdNCg1YBcnwjT62o/KpdhM/StwzMZx+LnAN/t9BOxOI sn+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cUFD8L2g; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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The first video port (VP0) in am625-dss can output OLDI signals through 2 OLDI TXes. A 3rd output port has been added with "DISPC_PORT_OLDI" bus type. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 57 +++++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 2 + drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 60 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index c1c4faccbddc..b55ccbcaa67f 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -140,6 +140,58 @@ static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { [DISPC_SECURE_DISABLE_OFF] = 0xac, }; +const struct dispc_features dispc_am625_feats = { + .max_pclk_khz = { + [DISPC_PORT_DPI] = 165000, + [DISPC_PORT_OLDI] = 165000, + }, + + .scaling = { + .in_width_max_5tap_rgb = 1280, + .in_width_max_3tap_rgb = 2560, + .in_width_max_5tap_yuv = 2560, + .in_width_max_3tap_yuv = 4096, + .upscale_limit = 16, + .downscale_limit_5tap = 4, + .downscale_limit_3tap = 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max = 32, + }, + + .subrev = DISPC_AM625, + + .common = "common", + .common_regs = tidss_am65x_common_regs, + + .num_vps = 2, + .vp_name = { "vp1", "vp2" }, + .ovr_name = { "ovr1", "ovr2" }, + .vpclk_name = { "vp1", "vp2" }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 256, + .gamma_type = TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes = 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name = { "vid", "vidl1" }, + .vid_lite = { false, true, }, + .vid_order = { 1, 0 }, + + /* 3rd output port is not representative of a 3rd pipeline */ + .num_output_ports = 3, + .output_port_bus_type = { DISPC_PORT_OLDI, DISPC_PORT_DPI, DISPC_PORT_OLDI }, +}; + const struct dispc_features dispc_am65x_feats = { .max_pclk_khz = { [DISPC_PORT_DPI] = 165000, @@ -783,6 +835,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) switch (dispc->feat->subrev) { case DISPC_K2G: return dispc_k2g_read_and_clear_irqstatus(dispc); + case DISPC_AM625: case DISPC_AM65X: case DISPC_J721E: return dispc_k3_read_and_clear_irqstatus(dispc); @@ -798,6 +851,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) case DISPC_K2G: dispc_k2g_set_irqenable(dispc, mask); break; + case DISPC_AM625: case DISPC_AM65X: case DISPC_J721E: dispc_k3_set_irqenable(dispc, mask); @@ -1288,6 +1342,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); break; + case DISPC_AM625: case DISPC_AM65X: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); @@ -2210,6 +2265,7 @@ static void dispc_plane_init(struct dispc_device *dispc) case DISPC_K2G: dispc_k2g_plane_init(dispc); break; + case DISPC_AM625: case DISPC_AM65X: case DISPC_J721E: dispc_k3_plane_init(dispc); @@ -2316,6 +2372,7 @@ static void dispc_vp_write_gamma_table(struct dispc_device *dispc, case DISPC_K2G: dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); break; + case DISPC_AM625: case DISPC_AM65X: dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); break; diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index 30fb44158347..971f2856f015 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -59,6 +59,7 @@ enum dispc_port_bus_type { enum dispc_dss_subrevision { DISPC_K2G, + DISPC_AM625, DISPC_AM65X, DISPC_J721E, }; @@ -87,6 +88,7 @@ struct dispc_features { }; extern const struct dispc_features dispc_k2g_feats; +extern const struct dispc_features dispc_am625_feats; extern const struct dispc_features dispc_am65x_feats; extern const struct dispc_features dispc_j721e_feats; diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c index 2dac8727d2f4..8558dc6999d8 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -232,6 +232,7 @@ static void tidss_shutdown(struct platform_device *pdev) static const struct of_device_id tidss_of_table[] = { { .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, }, + { .compatible = "ti,am625-dss", .data = &dispc_am625_feats, }, { .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, }, { .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, }, { } From patchwork Wed Jan 25 11:35:27 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z2-20020a056402274200b0049db071cacasi8288746edd.349.2023.01.25.03.39.22; Wed, 25 Jan 2023 03:39:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UOsUDwFr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235381AbjAYLhC (ORCPT + 99 others); Wed, 25 Jan 2023 06:37:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235093AbjAYLgq (ORCPT ); Wed, 25 Jan 2023 06:36:46 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A7451164E; Wed, 25 Jan 2023 03:36:12 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZevM120967; Wed, 25 Jan 2023 05:35:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674646540; bh=zSjYKlSe448zdPgmMjwnyU0kRDTtF4UwWV/GqtE2stI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UOsUDwFrRLCLkelzaaBfEmRVuhUJHJxCsABt5+jJHQ4rNp9dmqTUPzzKXUDJ9KDmU OpCfWrEm/MJypszyH5VqUaB9PbCDszdw0zi+J9jzSY815nzaQ08c8Nyp3oy0xAVmBL W3gdP0fZxHiPFVAEq9nfEJyaO8aPSQFHJijL5XpE= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30PBZeZE027894 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Jan 2023 05:35:40 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 25 Jan 2023 05:35:40 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 25 Jan 2023 05:35:39 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZcqX021874; Wed, 25 Jan 2023 05:35:38 -0600 From: Aradhya Bhatia To: Rob Herring , Krzysztof Kozlowski , Tomi Valkeinen , Jyri Sarha , David Airlie , Daniel Vetter CC: DRI Development List , Devicetree List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Rahul T R , Devarsh Thakkar , Jai Luthra , Jayesh Choudhary , Aradhya Bhatia Subject: [PATCH v7 4/6] drm/tidss: Add support to configure OLDI mode for am625-dss Date: Wed, 25 Jan 2023 17:05:27 +0530 Message-ID: <20230125113529.13952-5-a-bhatia1@ti.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230125113529.13952-1-a-bhatia1@ti.com> References: <20230125113529.13952-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755994429136002852?= X-GMAIL-MSGID: =?utf-8?q?1755994429136002852?= The newer version of DSS (AM625-DSS) has 2 OLDI TXes at its disposal. These can be configured to support the following modes: 1. OLDI_SINGLE_LINK_SINGLE_MODE Single Output over OLDI 0. +------+ +---------+ +-------+ | | | | | | | CRTC +------->+ ENCODER +----->| PANEL | | | | | | | +------+ +---------+ +-------+ 2. OLDI_SINGLE_LINK_CLONE_MODE Duplicate Output over OLDI 0 and 1. +------+ +---------+ +-------+ | | | | | | | CRTC +---+--->| ENCODER +----->| PANEL | | | | | | | | +------+ | +---------+ +-------+ | | +---------+ +-------+ | | | | | +--->| ENCODER +----->| PANEL | | | | | +---------+ +-------+ 3. OLDI_DUAL_LINK_MODE Combined Output over OLDI 0 and 1. +------+ +---------+ +-------+ | | | +----->| | | CRTC +------->+ ENCODER | | PANEL | | | | +----->| | +------+ +---------+ +-------+ Following the above pathways for different modes, 2 encoder/panel-bridge pipes get created for clone mode, and 1 pipe in cases of single link and dual link mode. Add support for confguring the OLDI modes using OF and LVDS DRM helper functions. Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/tidss/tidss_dispc.c | 24 ++- drivers/gpu/drm/tidss/tidss_dispc.h | 12 ++ drivers/gpu/drm/tidss/tidss_drv.h | 3 + drivers/gpu/drm/tidss/tidss_encoder.c | 4 +- drivers/gpu/drm/tidss/tidss_encoder.h | 3 +- drivers/gpu/drm/tidss/tidss_kms.c | 221 ++++++++++++++++++++++++-- 6 files changed, 245 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index b55ccbcaa67f..37a73e309330 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -88,6 +88,8 @@ const struct dispc_features dispc_k2g_feats = { .subrev = DISPC_K2G, + .has_oldi = false, + .common = "common", .common_regs = tidss_k2g_common_regs, @@ -166,6 +168,8 @@ const struct dispc_features dispc_am625_feats = { .subrev = DISPC_AM625, + .has_oldi = true, + .common = "common", .common_regs = tidss_am65x_common_regs, @@ -218,6 +222,8 @@ const struct dispc_features dispc_am65x_feats = { .subrev = DISPC_AM65X, + .has_oldi = true, + .common = "common", .common_regs = tidss_am65x_common_regs, @@ -309,6 +315,8 @@ const struct dispc_features dispc_j721e_feats = { .subrev = DISPC_J721E, + .has_oldi = false, + .common = "common_m", .common_regs = tidss_j721e_common_regs, @@ -361,6 +369,8 @@ struct dispc_device { struct dss_vp_data vp_data[TIDSS_MAX_VPS]; + enum dispc_oldi_modes oldi_mode; + u32 *fourccs; u32 num_fourccs; @@ -1963,6 +1973,12 @@ const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len) return dispc->fourccs; } +void dispc_set_oldi_mode(struct dispc_device *dispc, + enum dispc_oldi_modes oldi_mode) +{ + dispc->oldi_mode = oldi_mode; +} + static s32 pixinc(int pixels, u8 ps) { if (pixels == 1) @@ -2647,7 +2663,7 @@ int dispc_runtime_resume(struct dispc_device *dispc) REG_GET(dispc, DSS_SYSSTATUS, 2, 2), REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); - if (dispc->feat->subrev == DISPC_AM65X) + if (dispc->feat->has_oldi) dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", REG_GET(dispc, DSS_SYSSTATUS, 5, 5), REG_GET(dispc, DSS_SYSSTATUS, 6, 6), @@ -2688,7 +2704,7 @@ static int dispc_iomap_resource(struct platform_device *pdev, const char *name, return 0; } -static int dispc_init_am65x_oldi_io_ctrl(struct device *dev, +static int dispc_init_am6xx_oldi_io_ctrl(struct device *dev, struct dispc_device *dispc) { dispc->oldi_io_ctrl = @@ -2827,8 +2843,8 @@ int dispc_init(struct tidss_device *tidss) dispc->vp_data[i].gamma_table = gamma_table; } - if (feat->subrev == DISPC_AM65X) { - r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); + if (feat->has_oldi) { + r = dispc_init_am6xx_oldi_io_ctrl(dev, dispc); if (r) return r; } diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h index 971f2856f015..880bc7de68b3 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -64,6 +64,15 @@ enum dispc_dss_subrevision { DISPC_J721E, }; +enum dispc_oldi_modes { + OLDI_MODE_SINGLE_LINK, /* Single output over OLDI 0. */ + OLDI_MODE_CLONE_SINGLE_LINK, /* Cloned output over OLDI 0 and 1. */ + OLDI_MODE_DUAL_LINK, /* Combined output over OLDI 0 and 1. */ + OLDI_MODE_OFF, /* OLDI TXes not connected in OF. */ + OLDI_MODE_UNSUPPORTED, /* Unsupported OLDI configuration in OF. */ + OLDI_MODE_UNAVAILABLE, /* OLDI TXes not available in SoC. */ +}; + struct dispc_features { int min_pclk_khz; int max_pclk_khz[DISPC_PORT_MAX_BUS_TYPE]; @@ -72,6 +81,8 @@ struct dispc_features { enum dispc_dss_subrevision subrev; + bool has_oldi; + const char *common; const u16 *common_regs; u32 num_vps; @@ -131,6 +142,7 @@ int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport); int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable); const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len); +void dispc_set_oldi_mode(struct dispc_device *dispc, enum dispc_oldi_modes oldi_mode); int dispc_init(struct tidss_device *tidss); void dispc_remove(struct tidss_device *tidss); diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h index 0ce7ee5ccd5b..58892f065c16 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.h +++ b/drivers/gpu/drm/tidss/tidss_drv.h @@ -13,6 +13,9 @@ #define TIDSS_MAX_PLANES 4 #define TIDSS_MAX_OUTPUT_PORTS 4 +/* For AM625-DSS with 2 OLDI TXes */ +#define TIDSS_MAX_BRIDGES_PER_PIPE 2 + typedef u32 dispc_irq_t; struct tidss_device { diff --git a/drivers/gpu/drm/tidss/tidss_encoder.c b/drivers/gpu/drm/tidss/tidss_encoder.c index 0d4865e9c03d..bd2a7358d7b0 100644 --- a/drivers/gpu/drm/tidss/tidss_encoder.c +++ b/drivers/gpu/drm/tidss/tidss_encoder.c @@ -70,7 +70,8 @@ static const struct drm_encoder_funcs encoder_funcs = { }; struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss, - u32 encoder_type, u32 possible_crtcs) + u32 encoder_type, u32 possible_crtcs, + u32 possible_clones) { struct drm_encoder *enc; int ret; @@ -80,6 +81,7 @@ struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss, return ERR_PTR(-ENOMEM); enc->possible_crtcs = possible_crtcs; + enc->possible_clones = possible_clones; ret = drm_encoder_init(&tidss->ddev, enc, &encoder_funcs, encoder_type, NULL); diff --git a/drivers/gpu/drm/tidss/tidss_encoder.h b/drivers/gpu/drm/tidss/tidss_encoder.h index ace877c0e0fd..01c62ba3ef16 100644 --- a/drivers/gpu/drm/tidss/tidss_encoder.h +++ b/drivers/gpu/drm/tidss/tidss_encoder.h @@ -12,6 +12,7 @@ struct tidss_device; struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss, - u32 encoder_type, u32 possible_crtcs); + u32 encoder_type, u32 possible_crtcs, + u32 possible_clones); #endif diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c index d449131935d2..8322ee6310bf 100644 --- a/drivers/gpu/drm/tidss/tidss_kms.c +++ b/drivers/gpu/drm/tidss/tidss_kms.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "tidss_crtc.h" #include "tidss_dispc.h" @@ -104,26 +105,129 @@ static const struct drm_mode_config_funcs mode_config_funcs = { .atomic_commit = drm_atomic_helper_commit, }; +static enum dispc_oldi_modes tidss_get_oldi_mode(struct tidss_device *tidss) +{ + int pixel_order; + enum dispc_oldi_modes oldi_mode; + struct device_node *oldi0_port, *oldi1_port; + + /* + * For am625-dss, the OLDI ports are expected at port reg = 0 and 2, + * and for am65x-dss, the OLDI port is expected only at port reg = 0. + */ + const u32 portnum_oldi0 = 0, portnum_oldi1 = 2; + + oldi0_port = of_graph_get_port_by_id(tidss->dev->of_node, portnum_oldi0); + oldi1_port = of_graph_get_port_by_id(tidss->dev->of_node, portnum_oldi1); + + if (!(oldi0_port || oldi1_port)) { + /* Keep OLDI TXes OFF if neither OLDI port is present. */ + oldi_mode = OLDI_MODE_OFF; + } else if (oldi0_port && !oldi1_port) { + /* + * OLDI0 port found, but not OLDI1 port. Setting single + * link output mode. + */ + oldi_mode = OLDI_MODE_SINGLE_LINK; + } else if (!oldi0_port && oldi1_port) { + /* + * The 2nd OLDI TX cannot be operated alone. This use case is + * not supported in the HW. Since the pins for OLDIs 0 and 1 are + * separate, one could theoretically set a clone mode over OLDIs + * 0 and 1 and just simply not use the OLDI 0. This is a hacky + * way to enable only OLDI TX 1 and hence is not officially + * supported. + */ + dev_warn(tidss->dev, + "Single Mode over OLDI 1 is not supported in HW.\n"); + oldi_mode = OLDI_MODE_UNSUPPORTED; + } else { + /* + * OLDI Ports found for both the OLDI TXes. The DSS is to be + * configured in either Dual Link or Clone Mode. + */ + pixel_order = drm_of_lvds_get_dual_link_pixel_order(oldi0_port, + oldi1_port); + switch (pixel_order) { + case -EINVAL: + /* + * The dual link properties were not found in at least + * one of the sink nodes. Since 2 OLDI ports are present + * in the DT, it can be safely assumed that the required + * configuration is Clone Mode. + */ + oldi_mode = OLDI_MODE_CLONE_SINGLE_LINK; + break; + + case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: + /* + * Note that the OLDI TX 0 transmits the odd set of + * pixels while the OLDI TX 1 transmits the even set. + * This is a fixed configuration in the HW and an cannot + * be change via SW. + */ + dev_warn(tidss->dev, + "EVEN-ODD Dual-Link Mode is not supported in HW.\n"); + oldi_mode = OLDI_MODE_UNSUPPORTED; + break; + + case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: + oldi_mode = OLDI_MODE_DUAL_LINK; + break; + + default: + oldi_mode = OLDI_MODE_UNSUPPORTED; + break; + } + } + + of_node_put(oldi0_port); + of_node_put(oldi1_port); + + return oldi_mode; +} + static int tidss_dispc_modeset_init(struct tidss_device *tidss) { struct device *dev = tidss->dev; unsigned int fourccs_len; const u32 *fourccs = dispc_plane_formats(tidss->dispc, &fourccs_len); - unsigned int i; + unsigned int i, j; struct pipe { u32 hw_videoport; - struct drm_bridge *bridge; + struct drm_bridge *bridge[TIDSS_MAX_BRIDGES_PER_PIPE]; u32 enc_type; + u32 num_bridges; }; const struct dispc_features *feat = tidss->feat; u32 output_ports = feat->num_output_ports; u32 max_planes = feat->num_planes; - struct pipe pipes[TIDSS_MAX_VPS]; + struct pipe pipes[TIDSS_MAX_VPS] = {0}; + u32 num_pipes = 0; u32 crtc_mask; + enum dispc_oldi_modes oldi_mode = OLDI_MODE_UNAVAILABLE; + u32 num_oldi = 0; + u32 num_encoders = 0; + u32 oldi_pipe_index = 0; + + if (feat->has_oldi) { + oldi_mode = tidss_get_oldi_mode(tidss); + + if ((oldi_mode == OLDI_MODE_DUAL_LINK || + oldi_mode == OLDI_MODE_CLONE_SINGLE_LINK) && + feat->subrev == DISPC_AM65X) { + dev_warn(tidss->dev, + "am65x-dss does not support this OLDI mode.\n"); + + oldi_mode = OLDI_MODE_UNSUPPORTED; + } + + dispc_set_oldi_mode(tidss->dispc, oldi_mode); + } /* first find all the connected panels & bridges */ @@ -179,10 +283,87 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss) } } - pipes[num_pipes].hw_videoport = i; - pipes[num_pipes].bridge = bridge; - pipes[num_pipes].enc_type = enc_type; - num_pipes++; + if (feat->output_port_bus_type[i] == DISPC_PORT_OLDI) { + switch (oldi_mode) { + case OLDI_MODE_UNSUPPORTED: + case OLDI_MODE_OFF: + /* + * Either the OLDI ports are not connected in + * OF, or their configuration mode is not + * supported. + * In both the cases, the OLDI sink ports shall + * not be logically connected to DSS ports. + * + * However, since other dss ports might still + * be in use (eg, for DPI), the driver shall + * continue to find the next connected sink in + * OF. + */ + dev_dbg(dev, "OLDI disconnected on port %d\n", i); + continue; + + case OLDI_MODE_DUAL_LINK: + /* + * The 2nd OLDI port of a dual-link sink does + * not require a separate bridge entity. + */ + if (num_oldi) { + drm_panel_bridge_remove(bridge); + continue; + } + + fallthrough; + + case OLDI_MODE_CLONE_SINGLE_LINK: + case OLDI_MODE_SINGLE_LINK: + /* + * Setting up pipe parameters when 1st OLDI + * port is detected. + */ + if (!num_oldi) { + pipes[num_pipes].hw_videoport = i; + pipes[num_pipes].enc_type = enc_type; + + /* + * Saving the pipe index in case its + * required for 2nd OLDI Port. + */ + oldi_pipe_index = num_pipes; + + /* + * Incrememnt num_pipe when 1st oldi + * port is discovered. For the 2nd OLDI + * port, num_pipe need not be + * incremented because the 2nd + * Encoder-to-Bridge connection will + * still be the part of the first OLDI + * Port pipe. + */ + num_pipes++; + } + + /* + * Bridge is required to be added only if the + * detected port is the first OLDI port (of any + * mode) or a subsequent port in Clone Mode. + */ + pipes[oldi_pipe_index].bridge[num_oldi] = bridge; + pipes[oldi_pipe_index].num_bridges++; + num_oldi++; + break; + + case OLDI_MODE_UNAVAILABLE: + default: + dev_dbg(dev, "OLDI unavailable on this device.\n"); + break; + } + } else { + pipes[num_pipes].hw_videoport = i; + pipes[num_pipes].bridge[0] = bridge; + pipes[num_pipes].num_bridges++; + pipes[num_pipes].enc_type = enc_type; + num_pipes++; + } } /* all planes can be on any crtc */ @@ -194,6 +375,7 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss) struct tidss_plane *tplane; struct tidss_crtc *tcrtc; struct drm_encoder *enc; + u32 possible_clones = 0; u32 hw_plane_id = feat->vid_order[tidss->num_planes]; int ret; @@ -216,16 +398,23 @@ static int tidss_dispc_modeset_init(struct tidss_device *tidss) tidss->crtcs[tidss->num_crtcs++] = &tcrtc->crtc; - enc = tidss_encoder_create(tidss, pipes[i].enc_type, - 1 << tcrtc->crtc.index); - if (IS_ERR(enc)) { - dev_err(tidss->dev, "encoder create failed\n"); - return PTR_ERR(enc); - } + possible_clones = (((1 << pipes[i].num_bridges) - 1) + << num_encoders); - ret = drm_bridge_attach(enc, pipes[i].bridge, NULL, 0); - if (ret) - return ret; + for (j = 0; j < pipes[i].num_bridges; j++) { + enc = tidss_encoder_create(tidss, pipes[i].enc_type, + 1 << tcrtc->crtc.index, + possible_clones); + if (IS_ERR(enc)) { + dev_err(tidss->dev, "encoder create failed\n"); + return PTR_ERR(enc); + } + + ret = drm_bridge_attach(enc, pipes[i].bridge[j], NULL, 0); + if (ret) + return ret; + } + num_encoders += pipes[i].num_bridges; } /* create overlay planes of the leftover planes */ From patchwork Wed Jan 25 11:35:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 48124 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp227103wrn; Wed, 25 Jan 2023 03:39:45 -0800 (PST) X-Google-Smtp-Source: AMrXdXtFhKeO/qHHgKRB0nfUHo6+1Gbn/fIfVdx3Ns/kkiQgr1ft2Ei/bTTIbVKWT+U0prIhL2E1 X-Received: by 2002:a17:906:7f06:b0:86f:fe8a:2f1c with SMTP id d6-20020a1709067f0600b0086ffe8a2f1cmr33668646ejr.35.1674646785525; Wed, 25 Jan 2023 03:39:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674646785; cv=none; d=google.com; s=arc-20160816; b=M9h2aM4KsyPzg5Lw1uWX4iOrmMx/tsme33tMFv1vi19tXZjcTRjHZFYzhYg7rqHZ+Q /SnbIEge/WzlpA83zq6T5DAxUng1dEQfSIoRQK5iuZTPaseRUM30hrTxkYkGSt0ii5wT aKyFj7t/3F0XFBbAGK8UgARAWYMZvhLjvvXlAnZZNlXqVEeHfLiGh4C31vnyfq1aCmFA 7avMyIWhJa5hFwgol7f1mKDNc0QgAal9cib1x4V0D/nv1vWYiwMRHSc69zoHwagrI4ea I39OSTcPYicWYkHzy+pEtVICwp/pMyexJPMPoRjpbhvWZ8OyRpwb3oLJwIQMUHKj6w5x hfMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FTzBSlhK5RUNaOUKZ3pnFEXS6CiPBc4U1DhXc8++ItA=; b=g/jYpfy3/t152l52m6A6giMlEucrT4hAACSF4p6Ov5TgOYqLFzgFdEhg1gQu4B4P1H wg4hFiyzpSI7iN24azpINh1P0l1Aduwu80GvMLhepP+iRGgB/5EQZ2ese5pGZRUwZk5A y2lCb1SkLZKRop6lwq1kE1qhS3LARL8v94HtIDdRUTHNlrw0BNV3gCyMV4LCpkZ68/am 79+Ih8K2CTkgWL4z2wekxihyGS5ODAfbyODVriSj8Tlq9o8IuB3d1nRqDUQdLdn9y1jv jXP/S3kwVLBLYHIa7+HojvhGEzINjxzMlYFb/xXbgDvCJ5MGUwKCAWeku5uRUjhNmPYg gDUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GSzg8IvG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 30-20020a170906005e00b008773f54e94bsi7845068ejg.553.2023.01.25.03.39.20; Wed, 25 Jan 2023 03:39:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GSzg8IvG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235737AbjAYLhB (ORCPT + 99 others); Wed, 25 Jan 2023 06:37:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235395AbjAYLgp (ORCPT ); Wed, 25 Jan 2023 06:36:45 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 007AC56494; Wed, 25 Jan 2023 03:36:12 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZgRE120976; Wed, 25 Jan 2023 05:35:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674646542; bh=FTzBSlhK5RUNaOUKZ3pnFEXS6CiPBc4U1DhXc8++ItA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GSzg8IvGiNCdRbkWxof5dBN8Ig5to4fpWXX84D1easiyz13tKvOwYOptb3eOYlJNW ncyBytrtPZfrNu/4Ud0oYYNnFC/1FELPEZTgrF4PVxoQ8jsXGPpahRXqxLfxRiFHD8 Obdgpf7zqRsf9rlsPkT5GExLsegTGEmmL+dUR8Tk= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30PBZgYH013323 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Jan 2023 05:35:42 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 25 Jan 2023 05:35:42 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 25 Jan 2023 05:35:41 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZe69021889; Wed, 25 Jan 2023 05:35:41 -0600 From: Aradhya Bhatia To: Rob Herring , Krzysztof Kozlowski , Tomi Valkeinen , Jyri Sarha , David Airlie , Daniel Vetter CC: DRI Development List , Devicetree List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Rahul T R , Devarsh Thakkar , Jai Luthra , Jayesh Choudhary , Aradhya Bhatia Subject: [PATCH v7 5/6] drm/tidss: Add IO CTRL and Power support for OLDI TX in am625 Date: Wed, 25 Jan 2023 17:05:28 +0530 Message-ID: <20230125113529.13952-6-a-bhatia1@ti.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230125113529.13952-1-a-bhatia1@ti.com> References: <20230125113529.13952-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755994427345161913?= X-GMAIL-MSGID: =?utf-8?q?1755994427345161913?= The ctrl mmr module of the AM625 is different from the AM65X SoC. Thus the ctrl mmr registers that supported the OLDI TX power have become different in AM625 SoC. The common mode voltage of the LVDS buffers becomes random when the bandgap reference is turned off. This causes uncertainity in the LVDS Data and Clock signal outputs, making it behave differently under different conditions and panel setups. The bandgap reference must be powered on before using the OLDI IOs, to keep the common voltage trimmed down to desired levels. Add support to enable/disable OLDI IO signals as well as the bandgap reference circuit for the LVDS signals. Signed-off-by: Aradhya Bhatia Reviewed-by: Tomi Valkeinen --- Note: - Dropped Tomi Valkeinen's reviewed-by tag in this patch because I did not implement one of his comments which suggested to remove the 'oldi_supported' variable. While the oldi support is indeed based on SoC variations, keeping that variable helps take into account the case where an OLDI supporting SoC by-passes OLDI TXes and gives out DPI video signals straight from DSS. drivers/gpu/drm/tidss/tidss_dispc.c | 57 +++++++++++++++++++----- drivers/gpu/drm/tidss/tidss_dispc_regs.h | 40 ++++++++++++----- 2 files changed, 76 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 37a73e309330..0e03557bc142 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -934,21 +934,56 @@ int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) { - u32 val = power ? 0 : OLDI_PWRDN_TX; + u32 val; if (WARN_ON(!dispc->oldi_io_ctrl)) return; - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, - OLDI_PWRDN_TX, val); - regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, - OLDI_PWRDN_TX, val); + if (dispc->feat->subrev == DISPC_AM65X) { + val = power ? 0 : AM65X_OLDI_PWRDN_TX; + + regmap_update_bits(dispc->oldi_io_ctrl, AM65X_OLDI_DAT0_IO_CTRL, + AM65X_OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, AM65X_OLDI_DAT1_IO_CTRL, + AM65X_OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, AM65X_OLDI_DAT2_IO_CTRL, + AM65X_OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, AM65X_OLDI_DAT3_IO_CTRL, + AM65X_OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, AM65X_OLDI_CLK_IO_CTRL, + AM65X_OLDI_PWRDN_TX, val); + + } else if (dispc->feat->subrev == DISPC_AM625) { + if (power) { + switch (dispc->oldi_mode) { + case OLDI_MODE_SINGLE_LINK: + /* Power down OLDI TX 1 */ + val = AM625_OLDI1_PWRDN_TX; + break; + + case OLDI_MODE_CLONE_SINGLE_LINK: + case OLDI_MODE_DUAL_LINK: + /* No Power down */ + val = 0; + break; + + default: + /* Power down both OLDI TXes and LVDS Bandgap */ + val = AM625_OLDI0_PWRDN_TX | AM625_OLDI1_PWRDN_TX | + AM625_OLDI_PWRDN_BG; + break; + } + + } else { + /* Power down both OLDI TXes and LVDS Bandgap */ + val = AM625_OLDI0_PWRDN_TX | AM625_OLDI1_PWRDN_TX | + AM625_OLDI_PWRDN_BG; + } + + regmap_update_bits(dispc->oldi_io_ctrl, AM625_OLDI_PD_CTRL, + AM625_OLDI0_PWRDN_TX | AM625_OLDI1_PWRDN_TX | + AM625_OLDI_PWRDN_BG, val); + } } static void dispc_set_num_datalines(struct dispc_device *dispc, diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tidss/tidss_dispc_regs.h index 13feedfe5d6d..b2a148e96022 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc_regs.h +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h @@ -227,17 +227,37 @@ enum dispc_common_regs { #define DISPC_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */ /* - * OLDI IO_CTRL register offsets. On AM654 the registers are found - * from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from - * CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL - * register range. + * OLDI IO and PD CTRL register offsets. + * These registers are found in the CTRL_MMR0, where the syscon regmap should map + * + * 1. 0x14 bytes from CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL + * register range for the AM65X DSS, and + * + * 2. 0x200 bytes from OLDI0_DAT0_IO_CTRL to OLDI_LB_CTRL register range for the + * AM625 DSS. */ -#define OLDI_DAT0_IO_CTRL 0x00 -#define OLDI_DAT1_IO_CTRL 0x04 -#define OLDI_DAT2_IO_CTRL 0x08 -#define OLDI_DAT3_IO_CTRL 0x0C -#define OLDI_CLK_IO_CTRL 0x10 -#define OLDI_PWRDN_TX BIT(8) +/* -- For AM65X OLDI TX -- */ +/* Register offsets */ +#define AM65X_OLDI_DAT0_IO_CTRL 0x00 +#define AM65X_OLDI_DAT1_IO_CTRL 0x04 +#define AM65X_OLDI_DAT2_IO_CTRL 0x08 +#define AM65X_OLDI_DAT3_IO_CTRL 0x0C +#define AM65X_OLDI_CLK_IO_CTRL 0x10 + +/* Power control bits */ +#define AM65X_OLDI_PWRDN_TX BIT(8) + +/* -- For AM625 OLDI TX -- */ +/* Register offsets */ +#define AM625_OLDI_PD_CTRL 0x100 +#define AM625_OLDI_LB_CTRL 0x104 + +/* Power control bits */ +#define AM625_OLDI0_PWRDN_TX BIT(0) +#define AM625_OLDI1_PWRDN_TX BIT(1) + +/* LVDS Bandgap reference Enable/Disable */ +#define AM625_OLDI_PWRDN_BG BIT(8) #endif /* __TIDSS_DISPC_REGS_H */ From patchwork Wed Jan 25 11:35:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aradhya Bhatia X-Patchwork-Id: 48120 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp226639wrn; Wed, 25 Jan 2023 03:38:17 -0800 (PST) X-Google-Smtp-Source: AK7set/P5tjNU6ByzJK/kJokMQPGb/6EX/FwUzLJBiZlcONCfLXUIZnhI9NeCXzOMGeDQiI1DR9s X-Received: by 2002:a05:6402:289d:b0:4a0:b051:5f21 with SMTP id eg29-20020a056402289d00b004a0b0515f21mr990582edb.27.1674646697628; Wed, 25 Jan 2023 03:38:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674646697; cv=none; d=google.com; s=arc-20160816; b=Ec4XwXGkOp+xgXIfQFWUio9lT2PQSYvizy6OU9eAqJE289lWvfWRtM+TqH+V5vW/Dp Q9GXw6sGZWPtGQrJlWng7ABarkzNdh7kiWSslsUg7XV0Kt9quzRIJqflIeLcbS6MHDAp ctfwtWNRPltz9C40I7ZOmLp5WxMOhCbboyqXI5Hmo9AWHJ2LC1PxRj8HMK+uUh3M3och X0f3jNRe2rdvaYXs0jQUl//WLCHCjcU7z4npQRXwUyfMtOx6DqFE4z4/fqyMBfUKUDFB s9vuB5XINpJ9UwAMsJ+jMUNPwrZxtaRztVusGa0QYOSg4f+lOjYkvz5jSBjmZ7Riud9Z kLdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YNw16xWGpsD/uXggMokkTEYED+EdmUza/46l2QtEBuE=; b=UZ1nhcd2XNIr2tsQe6RhnqWQESsOTFEqMy4Fn1rab8MBXCPZYsozPnWj6t29tskKlK Ub+o5LqQL/cgK8QloL7oImNZaI4tliAAT1FZ/y0LWVBeTVOe2O/qVpXz16gK/wP3Mqam uxjn1Y7jtuofvnryUrSPyvm1wbke0pIuuXpSOr7YMaCfx5Z3Kq2z7rjA/Uhcr2F0C8/K FCixTQLm4WRFvl+85Q/2Q6FNjsDu3D4XNTyCSc0mKIyM/2NwMwLOcD/ddiRuNBamdOne VWEf9e8t/vxlHCYYU0/QnM9eGn/NReldhtmbUGKjvVJsP7pHK+g2p7A3T1wnIi+Pc09w SJAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=k6KWqtkU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s10-20020a056402014a00b00499e590d47esi5695993edu.36.2023.01.25.03.37.53; Wed, 25 Jan 2023 03:38:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=k6KWqtkU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235358AbjAYLgs (ORCPT + 99 others); Wed, 25 Jan 2023 06:36:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235516AbjAYLgn (ORCPT ); Wed, 25 Jan 2023 06:36:43 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 658F4568BC; Wed, 25 Jan 2023 03:36:10 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZia4120986; Wed, 25 Jan 2023 05:35:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674646544; bh=YNw16xWGpsD/uXggMokkTEYED+EdmUza/46l2QtEBuE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=k6KWqtkUR+mL9LJd4SJ3ZjdgV6+2P5hw9d8Ro5jREh0ZrLIIzB981gI1/lUb57dD7 BMj5UpYFTEbeGdjxqHyw7b86rFF9z1GBoxNBSt+ngimRK8QvzwhJUIZLMc2xd3oHHF fccgYoQt8rfHlL+/zEUyrWWp76rv99n4B4WjB9Ao= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30PBZixI013337 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Jan 2023 05:35:44 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 25 Jan 2023 05:35:43 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 25 Jan 2023 05:35:43 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30PBZght021900; Wed, 25 Jan 2023 05:35:43 -0600 From: Aradhya Bhatia To: Rob Herring , Krzysztof Kozlowski , Tomi Valkeinen , Jyri Sarha , David Airlie , Daniel Vetter CC: DRI Development List , Devicetree List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Rahul T R , Devarsh Thakkar , Jai Luthra , Jayesh Choudhary , Aradhya Bhatia Subject: [PATCH v7 6/6] drm/tidss: Enable Dual and Duplicate Modes for OLDI Date: Wed, 25 Jan 2023 17:05:29 +0530 Message-ID: <20230125113529.13952-7-a-bhatia1@ti.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230125113529.13952-1-a-bhatia1@ti.com> References: <20230125113529.13952-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755994335497541188?= X-GMAIL-MSGID: =?utf-8?q?1755994335497541188?= The AM625 DSS IP contains 2 OLDI TXes which can work together to enable 2 cloned displays of or even a single dual-link display with higher resolutions like WUXGA (1920x1200@60fps) with a reduced OLDI clock frequency. Configure the necessary register to enable and disable the OLDI TXes with required modes configurations. Signed-off-by: Aradhya Bhatia Reviewed-by: Tomi Valkeinen --- drivers/gpu/drm/tidss/tidss_dispc.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index 0e03557bc142..79ad9743a93b 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1020,8 +1020,8 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, int count = 0; /* - * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC - * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0. + * For the moment MASTERSLAVE, and SRC bits of DISPC_VP_DSS_OLDI_CFG are + * always set to 0. */ if (fmt->data_width == 24) @@ -1038,6 +1038,26 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, oldi_cfg |= BIT(0); /* ENABLE */ + switch (dispc->oldi_mode) { + case OLDI_MODE_SINGLE_LINK: + /* All configuration is done for this mode. */ + break; + + case OLDI_MODE_CLONE_SINGLE_LINK: + oldi_cfg |= BIT(5); /* CLONE MODE */ + break; + + case OLDI_MODE_DUAL_LINK: + oldi_cfg |= BIT(11); /* DUALMODESYNC */ + oldi_cfg |= BIT(3); /* data-mapping field also indicates dual-link mode */ + break; + + default: + dev_warn(dispc->dev, "%s: Incorrect oldi mode. Returning.\n", + __func__); + return; + } + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&