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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v9 1/8] x86/cpu, kvm: Add support for CPUID_80000021_EAX Date: Tue, 24 Jan 2023 10:33:12 -0600 Message-ID: <20230124163319.2277355-2-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124163319.2277355-1-kim.phillips@amd.com> References: <20230124163319.2277355-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT041:EE_|DS7PR12MB6168:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d08c122-475b-4b8b-8002-08dafe28c380 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8EM7gfCSr56GMSXDbK5YS6rzkGhRhDDqwBrawUz3Tzqpv5tUWYz/XGJtAUBNoon5b8Yc0V1CyQJ4M0wnsb1BlpNX1uGF8aarDUL5Evxv5Ne/Mzp7dFVdv48OT4MflSdUkHzryDdVzj5G5xyBbv6RhU+CmYI7zx02iIvA+NT8Qxcjt9wlrMfxZum5l4AchjQUI60egFCsSTcJjurrgN9a0mtWpeSfqGO+TlmyiZPaVbYDEwNLK1lm9zF8VvvmDM7fR5fkVsYAlGd7VelgVf9lLtQpFZOPnLSZVeuPeO5C64gQoNqOzj171dVAQ5lInLRa6PCYwe+ZGbJgv9B+uEoQP9n0jONB8JLowVaJtlE1fRGQgVZbicFT5gYeoENlPT4FQ0CPhCq95cfdttjAn8zQpnQBLQEO4NYG+f2MqdrCthMbR8S1mCnv3ZP1D96Q7kH+VrP6PeYVYvZZk1DIliRuHr3L/+HYHna8QtyaJKL3Mx/zM8wui8foVziAbdi3JelbOFx38nA33enbj1ixpi0GvY1QmjNpxb0hEi3yCnstcdi//jcz0GYBGoLxlZyeovRBB/2OB5nboTgtSNTEg+hYh92l7O/QVfVPFxMl69c9SpTz29FFcZ0tko5uak4ox5xni2UYgeLV257A3Irz+18SF2DCSlD06L/b94urc62km+hFdbK6pmlcOkQre+gpNQ26cy2S23HIsuO5Dicu44nyaltO6dA+rru3tecnMaJpsYA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199015)(36840700001)(46966006)(40470700004)(36756003)(41300700001)(86362001)(356005)(82740400003)(81166007)(7416002)(8936002)(5660300002)(4326008)(44832011)(2906002)(82310400005)(83380400001)(36860700001)(478600001)(7696005)(6916009)(26005)(8676002)(186003)(40460700003)(16526019)(40480700001)(316002)(6666004)(70206006)(70586007)(54906003)(2616005)(1076003)(336012)(426003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 16:33:45.8003 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d08c122-475b-4b8b-8002-08dafe28c380 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6168 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755923033744927165?= X-GMAIL-MSGID: =?utf-8?q?1755923033744927165?= Add support for CPUID leaf 80000021, EAX. The majority of the features will be used in the kernel and thus a separate leaf is appropriate. Include KVM's reverse_cpuid entry because features are used by KVM guests, too. [ bp: Massage commit message. ] Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeature.h | 7 +++++-- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/include/asm/disabled-features.h | 3 ++- arch/x86/include/asm/required-features.h | 3 ++- arch/x86/kernel/cpu/common.c | 3 +++ arch/x86/kvm/reverse_cpuid.h | 1 + 6 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 1a85e1fb0922..ce0c8f7d3218 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -32,6 +32,7 @@ enum cpuid_leafs CPUID_8000_0007_EBX, CPUID_7_EDX, CPUID_8000_001F_EAX, + CPUID_8000_0021_EAX, }; #define X86_CAP_FMT_NUM "%d:%d" @@ -94,8 +95,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \ + CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) || \ REQUIRED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 20)) + BUILD_BUG_ON_ZERO(NCAPINTS != 21)) #define DISABLED_MASK_BIT_SET(feature_bit) \ ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ @@ -118,8 +120,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \ + CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) || \ DISABLED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 20)) + BUILD_BUG_ON_ZERO(NCAPINTS != 21)) #define cpu_has(c, bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 123613cdae93..552bd3943370 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -13,7 +13,7 @@ /* * Defines x86 CPU feature bits */ -#define NCAPINTS 20 /* N 32-bit words worth of info */ +#define NCAPINTS 21 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index c44b56f7ffba..5dfa4fb76f4b 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -124,6 +124,7 @@ #define DISABLED_MASK17 0 #define DISABLED_MASK18 0 #define DISABLED_MASK19 0 -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20) +#define DISABLED_MASK20 0 +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21) #endif /* _ASM_X86_DISABLED_FEATURES_H */ diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h index aff774775c67..7ba1726b71c7 100644 --- a/arch/x86/include/asm/required-features.h +++ b/arch/x86/include/asm/required-features.h @@ -98,6 +98,7 @@ #define REQUIRED_MASK17 0 #define REQUIRED_MASK18 0 #define REQUIRED_MASK19 0 -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20) +#define REQUIRED_MASK20 0 +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21) #endif /* _ASM_X86_REQUIRED_FEATURES_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 5fe56f0ec9d7..094dbcd63f2a 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1093,6 +1093,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c) if (c->extended_cpuid_level >= 0x8000001f) c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); + if (c->extended_cpuid_level >= 0x80000021) + c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); + init_scattered_cpuid_features(c); init_speculation_control(c); diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 042d0aca3c92..81f4e9ce0c77 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -68,6 +68,7 @@ static const struct cpuid_reg reverse_cpuid[] = { [CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX}, [CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX}, [CPUID_7_1_EDX] = { 7, 1, CPUID_EDX}, + [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX}, }; /* From patchwork Tue Jan 24 16:33:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 47761 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2253979wrn; Tue, 24 Jan 2023 08:42:33 -0800 (PST) X-Google-Smtp-Source: AMrXdXs6icSCgHjW4/wgpo9DzVbq8NP7B1yaEWJND1N6VbKL2j2QzTOyltQAcCEQs4hins+myB9I X-Received: by 2002:a17:902:9693:b0:191:11ec:2028 with SMTP id n19-20020a170902969300b0019111ec2028mr30207905plp.46.1674578553389; Tue, 24 Jan 2023 08:42:33 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1674578553; cv=pass; d=google.com; s=arc-20160816; b=aSlH9ED1P49GANjKPwydJqs0aq7UCoXbrNSBQQJbZQCAaOLugSaUKF04Fyj4udNkTU RXR/WIPML/F1z6mOUSmffqUjMkEnDLv2kMEbtIImh3Z7JEYrpfcTZxDTU0u48WzwFzG9 CYk1eoteBnrMnFpsJ1jBCAXfs3hPZD8bd7plAlUctSFh+JCgXSn2hOczO+xCiJ+Fr7Xw LBJD+7AO2jzW2BI7gGrnofxapPSAvLtHBzfV3P54bw0xy8b+ia9F0eWX0Bebt2dt08eL BtluWV6ILDx5CyknrWF55aF776gFxCCXbWrdk0lpmTJzFjc514N6rEMKi5m7vEIemAbr zW4g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OgshsaAr/h/n5ex2a9CdYy/pLOZIxuOjhlH5l/nWcr8=; b=JSji2V4ZrAqMyFHsmUQbRu84+W8GRrcWiEaBrUS7eM8qkCcPxz7Gx6jH0O1jPl2GGa DU08HOcx2QTOU42TgPt3mKLD08vaofZfPiZFQA+LOiBe464VxZS5CPb48H/IyTw0p0Ip JlRl/qcewOVHs4CcoveG/SCY0uSI904RCTZQlXIaNbu09EldezVSERAUVqOdsEFMUHkC 11v9Sg7LolE7kJh2UdPVW5Ckip9oSOxZzG1Od3xDFbKGpQHyg450hh8pnmLUwmLtVG2i LO18bDCJeC4X9KMt4CGFEPtbwkXrfJBZ9ENkg1ZbSG6P4ezleJirYzkN3tefX4dDOQCB g3gA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=0zXEc6eJ; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v9 2/8] KVM: x86: Move open-coded cpuid leaf 0x80000021 EAX bit propagation code Date: Tue, 24 Jan 2023 10:33:13 -0600 Message-ID: <20230124163319.2277355-3-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124163319.2277355-1-kim.phillips@amd.com> References: <20230124163319.2277355-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT028:EE_|SA1PR12MB6750:EE_ X-MS-Office365-Filtering-Correlation-Id: de9b16a4-cb10-4d63-8dd1-08dafe28cd5d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /eexl8ne/eR4DzLH4oDdA3NgnLI+qycP80tltdLObGqQ+u6xjfgkaCvIa9bXL4Y8iy/LTJ4vTL4y3OxuGOSd1r6Daxl6Z6tsa4ppfniymU23Xmlkk5CUTBBkcorBD/wMuD4OCbQiShlRBzcVHU+3vfoBDbF5InTyrLyRnsV4Xm5YIZpK3y5xdA8S6a/iAdcWgkLDaz+pb7XuVvr8zyL2EnlEhKkVJ5WspnFWH97QZbycR5oYeFc2AvPgSJdDi04ueoXFb7/D4TOaAFOLTJWi9ndoHKEsMvX4CSwx+jAoIzrJGMlJYDMQ4IvV9AS45oaPu2pWGUcrjLIKkEy7VUHtb/Ne43cAnz4Y0HoCRV1M3rjA8qMGrFfdznekQ5BUiByezlOSmYNfWQ2yFt0S1yFR3sDshkMd4M9XS99mFqljcTouJ6pY290She4CDKn73MwIAt4+1BlX181Y+s5kQDkLHS/IsuXIRN4G/GKvn/A3dFcdQs62KIOFqbK7forMHPOxEO2DxDh9KWekC6yu11uYfLvf1x02NXAOo6zy3/TcePvXIMSq31GqNab57Egf7Y0Ysbk36tHRUqsuD+8+zeWQsUYVjSEAuI03Mn68hRTDQQQluxQ0F11bx0bd7VKCq8oNp/PniVm2NnMYdShyYYI+dOKrzu/4qTjfTToVISASbYjmyi6Pt6Ow9i0SlfF2I+EhlnumkQJU3qy/Xr9hM7WI9maqPTjAF32vu34Umk9jPY4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(39860400002)(136003)(396003)(451199015)(36840700001)(40470700004)(46966006)(336012)(82310400005)(426003)(316002)(47076005)(54906003)(40460700003)(2906002)(36756003)(86362001)(36860700001)(6916009)(4326008)(81166007)(40480700001)(356005)(44832011)(82740400003)(70206006)(41300700001)(7696005)(6666004)(1076003)(83380400001)(70586007)(478600001)(5660300002)(8936002)(2616005)(7416002)(26005)(16526019)(8676002)(186003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 16:34:02.3485 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de9b16a4-cb10-4d63-8dd1-08dafe28cd5d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6750 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755922881659420176?= X-GMAIL-MSGID: =?utf-8?q?1755922881659420176?= Move code from __do_cpuid_func() to kvm_set_cpu_caps() in preparation for adding the features in their native leaf. Also drop the bit description comments as it will be more self- describing once the individual features are added. Whilst there, switch to using the more efficient cpu_feature_enabled() instead of static_cpu_has(). Note, LFENCE_RDTSC and "NULL selector clears base" are currently synthetic, Linux-defined feature flags as Linux tracking of the features predates AMD's definition. Keep the manual propagation of the flags from their synthetic counterparts until the kernel fully converts to AMD's definition, otherwise KVM would stop synthesizing the flags as intended. Signed-off-by: Kim Phillips --- arch/x86/kvm/cpuid.c | 31 ++++++++++++------------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 596061c1610e..a1047763fdd3 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -741,6 +741,17 @@ void kvm_set_cpu_caps(void) 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | F(SME_COHERENT)); + kvm_cpu_cap_mask(CPUID_8000_0021_EAX, + BIT(0) /* NO_NESTED_DATA_BP */ | + BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ | + BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */ + ); + if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) + kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(2) /* LFENCE Always serializing */; + if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) + kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */; + kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */; + kvm_cpu_cap_mask(CPUID_C000_0001_EDX, F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | @@ -1222,25 +1233,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) break; case 0x80000021: entry->ebx = entry->ecx = entry->edx = 0; - /* - * Pass down these bits: - * EAX 0 NNDBP, Processor ignores nested data breakpoints - * EAX 2 LAS, LFENCE always serializing - * EAX 6 NSCB, Null selector clear base - * - * Other defined bits are for MSRs that KVM does not expose: - * EAX 3 SPCL, SMM page configuration lock - * EAX 13 PCMSR, Prefetch control MSR - * - * KVM doesn't support SMM_CTL. - * EAX 9 SMM_CTL MSR is not supported - */ - entry->eax &= BIT(0) | BIT(2) | BIT(6); - entry->eax |= BIT(9); - if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)) - entry->eax |= BIT(2); - if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) - entry->eax |= BIT(6); + cpuid_entry_override(entry, CPUID_8000_0021_EAX); break; /*Add support for Centaur's CPUID instruction*/ case 0xC0000000: From patchwork Tue Jan 24 16:33:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 47762 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2254265wrn; Tue, 24 Jan 2023 08:43:10 -0800 (PST) X-Google-Smtp-Source: AMrXdXufV6jeY/sVzCcQWy8qGfDE2LSFf1CJGX45t3QekvSyRw8LzXzlyUh1HrsC6LTOhwsUfiLM X-Received: by 2002:a17:906:d971:b0:870:7e7d:97a7 with SMTP id rp17-20020a170906d97100b008707e7d97a7mr27189230ejb.72.1674578590254; Tue, 24 Jan 2023 08:43:10 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1674578590; cv=pass; d=google.com; s=arc-20160816; b=UJ0NUPgOozov4g9GX0/iIuWgTwer4joEkxp1BxIz6KOUH/PqR6Yajm7zA9UCpS5NAQ BzfYVUxEoQCp/rarQkf1SSNpTto8zRDvNzKu+qlW8IeNXhu3X2TPsDxWlY5pU7FyfrEW LiUURthO6aap6ipMhKaiS9a4WPbVJZXyjp4aZodz16dWrRVsvIwIQQS3I3EsMG2FnsD3 DSNOHkWXuirRERC3PBcI8sG3AuJny53gF/NJBQ2TJNTgHwq9P1iULZFMytjyBySufHqq rcK3O9gfJxiigsZ/7N++5b+rp0U7coXw46tG5UutUSCS5pDTb7/Ug0fQtw2DBvzb4p3c ceCw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DhC2F3TI+mw7QDiGSq9QBBGKm8yRcn2UXO4vbye+Lt0=; b=NsK2yItBDTruD4o2Kj2NhXsGKrDYe19Iidx2/HTmd2HceLs1HmqWBjfPojPkhe8lKJ ENyGdBjYuUdizRNBY/+kNWADXGzLXpBNNZcW7pHgSHC/FZUd2gJv/Do7Ow3hozszImPu /1n3QZVALP68zlofBD25nihi4hZF1MB+CCZ6pKZlHzum6UdreEJ76Up7QQlZAebQQv/z d0S8rc550sEhR5957gp+8bphrPVT1wnSmNtJPzfbCVItDcNw4hhsG/jXynFE+2k41vAG NSMY/CgYgiceBVTvbmEhzaTm3cgjq4jgzEELPVre15eCeXwvXqV/QxXv09GdY9PTmaZ3 wj+Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=rTmOD4Q8; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v9 3/8] x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature Date: Tue, 24 Jan 2023 10:33:14 -0600 Message-ID: <20230124163319.2277355-4-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124163319.2277355-1-kim.phillips@amd.com> References: <20230124163319.2277355-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT049:EE_|BL1PR12MB5061:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b39b77a-717c-434c-e1fa-08dafe28d75f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ClAN5hh6dDf0IZT7HA3A+lqiIj3bA/SClIQrZcpqyjoXf6AS5A3zzKpUJDkJAHs4sRs+jXF5stc5achzQGpvgC+8YVofdSl+J1C2nzgpfXPpfQhHAM/i0sxGNGE2vwoO8B//zAUl8kpgf2mxwmqB+Fq3ceDC2VavmQQxmnfSM9u7W1jSbj1zce60uWPcHEQcZDlDFcu4rRvqkApFHUkGAt3A+m8RFkLA4jux3o2DwUPy8uL5FLpZQaUervtV0rlJ+ct9ilttqW7bNN/ZQNCL9sMAflaI31YXf3mI2njO3szZgpohx4xXGY7xR5WnrPu+embhER2KASTutA0IgWunvnrmMgGNMigQb78kfvDdR4HDfAKPW4sOl2PpoII54MaouEznKtsWsirGa0lBwTYZd0/gQiYsLG7aEYNIUC/+Qw7X3WfWfcB8nAVLRbvRzDqoyYcPOG29VgmApNSG/XY5WZwqNpZnQdqXb/x+dcLkAD6Jth26kmVDW49kJCIy7xOu/TLUE0ukK7jlpoMKwQ/oh7C7n0s3E5p0C8Ba6/Jx2rOyAfvyGrkcrpYQSzI2nJHDVWKXbnq20SFXQ6Dw3dSu7Q2m5cjZqVW6NCogX70Fvw+3rcBYfvkUNuAgywyttQDXF3wq1iKlQ0wtbUpaEDDZcXab20brK/wmNBHGg1O0jJVxSPqjFQe9/IvNWQWLaFOIvg0XDYx8ELRIaSr/zV0YyzYg+KSg0g7fsYsOjNtJL5s= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(136003)(396003)(376002)(451199015)(40470700004)(46966006)(36840700001)(36756003)(81166007)(356005)(2906002)(7416002)(82740400003)(8936002)(4326008)(44832011)(82310400005)(41300700001)(5660300002)(83380400001)(36860700001)(86362001)(26005)(478600001)(7696005)(186003)(16526019)(6916009)(40480700001)(54906003)(40460700003)(70206006)(2616005)(8676002)(316002)(70586007)(426003)(47076005)(336012)(1076003)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 16:34:19.1409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b39b77a-717c-434c-e1fa-08dafe28d75f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5061 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755922920067861095?= X-GMAIL-MSGID: =?utf-8?q?1755922920067861095?= The "Processor ignores nested data breakpoints" feature was being open-coded for KVM. Add the feature to its newly introduced CPUID leaf 0x80000021 EAX proper. Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 3 +++ arch/x86/kvm/cpuid.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 552bd3943370..4637fd7a84d6 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -430,6 +430,9 @@ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ +/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ +#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ + /* * BUG word(s) */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index a1047763fdd3..9764499acce2 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -742,7 +742,7 @@ void kvm_set_cpu_caps(void) F(SME_COHERENT)); kvm_cpu_cap_mask(CPUID_8000_0021_EAX, - BIT(0) /* NO_NESTED_DATA_BP */ | + F(NO_NESTED_DATA_BP) | BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ | BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */ ); From patchwork Tue Jan 24 16:33:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 47763 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2254288wrn; Tue, 24 Jan 2023 08:43:14 -0800 (PST) X-Google-Smtp-Source: AMrXdXshaOtbv8WpuG5paHtN8pmKD1oRLmy6BzCrm3PAQoS4aqmNQMGJabo7jv8B8XMWtuxlaXpY X-Received: by 2002:a05:6a00:2194:b0:58a:fa8d:ecce with SMTP id h20-20020a056a00219400b0058afa8deccemr33343506pfi.29.1674578593887; Tue, 24 Jan 2023 08:43:13 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1674578593; cv=pass; d=google.com; s=arc-20160816; b=giAhSpP8oDw/FIqq8KR5Lm4R6eOghVexgH2MgAFwa+BfgO4lynOZm61RTRsgJmSmT7 QI//cLwOVjpM/3A3fWWCZIsWI3fZm6asIzLMRGOqvvNRJ2mbr2RsBD/5c0YOZFLxrwUA L2h9i5hkuICA4an9OIjFkLVlQI14LpbWf9NxmW4YjSFnpUtaXLQkaFr1b3gtkmJjCLGK 1Lso2KvKktIGVKw0m2gpNOVH7DT264lu9VJNhn8zORkAxqhCmGCFBTwgfbfXE0z7UNLM jfmebC04xi83p44cm3f6unsf57lGGSACybFQGKpOlMEzmshtrHkM6ipOMAINd0jyrF+z +jYg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9yDG4uvs1w0obZGxxDm+raAwQbQJ/zFfwkygQNbaUkQ=; b=AMRyG/q66eVvETuOTuMkQBu4qe4y+cOvrZEvDq0e6KsC37d0Jtaub6DrkX12MoU4dC xvLYb+IzyBHnSCOhLFbL/0m1RhqSZ2SBeGyg1PRjHZ8HkNrWqDeG8cbzPOv6Dmcfy/yw ns6zoeizdn7zq9MRpeWneVDXljrBZRNPE8n4u8llBHQVbD0Kgw1hvrF44KY9+cm7WM5V y+BmPPQYhcpy8RlJOdqr7ZIwQH+wjTJqUBba00Aox/p2EqZsmeAZELhpAN0QYcWGxXsn 4kQp1u2+QS3EKEjycStoTEQADBm6m2nTJg8uX7SfjH/ZzK/kWPMYJnxN3mWp9zs320T2 Idqg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=4L1iWQMW; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v9 4/8] x86/cpu, kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf Date: Tue, 24 Jan 2023 10:33:15 -0600 Message-ID: <20230124163319.2277355-5-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124163319.2277355-1-kim.phillips@amd.com> References: <20230124163319.2277355-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT013:EE_|SN7PR12MB7022:EE_ X-MS-Office365-Filtering-Correlation-Id: 6202ddb3-4f19-4dde-135a-08dafe28de95 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bbu1aKUXRx7V+fK0gOPBOFDCKk15ThGBYdSLMPw55HL1v/+Y2gQhNTOf8FLjy4q6wVLhAbCOJpyXgMUiOcl87/8UDab7VrOCvtFQaq7bWMhoWWyBDdc2+D5j6mGOe4GRmyKX1XXYsUK9kaXhx55zMD2Bxw5oxgeOfyxPsnSaClXDyboiS956tbGMnRarbTBr3oJFI4Bnd/ggKnCNCR/WGv0GXUPB2wlfUnV0gKEgZs/LXPCJykXgPZ7zqRXYAck3VC9n1tjbiawr6up1rb40EPRzJq67qaKzWCNHvLIO20sLr1vaPt+DBZyV7RTiLOwhA6BezNJLFS4ovtsEDczFS34dwLsO+oszDn2F56d4m6DsAarMQqaZXxDaTpaLWHn1sS8XC2JOOrH7SKcinx6vy9qoCOTuH3wU0Id5hH4ePZnH4lGw+P1N/mjArtTgI1NxBNQmJ4F8xZ11lTv9NXt3cSURqOEk22b4znwQCjUVN+8PJmpsF2L8+3W2sl1SUZYkcbbVYqk1mkGZqYDHPLQF4DnU0HPREqgb9Uf0XDlnIgbv8HGmxrI2h1vopEhd/teVh17WJoiyPDcXyCZ3lO9qNiXz5t/JYclHdMqT58SbRMN707fRhqQdGgPRZV50x6AiyShYiQ5W6FI2ygNB18vZWEEMW6rBGmZHZ/c52I9cajW0Lk/D9yG/QXImsgsJ8qtqDcxPiqYr1FvsmnNC2T2v6yLGIW54KeWKKG5p59TWITs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(39860400002)(346002)(451199015)(36840700001)(40470700004)(46966006)(36860700001)(83380400001)(82740400003)(81166007)(2906002)(86362001)(44832011)(8936002)(5660300002)(356005)(41300700001)(4326008)(7416002)(82310400005)(186003)(40460700003)(40480700001)(16526019)(70206006)(6916009)(8676002)(26005)(316002)(47076005)(336012)(6666004)(426003)(70586007)(2616005)(54906003)(1076003)(478600001)(7696005)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 16:34:31.2336 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6202ddb3-4f19-4dde-135a-08dafe28de95 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7022 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755922923707329606?= X-GMAIL-MSGID: =?utf-8?q?1755922923707329606?= The LFENCE always serializing feature bit was defined as scattered LFENCE_RDTSC and its native leaf bit position open-coded for KVM. Add it to its newly added CPUID leaf 0x80000021 EAX proper. With LFENCE_RDTSC is in its proper place, the kernel's set_cpu_cap() will effectively sythesize the feature for KVM going forward. Drop the bit description comments now it's more self-describing. Also, in amd_init(), don't bother setting DE_CFG[1] any more. Signed-off-by: Kim Phillips Signed-off-by: Kim Phillips Signed-off-by: Borislav Petkov (AMD) Acked-by: Sean Christopherson --- arch/x86/include/asm/cpufeatures.h | 3 ++- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kvm/cpuid.c | 5 +---- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 4637fd7a84d6..e975822951b2 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -97,7 +97,7 @@ #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */ -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ +/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */ #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ @@ -432,6 +432,7 @@ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ +#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index f769d6d08b43..208c2ce8598a 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -956,7 +956,7 @@ static void init_amd(struct cpuinfo_x86 *c) init_amd_cacheinfo(c); - if (cpu_has(c, X86_FEATURE_XMM2)) { + if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { /* * Use LFENCE for execution serialization. On families which * don't have that MSR, LFENCE is already serializing. diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 9764499acce2..448b5de98b8f 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -742,12 +742,9 @@ void kvm_set_cpu_caps(void) F(SME_COHERENT)); kvm_cpu_cap_mask(CPUID_8000_0021_EAX, - F(NO_NESTED_DATA_BP) | - BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ | + F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */ ); - if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) - kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(2) /* LFENCE Always serializing */; if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */; kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */; From patchwork Tue Jan 24 16:33:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 47766 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2254893wrn; Tue, 24 Jan 2023 08:44:40 -0800 (PST) X-Google-Smtp-Source: AMrXdXuQF684O1dno/8Up+uRpmlWyaNbHAoBLYZjoOrfyjRfKDeDwSAwZz/dPlzg4tUsuSc8QQk9 X-Received: by 2002:a17:906:dc44:b0:86d:abca:3f55 with SMTP id yz4-20020a170906dc4400b0086dabca3f55mr35769729ejb.15.1674578680389; Tue, 24 Jan 2023 08:44:40 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1674578680; cv=pass; d=google.com; s=arc-20160816; b=fRL2hmiV4YkJhhZsNtEPTPSRZ3HPCzI8Ddkckz2RU1OpCSp5ROONVTZlqGNI2G+uqK fPUYE2fPjsNU7k5K2qpTnsvCJ93A+NGqpLLXYnc9oayM8in3IrSBJADXFZUrNMmlA+/7 ALYp40aIIQHZ7GXFc1/opLzi9KNT+isiIr+ta7hKgeq5+lS9HN/NDSVbLsihimTrhoVL w0ADGikPnCvkk4RnJTT3VCTgVNgLaGTiYLbbyilosuHz8/gGahRR/ysoWzrvpOclUNHX r/lbuDYvsSEfL7CmeIZE9Lmyijntm5PK9X2HB2AS5EeQi3PHHJ0o1bDi7wH7tdUhEUQl 9PfA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JHz2VoCROOyIzwsAcGGthYNYjnPqPZZuD4o7FeOwosY=; b=i+WCfscWmq73zh81awYdqV0Xdfz7vJjkSMVkb+GJbWmB/CExVDj1yWcgIiItdX+wvk YpbqfX5tMzypcnogB9ULl9EjbjMujU5lOOf8cz/daQgSpilli1MdscFLbrojhyx3wKzU fLveUNBI5ukzPLSJe7laS+PAcHi87vhKgO0OyBiaNOX/NRAvjnUXj+jzs7GUxDVMSdSk ALpFVZyDy43LCwRi/N+9eA8iLxGBY9T59IERdPf9SbyUDc/qTFlKeMguOvTv5yvV7QIv HavAHztWuW1G1aQTFx6/bK0HM3tDOWgg+EqNQRp6M8Jwq0MLaIoCmyKn86ZnmH9VQ04a BZJw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Fgn6d3pC; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v9 5/8] x86/cpu, kvm: Add the Null Selector Clears Base feature Date: Tue, 24 Jan 2023 10:33:16 -0600 Message-ID: <20230124163319.2277355-6-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124163319.2277355-1-kim.phillips@amd.com> References: <20230124163319.2277355-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT100:EE_|CY8PR12MB7684:EE_ X-MS-Office365-Filtering-Correlation-Id: b1673429-a5ae-4a6c-9db6-08dafe28e56f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7lYurIoC71GEojUnU83MOz02KUDQd7bWc8JtC6pODbExhmr5HJGlb0UmqDsy8NNJDUnIcdmCXHuwXVX9x1QaGYPKTPI21NVrVyazyPRMKOiYoGV5KF1/9g0SQGG5TMKwtg3yv8xVW8Gl6ByDzfT3S7l6nc3WS9DjpBNGPSAdpWFBJKKbMpD4Nngh6yl//+kA+BL/+wv+oTTzVjGWUExKNbKZbC91fqaVyYNfxURovEVyPUIxHD+1+TnOgbsRlkLx7iEHM8PCNInqKxwz5ohA0ryv/YQcmcaVAsGO0ZlGeOB3XQIopobCgm8rAR8fac3OcICOAu4Vsokrdsl+CUmXixhhAb6FHuW7rv14U9O26uDUdu1loK3y15WHFpaxN9JNWjaOdHPA6kAexuwjModTqGA/wQguCbXNoZ8J1Ny7FfEUkP+K3BphND34OBRlrO5HTN66HFaC6UVw6MNpS89I22dJo9vUG5tpY3Bz5rWUivID3NteVb10op2A8vxK6TpR8Jger/1AvvzdM6HkSr5KS1A2sRjxbO0ycqfTyZRBuSS0umXYGAhvIvdCTOM4KIkaYN4dmVuNsKitM51slpNXcPfQH+dhPeayVnv4N32RyYRGTg2crXqy2pNelYJBwMxw+bl9PDBJV7/bKpji2XouRjKduBOgXrRzaWXUXLlOZ2UIuCeTrOIpgPvcd/2eRpTG81T8U24mmzZdqxxHfNeI87Ioc0ZBsS5LgH2YZVhBiLI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199015)(46966006)(36840700001)(40470700004)(54906003)(7696005)(1076003)(70586007)(6916009)(70206006)(4326008)(8676002)(2616005)(47076005)(426003)(41300700001)(36860700001)(26005)(8936002)(186003)(44832011)(7416002)(16526019)(5660300002)(83380400001)(6666004)(2906002)(82740400003)(81166007)(316002)(478600001)(336012)(82310400005)(86362001)(40460700003)(36756003)(356005)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 16:34:42.7322 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1673429-a5ae-4a6c-9db6-08dafe28e56f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT100.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7684 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755923014416602272?= X-GMAIL-MSGID: =?utf-8?q?1755923014416602272?= The Null Selector Clears Base feature was being open-coded for KVM. Add it to its newly added native CPUID leaf 0x80000021 EAX proper. Also drop the bit description comments now it's more self-describing. [ bp: Convert test in check_null_seg_clears_base() too. ] Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/common.c | 4 +--- arch/x86/kvm/cpuid.c | 4 ++-- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index e975822951b2..bb0b483dcfd1 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -433,6 +433,7 @@ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ #define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ +#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 094dbcd63f2a..162352d42ce0 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1685,9 +1685,7 @@ void check_null_seg_clears_base(struct cpuinfo_x86 *c) if (!IS_ENABLED(CONFIG_X86_64)) return; - /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */ - if (c->extended_cpuid_level >= 0x80000021 && - cpuid_eax(0x80000021) & BIT(6)) + if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE)) return; /* diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 448b5de98b8f..e2c403cd33f1 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -743,10 +743,10 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_mask(CPUID_8000_0021_EAX, F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | - BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */ + F(NULL_SEL_CLR_BASE) | 0 /* PrefetchCtlMsr */ ); if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) - kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */; + kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */; kvm_cpu_cap_mask(CPUID_C000_0001_EDX, From patchwork Tue Jan 24 16:33:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 47765 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2254877wrn; Tue, 24 Jan 2023 08:44:37 -0800 (PST) X-Google-Smtp-Source: AMrXdXuXED2oLgBlrkTcpGaAJFYLWoHCdMY8TMLTPEGtCb1G0zotVQNfg32hjH6piHIi3oA6B68v X-Received: by 2002:a17:907:c609:b0:862:c1d5:ea1b with SMTP id ud9-20020a170907c60900b00862c1d5ea1bmr33285037ejc.8.1674578677520; Tue, 24 Jan 2023 08:44:37 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1674578677; cv=pass; d=google.com; s=arc-20160816; b=k7dKMM1TOk3kzr3ilX4ga3A9t8DwrkTdKw228e8XS5CR8q3Rn0hC1G6b/AV0os9GS/ jNBhOxqWr+ACf/ZUwuZ1SsgWsBssbj66Dw9wSKdcyetL1iTLLZ/0er9ztoJYc8Kte7u4 xyuiaRZppmSTM/67JuYshnuAgGw3GNFhmbFj6fTgj4frKz7XLkz3JDe2Yc1Kgu01ZkZA 1WLqv2EHY6TbBXah3o/nUCDIhX9Dbe4h7gZ1RuEzGG0AwmWywzQC8RRFVSU/B58/qdD5 gqXaYMqfGFgYUyyc4YBHKOVKVXFLX18WiPz47yAg2jgz3XcVU+rpXgrx6ZOCtIuCWHvb tzAw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QtECui6TSsADqcieXhOUyp4e4/9Pjdylrm4eQBeUgKk=; b=ilFZabE6ifOa+XbaRJ+G9BXBPUm2Omb8WDthAjvgDaTRRdooRMV31vKi4315bE2txf JLvFipiWVy8P03wD1sVJ2SSYnJNnKF0HD8ckZwZlPKYp8I5h9fnvz4Pnf2H6cSq6gzoZ R5MJtSSCFH3CHXdCr0LV8xyxo0eRfIe9AboCM2KD0fcsP+LVFFLHMGZzS4CBvMoIqRyn lFrwBeZaTDPe5i/xs3MzNj+r4Dccm5nhtzkGmRfhO209tGbBhe8OvIYH5O+If9+DR9Gg f5DopyOnYbIgMZ/51qe3w8jAuCu/tywiJVGRkB2IfWh9fbT1di5/mn52UfOQ7aNB//CB wXGA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="uqp/Wt+e"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v9 6/8] x86/cpu, kvm: Add the SMM_CTL MSR not present feature Date: Tue, 24 Jan 2023 10:33:17 -0600 Message-ID: <20230124163319.2277355-7-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124163319.2277355-1-kim.phillips@amd.com> References: <20230124163319.2277355-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT040:EE_|SJ0PR12MB5661:EE_ X-MS-Office365-Filtering-Correlation-Id: 04688a8e-a34b-4d9a-e5e0-08dafe28ecce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6enQsfyhcNPGp6Pvsst6UEaym+a67n/oBi9TV0jB0dt/qe/H5YY+6sUESfEtOJr9KOxD0iE3h/KewNSvivNdBsMnryV4h/gOg/SSXCXVS/qgXoy8C/Mm6uMM2zaVnjWzmgzDOEdDOZrey8T94jAVF7RkuksN0d2HNsJ0wiQvOkKtF6r5Wv+LBwIkJ8NOiKAUBrqS6/Eeei+m6HeHSaHNXD2lGyU6dENpnRDhklmwHhM3bt4DWwV4o/vhypz3EfjOxo+Jd6a5z5toY82Ab8klCXbXc30W/7yvxCkb+Nc0mdGRYBYnZqoRgqHsXeCFlMuywK3ES1psvsz8hQFM4MCb+o/ZTQ+NyWCXCuoZXeH5f9KHXNVQ8Ky5csXN5AY6pvY1+0filtCgbkqf8suHDZzpX2Da6RgKjtoj+UqT119f4+Mq08zocArIe12I8fhjHqP2ZP3A1bG0FGpBI3AiEgrsQ/hfi3M1Q7FAnYAkbvi/H5aKfdiVuuN+3qdpIK/o8RC79Lvsrk9KvzSJcI61TW2s+nlhqgGfqLE0LaL7SHm5Sw07HctionVJIPUMgBCzDx23f8ddkOjtyzwaBV7369HvFQfOh2avJa2/9mGmjRjIc3+1ZmTRN6TMUVurw/GeiFkIiZqWGbpQpNlRr+dZH4w+WAT5Ib3wVPPFFRmbc2C+C8bIV3O9ttnVpmIABgdLOVvXrhV3UojmI3FOyu5UX7B6WflZc7shb0iemJbwdIlULME= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199015)(40470700004)(46966006)(36840700001)(36756003)(41300700001)(86362001)(81166007)(356005)(82740400003)(7416002)(8936002)(5660300002)(4326008)(44832011)(2906002)(82310400005)(83380400001)(36860700001)(478600001)(7696005)(6916009)(26005)(8676002)(186003)(40460700003)(16526019)(40480700001)(316002)(6666004)(70206006)(70586007)(54906003)(2616005)(1076003)(336012)(426003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 16:34:55.1006 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04688a8e-a34b-4d9a-e5e0-08dafe28ecce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5661 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755923011241217544?= X-GMAIL-MSGID: =?utf-8?q?1755923011241217544?= The SMM_CTL MSR not present feature was being open-coded for KVM. Add it to its newly added CPUID leaf 0x80000021 EAX proper. Also drop the bit description comments now the code is more self-describing. Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index bb0b483dcfd1..8ef89d595771 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -434,6 +434,7 @@ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ #define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ #define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */ +#define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* "" SMM_CTL MSR is not present */ /* * BUG word(s) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index e2c403cd33f1..8519f4a993f7 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -747,7 +747,7 @@ void kvm_set_cpu_caps(void) ); if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); - kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */; + kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR); kvm_cpu_cap_mask(CPUID_C000_0001_EDX, F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | From patchwork Tue Jan 24 16:33:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 47768 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2255041wrn; Tue, 24 Jan 2023 08:45:02 -0800 (PST) X-Google-Smtp-Source: AMrXdXsHyY3JT6Oy+53sJydrhXnYl1QpmgPM2O7ibD+43Q2X2rE6lztwtprMnEvsm4wIn0Tnp8+6 X-Received: by 2002:aa7:c549:0:b0:46a:732e:fd29 with SMTP id s9-20020aa7c549000000b0046a732efd29mr40632421edr.42.1674578702687; Tue, 24 Jan 2023 08:45:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1674578702; cv=pass; d=google.com; s=arc-20160816; b=ONLw3Ru+7J+9nre681oazZRYJ41NFGWAdURqLNBjUUIi9eDqJclIIxuwVtvBrIq0fi lr0f9L4fJm8tC5jbxC1ec8TMjROFD083KFDXuCIYkzgbUtvxIjRVcQ3Kzo8C596c3bO/ yAo+wFq4DTZwKQqsV5RBCLJLgNyaZ9F4vG2WZOS6iYkjDqE1kdh6gWHJ7fLXyAreDgH1 KQ63ZoH6kbOImmjUFdtuRDGAVs15R+t4LOLxHXduSPVcxxuZNMwTE7VPOncjEHol1OWP rNd/o37HEnp6myr8pumidTXXGnM8kLhBYLPPM9OpMtedmWOkdkuv1u8/OY0GLKNf3U5U CbAw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2B+aDdAb9GOgPhjnJ8umNSx7UrhOhfi7KTSQrMiP5ho=; b=gAMGCVZaFjr81dT5E9XLja75uam043J26z62JLE7ZkWSH98/t9N9Gu+x2dsYlAeFaB xS7IL55f7gE3iGreSucGj7Ydo9eUezc8WjYGzlNb+X83CHMT/ytTDmgl0vDEV2Avx1vK OmgVjo1CYwhgZ1uef5+///a6NcHiyZOjNSaO/sP98y0P2dahsPq7hzsHLKI/GkjNtas9 SUQfXrvhdTfFD6GQkUtY5UTmVVN0OKXjqembeYpi5xfg6pUm2K4wO+XOsV9vuzVEcrMe I5aMXC6hJZ89V0PgMT+M0vaUdyC4ZA2RZI+B5og9EGJ4r5xLxM1Mh4Nn3kWcVR74kuMO 491Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=FcslhyYG; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v9 7/8] x86/cpu: Support AMD Automatic IBRS Date: Tue, 24 Jan 2023 10:33:18 -0600 Message-ID: <20230124163319.2277355-8-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124163319.2277355-1-kim.phillips@amd.com> References: <20230124163319.2277355-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT065:EE_|SJ0PR12MB7068:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c60c30d-aa9f-4d88-6fac-08dafe28f374 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RBp/20bLSsD/4xjhRILvWwQcYQ6KorlN5OwDxD5sT0IIjh3hIM4w+Rw51Pipv0buIoIY9WHPGfiWDzJjGRraZBORZ3qKTPd8HY6KP6vMnNo9n/xgxUfuFFOk2MbvSHEvJH5jKMQquObTKMiNVh23aq+Vdwrf54aHtMpD9dWCLrvXc3rgoN5g0eRVhIGVdTfMDVJ2OT17FAiu2EhagpUTnxruLNOgvR+QDv1/OaXiYxQiaTpMq4ubqECVI+d5sVU1/Yp3PDBRv3yKtNZWLp3/PoG/tiL8xKcLvfj5AbM5wrjjoR2h3tHFPmIxQtelmyERug+2EMbryVpKZtVc1oxXfVdQWRm+5PlQ4s4gU5ckBAVIQFGWWh0UlzrXlTQNI5S+FzKpcjSb/4v/MRW7HE35iuORGJaJ18O59qVb0qU9VauidrdK5SR//7V+PsdMtQhk/aKTPXehjKM+QYpSx/ckhYgfxBgJmP89/56eifhrCB1CKXcaiSALCXH3/BbDmViO0HqNXemCoRYDUfyI3t7ypwdo7su79Y2lWyqkmTy94XGupxI5ckQUuaSW75OcuXSdaZLpzd8pjtXAYr4BH+A7xrJzdiESKDfyvCMQ+V1giOgfBmesTr59jPL7WEmhK6pbda74dWUanDFrQc5zRObkKYA9EBB4j7TwQkQed2LQfs5T6i4vaJuvRfpcjKpBT2skYSd3Wv+cAC4ZuylaWNfrlgEjkwKMstRNklZYwid6sdk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(346002)(376002)(136003)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(6916009)(16526019)(36860700001)(316002)(36756003)(70206006)(70586007)(54906003)(4326008)(186003)(26005)(40480700001)(6666004)(83380400001)(7696005)(86362001)(478600001)(8676002)(356005)(2616005)(81166007)(336012)(1076003)(7416002)(5660300002)(44832011)(47076005)(8936002)(40460700003)(426003)(82740400003)(2906002)(41300700001)(82310400005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2023 16:35:06.2362 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c60c30d-aa9f-4d88-6fac-08dafe28f374 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7068 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755923037897777720?= X-GMAIL-MSGID: =?utf-8?q?1755923037897777720?= The AMD Zen4 core supports a new feature called Automatic IBRS. It is a "set-and-forget" feature that means that, like Intel's Enhanced IBRS, h/w manages its IBRS mitigation resources automatically across CPL transitions. The feature is advertised by CPUID_Fn80000021_EAX bit 8 and is enabled by setting MSR C000_0080 (EFER) bit 21. Enable Automatic IBRS by default if the CPU feature is present. It typically provides greater performance over the incumbent generic retpolines mitigation. Reuse the SPECTRE_V2_EIBRS spectre_v2_mitigation enum. AMD Automatic IBRS and Intel Enhanced IBRS have similar enablement. Add NO_EIBRS_PBRSB to cpu_vuln_whitelist, since AMD Automatic IBRS isn't affected by PBRSB-eIBRS. The kernel command line option spectre_v2=eibrs is used to select AMD Automatic IBRS, if available. Signed-off-by: Kim Phillips Acked-by: Dave Hansen Signed-off-by: Josh Poimboeuf Acked-by: Borislav Petkov (AMD) --- Documentation/admin-guide/hw-vuln/spectre.rst | 6 +++--- .../admin-guide/kernel-parameters.txt | 6 +++--- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/bugs.c | 20 +++++++++++-------- arch/x86/kernel/cpu/common.c | 19 ++++++++++-------- 6 files changed, 32 insertions(+), 22 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/spectre.rst b/Documentation/admin-guide/hw-vuln/spectre.rst index c4dcdb3d0d45..3fe6511c5405 100644 --- a/Documentation/admin-guide/hw-vuln/spectre.rst +++ b/Documentation/admin-guide/hw-vuln/spectre.rst @@ -610,9 +610,9 @@ kernel command line. retpoline,generic Retpolines retpoline,lfence LFENCE; indirect branch retpoline,amd alias for retpoline,lfence - eibrs enhanced IBRS - eibrs,retpoline enhanced IBRS + Retpolines - eibrs,lfence enhanced IBRS + LFENCE + eibrs Enhanced/Auto IBRS + eibrs,retpoline Enhanced/Auto IBRS + Retpolines + eibrs,lfence Enhanced/Auto IBRS + LFENCE ibrs use IBRS to protect kernel Not specifying this option is equivalent to diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 0ee891133d76..1d2f92edb5a1 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5729,9 +5729,9 @@ retpoline,generic - Retpolines retpoline,lfence - LFENCE; indirect branch retpoline,amd - alias for retpoline,lfence - eibrs - enhanced IBRS - eibrs,retpoline - enhanced IBRS + Retpolines - eibrs,lfence - enhanced IBRS + LFENCE + eibrs - Enhanced/Auto IBRS + eibrs,retpoline - Enhanced/Auto IBRS + Retpolines + eibrs,lfence - Enhanced/Auto IBRS + LFENCE ibrs - use IBRS to protect kernel Not specifying this option is equivalent to diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 8ef89d595771..fdb8e09234ba 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -434,6 +434,7 @@ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ #define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ #define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */ +#define X86_FEATURE_AUTOIBRS (20*32+ 8) /* "" Automatic IBRS */ #define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* "" SMM_CTL MSR is not present */ /* diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4e0a7ad17083..ad35355ee43e 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ #define EFER_SCE (1<<_EFER_SCE) #define EFER_LME (1<<_EFER_LME) @@ -33,6 +34,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) /* Intel MSRs. Some also available on other CPUs */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 4a0add86c182..cf81848b72f4 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1238,9 +1238,9 @@ static const char * const spectre_v2_strings[] = { [SPECTRE_V2_NONE] = "Vulnerable", [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines", [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE", - [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS", - [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE", - [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines", + [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced / Automatic IBRS", + [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced / Automatic IBRS + LFENCE", + [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced / Automatic IBRS + Retpolines", [SPECTRE_V2_IBRS] = "Mitigation: IBRS", }; @@ -1309,7 +1309,7 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { - pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n", + pr_err("%s selected but CPU doesn't have Enhanced or Automatic IBRS. Switching to AUTO select\n", mitigation_options[i].option); return SPECTRE_V2_CMD_AUTO; } @@ -1495,8 +1495,12 @@ static void __init spectre_v2_select_mitigation(void) pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); if (spectre_v2_in_ibrs_mode(mode)) { - x86_spec_ctrl_base |= SPEC_CTRL_IBRS; - update_spec_ctrl(x86_spec_ctrl_base); + if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) { + msr_set_bit(MSR_EFER, _EFER_AUTOIBRS); + } else { + x86_spec_ctrl_base |= SPEC_CTRL_IBRS; + update_spec_ctrl(x86_spec_ctrl_base); + } } switch (mode) { @@ -1580,8 +1584,8 @@ static void __init spectre_v2_select_mitigation(void) /* * Retpoline protects the kernel, but doesn't protect firmware. IBRS * and Enhanced IBRS protect firmware too, so enable IBRS around - * firmware calls only when IBRS / Enhanced IBRS aren't otherwise - * enabled. + * firmware calls only when IBRS / Enhanced / Automatic IBRS aren't + * otherwise enabled. * * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because * the user might select retpoline on the kernel command line and if diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 162352d42ce0..8ce67a8a61a6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1229,8 +1229,8 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ - VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), - VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), + VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), + VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), /* Zhaoxin Family 7 */ VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), @@ -1341,8 +1341,16 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); - if (ia32_cap & ARCH_CAP_IBRS_ALL) + /* + * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature + * flag and protect from vendor-specific bugs via the whitelist. + */ + if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) { setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); + if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && + !(ia32_cap & ARCH_CAP_PBRSB_NO)) + setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); + } if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { @@ -1404,11 +1412,6 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) setup_force_cpu_bug(X86_BUG_RETBLEED); } - if (cpu_has(c, X86_FEATURE_IBRS_ENHANCED) && - !cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && - !(ia32_cap & ARCH_CAP_PBRSB_NO)) - setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); - if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) return; From patchwork Tue Jan 24 16:33:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 47769 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2255325wrn; Tue, 24 Jan 2023 08:45:36 -0800 (PST) X-Google-Smtp-Source: AMrXdXv6yq/dqTeoUVeQg7dKbwJJSfkY2oi+i96lac6/KbZMFcKF0jEMqsL4CG3lHKU8UAa3XH8i X-Received: by 2002:a05:6a00:288c:b0:586:8ead:a8e8 with SMTP id ch12-20020a056a00288c00b005868eada8e8mr30886263pfb.8.1674578736562; Tue, 24 Jan 2023 08:45:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1674578736; cv=pass; d=google.com; s=arc-20160816; b=NOftO3kuAtSXR6Ag3n2tREeqU5/b1aMn2C+sRW4xGSKxOKlUM5wIk4fGoPbeLdNOSe hDzVtwx4n22Z5K6w31XnTPF5Hgb5qPTy57j/fV5CRjhdA9MgxgR5aGnZkwaGHa4bX18l 0A+fvy5QpnE5f1x0i8I/6zIGLHLGt7ovv4kwCrclo7M6V1UE9ZhS7S+ELALG7jvlEVvR cmTrWB7REfUiyQmAWzmXq/XBK84IlvfuPNJbsi9c3IbuSYtPznGMKIFD8rV445jtxAub +S5Ob7RftOantCeByPx5KNDpjkytiRKMTywjdlkBDL8S0blmel65mJyim8qaGP8SV62z FNPw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XOrXxt4az/1m3xxxc8phYeF2k3nu+oPU/LTvGHktjZg=; b=v/NugcLCoisxO6IR88GU1voveLTNBubEsPdycCrG2apdZh5qEglZGXZMlWhP2TF7Mn Cbca7P6sKn4Jbeo0X+e2LQyDXIxSTNZ3M3qpMfSOIHcBGesYiTEfJpDBeKFQ5/jFP7+6 fg3s+q2PgZ9Mig3/w59EHxs1Aknae9AeCq3YDzouEH6bIZkyIPn4JKWJSfhql/zAPiKM Kxr67OcNV511PzYQIKJaBqVrFkGDHvVk9qR+RMOkyYCvpQIV072pb+uqZGcJYXpdHeG7 xaG/Ml7BDxPd8LWdyafIq/oXCKOZcUHRYv/Q6KWjMCu8NJCmvtkjxew89aehzS6BqYZ8 0X9w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Szpok9lg; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Kim Phillips --- arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/svm/svm.c | 3 +++ arch/x86/kvm/x86.c | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 8519f4a993f7..f29d35c20c7e 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -743,7 +743,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_mask(CPUID_8000_0021_EAX, F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | - F(NULL_SEL_CLR_BASE) | 0 /* PrefetchCtlMsr */ + F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ ); if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9a194aa1a75a..60c7c880266b 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4969,6 +4969,9 @@ static __init int svm_hardware_setup(void) tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX); + if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) + kvm_enable_efer_bits(EFER_AUTOIBRS); + /* Check for pause filtering support */ if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { pause_filter_count = 0; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index da4bbd043a7b..8dd0cb230ef5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1685,6 +1685,9 @@ static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) { + if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS)) + return false; + if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) return false;