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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m15-20020a056402430f00b0043d54ba0a4dsi2656383edc.327.2022.10.14.04.36.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 04:36:57 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=wB+dOvVU; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 007EB385842F for ; Fri, 14 Oct 2022 11:36:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 007EB385842F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665747415; bh=YD64XmVQ6n+CrnQkD5s1IAYvxoP5GsLuU9hZi+1BIU4=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=wB+dOvVUt1lRnifhzx7wD/nnaprnb3QUNkqMAjctZqE/hQOU8xFLPdO0rsemgk/9J 9Nt9vZf9mgIg16gYS5ZYHiEzF6pxF6x1xPjjDuDDVes7uPL1vJE/grcZekR9OyuKjt S8nmP0HQ+eTecrIpnbfTJ7+xl9pQY0wdJONuV2L4= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by sourceware.org (Postfix) with ESMTPS id 3C58E385AC1D for ; Fri, 14 Oct 2022 11:36:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3C58E385AC1D Received: by mail-pj1-x102c.google.com with SMTP id a6-20020a17090abe0600b0020d7c0c6650so7705420pjs.0 for ; Fri, 14 Oct 2022 04:36:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-disposition:mime-version:message-id:subject:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YD64XmVQ6n+CrnQkD5s1IAYvxoP5GsLuU9hZi+1BIU4=; b=sMZdKvcak6zZBBVwV2XnsOkSODZAgEKTGcPwuizzQt/E4twG91s619Y7sbW4pw35nk 8GJ/tdUOGmnAP/WmP0/zlvglrHqIRZi3JZxIfwZaB6CNghJvb5mAJ11ETXi0OATrN1xV //Y/Y/1+P8lFhiNQMNRT/61zyEf2WWtJlE1zTt+m7YWlYxGQyPVaeYwK29lMlYH/7zfr KKi7le8wcujJV7NpUwUu3HitK30dSvvKscAVglFqeI9HBTHmmOo858qAFV0iyXdzSQly cJ2l8qBW9QM4TVCjX9Mhws/lJbYBk5BrPxTzoBSjldgD/11eiCiKlhYyMIxb4zkdDXYm Tw4A== X-Gm-Message-State: ACrzQf2gnWfVAgIENXOSetWeoFsfQzEDySlIVHyG3IB45bbm289XZiOv mKjOP7NmoHZ5UcyFNFCuNe1Lmh0/T+8= X-Received: by 2002:a17:902:f546:b0:177:ed6b:4696 with SMTP id h6-20020a170902f54600b00177ed6b4696mr4688178plf.171.1665747402729; Fri, 14 Oct 2022 04:36:42 -0700 (PDT) Received: from squeak.grove.modra.org ([2406:3400:51d:8cc0:16f7:73a:410:46e6]) by smtp.gmail.com with ESMTPSA id f15-20020a170902684f00b00176b0dec886sm1550602pln.58.2022.10.14.04.36.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 04:36:41 -0700 (PDT) Received: by squeak.grove.modra.org (Postfix, from userid 1000) id 887021142DF3; Fri, 14 Oct 2022 22:06:39 +1030 (ACDT) Date: Fri, 14 Oct 2022 22:06:39 +1030 To: binutils@sourceware.org Subject: PowerPC SPE disassembly and tests Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-3035.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alan Modra via Binutils From: Alan Modra Reply-To: Alan Modra Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746662764126445236?= X-GMAIL-MSGID: =?utf-8?q?1746662764126445236?= Where sub and subf forms of an instruction exist we generally disassemble to the extended insn sub form rather than the underlying machine subf instruction. Do so for SPE evsubw and evsubiw too. spe_ambiguous.d always was a bit too optimistic. There is no sensible way to disassemble identical bytes back to different and original source. Instead change the test to check -Mraw results. gas/ * testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test. * testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than evsubfw and evsubifw. * testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent to evnot. * testsuite/gas/ppc/spe_ambiguous.d: Test Mraw. opcodes/ * ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and evsubiw before evsubifw and mark EXT. diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 9a18ce2e2ff..1bfd375ccd6 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -94,10 +94,7 @@ run_dump_test "efs2" run_dump_test "spe2" run_dump_test "spe2-checks" run_dump_test "spe" - -setup_xfail "*-*-*" run_dump_test "spe_ambiguous" - run_dump_test "altivec" run_dump_test "altivec2" run_dump_test "altivec3" diff --git a/gas/testsuite/gas/ppc/spe.d b/gas/testsuite/gas/ppc/spe.d index 958bdf1e57b..7429879329b 100644 --- a/gas/testsuite/gas/ppc/spe.d +++ b/gas/testsuite/gas/ppc/spe.d @@ -10,10 +10,10 @@ Disassembly of section .text: 00000000 <.text>: .*: 10 01 12 00 evaddw r0,r1,r2 .*: 10 1f 12 02 evaddiw r0,r2,31 -.*: 10 01 12 04 evsubfw r0,r1,r2 -.*: 10 01 12 04 evsubfw r0,r1,r2 -.*: 10 1f 12 06 evsubifw r0,31,r2 -.*: 10 1f 12 06 evsubifw r0,31,r2 +.*: 10 01 12 04 evsubw r0,r2,r1 +.*: 10 01 12 04 evsubw r0,r2,r1 +.*: 10 1f 12 06 evsubiw r0,r2,31 +.*: 10 1f 12 06 evsubiw r0,r2,31 .*: 10 01 02 08 evabs r0,r1 .*: 10 01 02 09 evneg r0,r1 .*: 10 01 02 0a evextsb r0,r1 diff --git a/gas/testsuite/gas/ppc/spe_ambiguous.d b/gas/testsuite/gas/ppc/spe_ambiguous.d index 2e0b1d3594f..3cbbb1a1610 100644 --- a/gas/testsuite/gas/ppc/spe_ambiguous.d +++ b/gas/testsuite/gas/ppc/spe_ambiguous.d @@ -1,6 +1,6 @@ #as: -a32 -mbig -mvle -#objdump: -d -Mspe -#name: Validate SPE instructions +#objdump: -d -Mspe -Mraw +#name: Validate SPE raw instructions .*: +file format elf.*-powerpc.* @@ -8,8 +8,8 @@ Disassembly of section .text: 00000000 <.text>: 0: 10 01 12 04 evsubfw r0,r1,r2 - 4: 10 01 12 04 evsubw r0,r2,r1 + 4: 10 01 12 04 evsubfw r0,r1,r2 8: 10 1f 12 06 evsubifw r0,31,r2 - c: 10 1f 12 06 evsubiw r0,r2,31 - 10: 10 01 12 18 evnor r0,r1,r2 - 14: 10 01 0a 18 evnot r0,r1 + c: 10 1f 12 06 evsubifw r0,31,r2 + 10: 10 01 0a 18 evnor r0,r1,r1 + 14: 10 01 0a 18 evnor r0,r1,r1 diff --git a/gas/testsuite/gas/ppc/spe_ambiguous.s b/gas/testsuite/gas/ppc/spe_ambiguous.s index b60e02bfb7f..97de2eb3a96 100644 --- a/gas/testsuite/gas/ppc/spe_ambiguous.s +++ b/gas/testsuite/gas/ppc/spe_ambiguous.s @@ -17,5 +17,5 @@ evsubw rS, rB, rA evsubifw rS, UIMM, rB evsubiw rS, rB, UIMM - evnor rS, rA, rB + evnor rS, rA, rA evnot rS, rA diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 1d274c39147..e1b67647da6 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -5201,12 +5201,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"evsubw", VX (4, 516), VX_MASK, PPCSPE, EXT, {RS, RB, RA}}, {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, -{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vsrq", VX (4, 517), VX_MASK, POWER10, 0, {VD, VA, VB}}, +{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, EXT, {RS, RB, UIMM}}, {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, -{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},