From patchwork Fri Jan 20 22:40:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 46654 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp462994wrn; Fri, 20 Jan 2023 14:41:44 -0800 (PST) X-Google-Smtp-Source: AMrXdXsk0rHnS5b0M4dbr7v3i3BxUn3v3IWg/1GdYyUHfc3gWdY/0BpUj3CvMy97cb12CxrpmX0w X-Received: by 2002:a17:90a:fcf:b0:229:eec1:a488 with SMTP id 73-20020a17090a0fcf00b00229eec1a488mr7085143pjz.20.1674254504523; Fri, 20 Jan 2023 14:41:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674254504; cv=none; d=google.com; s=arc-20160816; b=oHgkyPTTrB/ZjgwGY/8l7PBkYhS5QwOPYqoqGTK3GxT9cnHRPC+BGbHkE5u+ZbhQGp zIJ1xcai0sCtvgXJax3lvqtGCH/iVN7WHY/pPO8ZLCq3wZ+seMAZdaWQb8MswsTt9nfb 5KKSQ40bgwEkqT3OarGIKYpjxYo4jXFQ4qYmHpUFY/kOCbANF/gC10CI+Rr2UWqw7ZwO oq/NgeG07T5UtFk8qeQYBMBUY57jbdjSolIY+KKO9/S8aAol3Hec1MuNbGNQdudZREuh ybGJdnJnLH0EooFub+TrKwP7PkIdkMYSGDwCRjyG7/Mqh51vkGYI4jbWQpBj8dX+2uhf uOaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xk0c8KXT0x8OjHkq5e1tXzEKZP0LwHWjl4YMIq+eX4M=; b=dtrsLuduJ/oHFjRnS44uRh/8w3zaLw1xqpQKQGM5gKNvsjaRBB8ggGB+9hSrL3dFoY bYrA8YBYy9zpZ9vIr66fznUma2f0a7CRRi5a6Sm5FsSAmkDrYQ1Bxz1b9XENmunn/+KY FdGHY7pIRI8rEXoesO98toflPqJKcTYUXcGRVm55NeQHo+98OheG16VGPhTkIFITY47i A2S6zmfYHaUrQiZJtnjFJzEg1ZOv439WON4usXHfFXJ0Y/yeS1qijF47PvQ7Aq6VzXjG jK6DiGjOYstVciNc7wJFMKGctNIZfjQ0QdaxcpAARfGQc1X8ucin3u2ufaJW/lnHYzjZ eZ9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2022082101 header.b=r1hdBTaI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=walle.cc Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r5-20020a17090a690500b0021d20da7a5fsi3487549pjj.120.2023.01.20.14.41.31; Fri, 20 Jan 2023 14:41:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2022082101 header.b=r1hdBTaI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=walle.cc Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229744AbjATWk2 (ORCPT + 99 others); Fri, 20 Jan 2023 17:40:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229634AbjATWkX (ORCPT ); Fri, 20 Jan 2023 17:40:23 -0500 Received: from mail.3ffe.de (0001.3ffe.de [159.69.201.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9993080BA0; Fri, 20 Jan 2023 14:40:22 -0800 (PST) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 01322168F; Fri, 20 Jan 2023 23:40:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1674254420; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xk0c8KXT0x8OjHkq5e1tXzEKZP0LwHWjl4YMIq+eX4M=; b=r1hdBTaIxDJbu5FJo/TGTrKSx6Ixn1HeMHxI6bmZxa1kMUyMpDoL37A9OPInreH/ITaS05 9sSoGcdYywRCTFne161/qsrmFCZ9AkPIyi8QDnkIUv/3VCc75LfKio8BDyr7DWeQEu8YxP xvS3//4U9YuS3pMdurAAaPCJyFGfwDSrsU9zJRDJPpL9rZCEzfUpl0H7u9u87YGIP4QK8L L1ewM3ad6IOLrFb2EqPNVKRuXPJwC6uheXJxH/eUOO/wg7+tIvV4ELjhlPshDszRWbQALz 9X2786k6ggAynG+VGKmXkaHfXYbt0+xcyyThCEnlLeFvRGmqWt6vH2TvuiKWsQ== From: Michael Walle To: Yisen Zhuang , Salil Mehta , "David S . Miller" , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Broadcom internal kernel review list , Andrew Lunn , Heiner Kallweit , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Xu Liang Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH net-next 1/5] net: phy: add error checks in mmd_phy_indirect() and export it Date: Fri, 20 Jan 2023 23:40:07 +0100 Message-Id: <20230120224011.796097-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230120224011.796097-1-michael@walle.cc> References: <20230120224011.796097-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755583091625559128?= X-GMAIL-MSGID: =?utf-8?q?1755583091625559128?= Add missing error checks in mmd_phy_indirect(). The error checks need to be disabled to retain the current behavior in phy_read_mmd() and phy_write_mmd(). Therefore, add a new parameter to enable the error checks. Add a thin wrapper __phy_mmd_indirect() which is then exported. Signed-off-by: Michael Walle --- drivers/net/phy/phy-core.c | 44 +++++++++++++++++++++++++++++++------- include/linux/phy.h | 2 ++ 2 files changed, 38 insertions(+), 8 deletions(-) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index a64186dc53f8..c9c92b95ace2 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -524,19 +524,47 @@ int phy_speed_down_core(struct phy_device *phydev) return 0; } -static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad, - u16 regnum) +static int mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad, + u16 regnum, bool check_rc) { + int ret; + /* Write the desired MMD Devad */ - __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad); + ret = __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad); + if (check_rc && ret) + return ret; /* Write the desired MMD register address */ - __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); + ret = __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); + if (check_rc && ret) + return ret; /* Select the Function : DATA with no post increment */ - __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, - devad | MII_MMD_CTRL_NOINCR); + ret = __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, + devad | MII_MMD_CTRL_NOINCR); + if (check_rc && ret) + return ret; + + return 0; +} + +/** + * __phy_mmd_indirect - prepare an indirect C45 register access + * + * @bus: the target MII bus + * @phy_addr: PHY address on the MII bus + * @devad: The target MMD (0..31) + * @regnum: The target register on the MMD (0..65535) + * + * Prepare an indirect C45 read or write transfer using the MII_MMD_CTRL and + * MII_MMD_DATA registers in C22 space. + */ +int __phy_mmd_indirect(struct mii_bus *bus, int phy_addr, int devad, + u16 regnum) +{ + return mmd_phy_indirect(bus, phy_addr, devad, regnum, true); } +EXPORT_SYMBOL(__phy_mmd_indirect); /** * __phy_read_mmd - Convenience function for reading a register @@ -563,7 +591,7 @@ int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) struct mii_bus *bus = phydev->mdio.bus; int phy_addr = phydev->mdio.addr; - mmd_phy_indirect(bus, phy_addr, devad, regnum); + mmd_phy_indirect(bus, phy_addr, devad, regnum, false); /* Read the content of the MMD's selected register */ val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA); @@ -619,7 +647,7 @@ int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) struct mii_bus *bus = phydev->mdio.bus; int phy_addr = phydev->mdio.addr; - mmd_phy_indirect(bus, phy_addr, devad, regnum); + mmd_phy_indirect(bus, phy_addr, devad, regnum, false); /* Write the data into MMD's selected register */ __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val); diff --git a/include/linux/phy.h b/include/linux/phy.h index fbeba4fee8d4..f7a5e110f95c 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1228,6 +1228,8 @@ int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum); __ret; \ }) +int __phy_mmd_indirect(struct mii_bus *bus, int phy_addr, int devad, + u16 regnum); /* * __phy_read_mmd - Convenience function for reading a register * from an MMD on a given PHY. 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(unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id C6DFF1692; Fri, 20 Jan 2023 23:40:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1674254421; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BDVuKXh0Kd5QNrze0FujuDJa3AT6+b9OQz14bZfixL4=; b=tgAxm0nUOZazHv5XPuvTMF39YrBySknoyWVd6o/fYI1adapxtfqWEeaySA5Z5vGPdvro4f O1VL1SWycmgdTT8feGCYXPc5l8SMD+kBNb04YNSZFAbvjzdOgBmQ9DfnT8DweXA282C52J IfJ37nPZENgCOrcDGNDgRIRxiSCwjnmbchADTc/T4pZJLOkmkpGEH1DQdNTX/ipfYoQFNs WUkyaQVHfMjZl5Qmr+P4+CLCFsnk2rjS1KTXFLIS5ygpWA1tZh665g+IBq4WCtspBJqsP+ L93zd9bxDXLUb68CZuStHpwZGRV8fSXOfsO/TmJWYpR6uXYrTWdY4stHl571fw== From: Michael Walle To: Yisen Zhuang , Salil Mehta , "David S . Miller" , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Broadcom internal kernel review list , Andrew Lunn , Heiner Kallweit , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Xu Liang Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH net-next 2/5] net: phy: support indirect c45 access in get_phy_c45_ids() Date: Fri, 20 Jan 2023 23:40:08 +0100 Message-Id: <20230120224011.796097-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230120224011.796097-1-michael@walle.cc> References: <20230120224011.796097-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755583112161174630?= X-GMAIL-MSGID: =?utf-8?q?1755583112161174630?= There are some PHYs, namely the Maxlinear GPY215, whose driver is explicitly supporting C45-over-C22 access. At least that was the intention. In practice, it cannot work because get_phy_c45_ids() will always issue c45 register accesses. There is another issue at hand: the Microchip LAN8814, which is a c22 only quad PHY, has issues with c45 accesses on the same bus and its address decoder will find a match in the middle of another c45 transaction. This will lead to spurious reads and writes. The reads will corrupt the c45 in flight. The write will lead to random writes to the LAN8814 registers. As a workaround for PHYs which support C45-over-C22 register accesses, we can make the MDIO bus c22-only. For both reasons, extend the register accesses in get_phy_c45_ids() to allow indirect C45 accesses over the C22 registers. Signed-off-by: Michael Walle --- drivers/net/phy/phy_device.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 9ba8f973f26f..9777a7fd180a 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -698,6 +698,28 @@ struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id, } EXPORT_SYMBOL(phy_device_create); +static int mdiobus_probe_mmd_read(struct mii_bus *bus, int prtad, int devad, + u16 regnum) +{ + int ret; + + if (bus->read_c45) + return mdiobus_c45_read(bus, prtad, devad, regnum); + + mutex_lock(&bus->mdio_lock); + + ret = __phy_mmd_indirect(bus, prtad, devad, regnum); + if (ret) + goto out; + + ret = __mdiobus_read(bus, prtad, MII_MMD_DATA); + +out: + mutex_unlock(&bus->mdio_lock); + + return ret; +} + /* phy_c45_probe_present - checks to see if a MMD is present in the package * @bus: the target MII bus * @prtad: PHY package address on the MII bus @@ -713,7 +735,7 @@ static int phy_c45_probe_present(struct mii_bus *bus, int prtad, int devad) { int stat2; - stat2 = mdiobus_c45_read(bus, prtad, devad, MDIO_STAT2); + stat2 = mdiobus_probe_mmd_read(bus, prtad, devad, MDIO_STAT2); if (stat2 < 0) return stat2; @@ -736,12 +758,12 @@ static int get_phy_c45_devs_in_pkg(struct mii_bus *bus, int addr, int dev_addr, { int phy_reg; - phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS2); + phy_reg = mdiobus_probe_mmd_read(bus, addr, dev_addr, MDIO_DEVS2); if (phy_reg < 0) return -EIO; *devices_in_package = phy_reg << 16; - phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS1); + phy_reg = mdiobus_probe_mmd_read(bus, addr, dev_addr, MDIO_DEVS1); if (phy_reg < 0) return -EIO; *devices_in_package |= phy_reg; @@ -825,12 +847,12 @@ static int get_phy_c45_ids(struct mii_bus *bus, int addr, continue; } - phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID1); + phy_reg = mdiobus_probe_mmd_read(bus, addr, i, MII_PHYSID1); if (phy_reg < 0) return -EIO; c45_ids->device_ids[i] = phy_reg << 16; - phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID2); + phy_reg = mdiobus_probe_mmd_read(bus, addr, i, MII_PHYSID2); if (phy_reg < 0) return -EIO; c45_ids->device_ids[i] |= phy_reg; From patchwork Fri Jan 20 22:40:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 46656 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp463742wrn; Fri, 20 Jan 2023 14:44:10 -0800 (PST) X-Google-Smtp-Source: AMrXdXuIQtH+MlPPyJAoUXMPycKuTvCFS3iU1YZwfsz+FuOJNakYCgVQ/Z32888nJSj6yAXpG91v X-Received: by 2002:a17:906:40a:b0:86f:a21d:62b7 with SMTP id d10-20020a170906040a00b0086fa21d62b7mr16858719eja.9.1674254649890; Fri, 20 Jan 2023 14:44:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674254649; cv=none; d=google.com; s=arc-20160816; b=RiHPl14wOLkBV8wRm8JhjG6JRl8Y4yHR0gceLiWIAdOfZ5zBzjFpEjQqxVeI7PFJoR mUx+xkp+VPxPH+HLvbYvmH35bVsJS5bAtqvZrq8CoxHSaWSBVmfEAfaSuhX4dO0GPkJg O1Znt3JFUMgKwaQUidSiBW0I5Guno1PsRJ+RWXaLAxwcGTaRbGuTuz71ebfb7mYaxDje CfsDCHTh1BTAdU/MC/41MhQWENDachwFrVGl19NJD1xktd/Q9yWjDfOTh588jDr+Exb4 ns8luVEvJvR5PGA3D9ABRnk2tVXlu+kju3RzYEi64183UnvXuMllJDipz+bI5gV1WgzB xx0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wRykbIaW0o1idEZGzRxAVeXSO7s76nZHIN9EB7BE3zA=; b=YEHxBlVQ1wiCDE1mudHrw0LKiiF7sO+eDTVrHGNBB7P7oOkLN3LLIcbOw3V5dCMfG5 04RWyO0s+MQtXaSDyllJzs78tsgm1pOoj4j3IoNuovvES0InKp0sxqJ4a/gVZomrWPu+ OOt5Wos4aetyzmNh1hZZLwn4D59wLYimAhUcoUGplQrROThguuquOpeeU0vkf532dbqZ 3MU8ZZrTejVyjPQQPQy4toIPBA1CYf9IvfhHLgtvEYEBoOhxQqncxj1hbSYSvfSFucp9 sbc7JuxP9JEXUp6Yaw4nVxmg8wcOCfva5smLOhhxfl/WfMizoUDeoJBC3/RiVwwXqOOp 6l9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2022082101 header.b=18rshqzF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=walle.cc Received: from out1.vger.email (out1.vger.email. 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(unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 9095518D8; Fri, 20 Jan 2023 23:40:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1674254421; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wRykbIaW0o1idEZGzRxAVeXSO7s76nZHIN9EB7BE3zA=; b=18rshqzFTPUngdepaUWoX/X5JFl9Wx276PkINHX5MQo9ux3vg6OY0fk4FMhTwgkPFukirY EbtIkA1JOFUtEvnK7p/PpAjJgfVvPsxy8XiRULX2q5nhbtI0MKOpObUTKnKETytI3QEd4v kxk3MALOCXHtWBgb4Edghx9c+8HcvpVrbT20zE41R5XBP6/r9kNxRH20BBvJDEqLRgudbO CGJj5G8bdEfPB4FkHFINGq3JlvfnZQNGjaybYug4O173WIKXrDme+xJlCPq/7kn75g+dvf sSvQPc8v/vpCHowIXPeBkqfRM3LtS/o12jFybqpxUrSvxOgL3eBjYupcWVcjmw== From: Michael Walle To: Yisen Zhuang , Salil Mehta , "David S . Miller" , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Broadcom internal kernel review list , Andrew Lunn , Heiner Kallweit , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Xu Liang Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH net-next 3/5] net: phy: add support for C45-over-C22 transfers Date: Fri, 20 Jan 2023 23:40:09 +0100 Message-Id: <20230120224011.796097-4-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230120224011.796097-1-michael@walle.cc> References: <20230120224011.796097-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755583244109906535?= X-GMAIL-MSGID: =?utf-8?q?1755583244109906535?= If an MDIO bus is only capable of doing C22 transfers we can use indirect accesses to C45 registers over C22 registers. This was already the intention of the GPY215 driver. The author described their use case as follows: Our product supports both C22 and C45. In the real system, we found C22 was used by customers (with indirect access to C45 registers when necessary). In its probe function phy_get_c45_ids() is called but this will always do C45 accesses and thus will fail on a C22-only bus. With the current code we only have the is_c45 property which is used to indicate a C45 PHY but also used to choose the transfer mode. With C45-over-C22 we need to split these two properties. Drop the is_c45 and instead introduce two new properties, has_c45 and c45_over_c22. has_c45 is set to true if this is a C45 PHY and c45_over_c22 is true if we need to do indirect accesses using the C22 registers. c45_over_c22 will always be set by just looking at the bus capabilities. It will be set to true if a bus is C22-only, regardless if the PHY would support indirect access. Firstly, it is a reasonable assumption that C45 PHYs will support this access and secondly, there is really not much we can do otherwise. Signed-off-by: Michael Walle --- .../net/ethernet/hisilicon/hns/hns_ethtool.c | 4 +-- drivers/net/phy/bcm84881.c | 2 +- drivers/net/phy/marvell10g.c | 2 +- drivers/net/phy/mxl-gpy.c | 2 +- drivers/net/phy/phy-core.c | 4 +-- drivers/net/phy/phy.c | 6 ++--- drivers/net/phy/phy_device.c | 25 ++++++++++++++++--- drivers/net/phy/phylink.c | 8 +++--- include/linux/phy.h | 8 +++--- 9 files changed, 40 insertions(+), 21 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns/hns_ethtool.c b/drivers/net/ethernet/hisilicon/hns/hns_ethtool.c index b54f3706fb97..e34e1510e6a6 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_ethtool.c +++ b/drivers/net/ethernet/hisilicon/hns/hns_ethtool.c @@ -916,7 +916,7 @@ static void hns_get_strings(struct net_device *netdev, u32 stringset, u8 *data) hns_nic_test_strs[MAC_INTERNALLOOP_MAC]); ethtool_sprintf(&buff, hns_nic_test_strs[MAC_INTERNALLOOP_SERDES]); - if ((netdev->phydev) && (!netdev->phydev->is_c45)) + if (netdev->phydev && !netdev->phydev->has_c45) ethtool_sprintf(&buff, hns_nic_test_strs[MAC_INTERNALLOOP_PHY]); @@ -976,7 +976,7 @@ static int hns_get_sset_count(struct net_device *netdev, int stringset) if (priv->ae_handle->phy_if == PHY_INTERFACE_MODE_XGMII) cnt--; - if ((!netdev->phydev) || (netdev->phydev->is_c45)) + if (!netdev->phydev || netdev->phydev->has_c45) cnt--; return cnt; diff --git a/drivers/net/phy/bcm84881.c b/drivers/net/phy/bcm84881.c index 9717a1626f3f..d9131d5284c1 100644 --- a/drivers/net/phy/bcm84881.c +++ b/drivers/net/phy/bcm84881.c @@ -47,7 +47,7 @@ static int bcm84881_probe(struct phy_device *phydev) /* This driver requires PMAPMD and AN blocks */ const u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; - if (!phydev->is_c45 || + if (!phydev->has_c45 || (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) return -ENODEV; diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 383a9c9f36e5..27a52c11ad75 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -499,7 +499,7 @@ static int mv3310_probe(struct phy_device *phydev) u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; int ret; - if (!phydev->is_c45 || + if (!phydev->has_c45 || (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) return -ENODEV; diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c index e5972b4ef6e8..e86aea4381c2 100644 --- a/drivers/net/phy/mxl-gpy.c +++ b/drivers/net/phy/mxl-gpy.c @@ -281,7 +281,7 @@ static int gpy_probe(struct phy_device *phydev) int fw_version; int ret; - if (!phydev->is_c45) { + if (!phydev->has_c45) { ret = phy_get_c45_ids(phydev); if (ret < 0) return ret; diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index c9c92b95ace2..5e4a54f0a3dc 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -584,7 +584,7 @@ int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum) if (phydev->drv && phydev->drv->read_mmd) { val = phydev->drv->read_mmd(phydev, devad, regnum); - } else if (phydev->is_c45) { + } else if (phydev->has_c45 && !phydev->c45_over_c22) { val = __mdiobus_c45_read(phydev->mdio.bus, phydev->mdio.addr, devad, regnum); } else { @@ -640,7 +640,7 @@ int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) if (phydev->drv && phydev->drv->write_mmd) { ret = phydev->drv->write_mmd(phydev, devad, regnum, val); - } else if (phydev->is_c45) { + } else if (phydev->has_c45 && !phydev->c45_over_c22) { ret = __mdiobus_c45_write(phydev->mdio.bus, phydev->mdio.addr, devad, regnum, val); } else { diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 3378ca4f49b6..121aaae6b2f8 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -169,7 +169,7 @@ int phy_restart_aneg(struct phy_device *phydev) { int ret; - if (phydev->is_c45 && !(phydev->c45_ids.devices_in_package & BIT(0))) + if (phydev->has_c45 && !(phydev->c45_ids.devices_in_package & BIT(0))) ret = genphy_c45_restart_aneg(phydev); else ret = genphy_restart_aneg(phydev); @@ -190,7 +190,7 @@ int phy_aneg_done(struct phy_device *phydev) { if (phydev->drv && phydev->drv->aneg_done) return phydev->drv->aneg_done(phydev); - else if (phydev->is_c45) + else if (phydev->has_c45) return genphy_c45_aneg_done(phydev); else return genphy_aneg_done(phydev); @@ -883,7 +883,7 @@ int phy_config_aneg(struct phy_device *phydev) /* Clause 45 PHYs that don't implement Clause 22 registers are not * allowed to call genphy_config_aneg() */ - if (phydev->is_c45 && !(phydev->c45_ids.devices_in_package & BIT(0))) + if (phydev->has_c45 && !(phydev->c45_ids.devices_in_package & BIT(0))) return genphy_c45_config_aneg(phydev); return genphy_config_aneg(phydev); diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 9777a7fd180a..d5ea034cde98 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -516,7 +516,7 @@ static int phy_bus_match(struct device *dev, struct device_driver *drv) if (phydrv->match_phy_device) return phydrv->match_phy_device(phydev); - if (phydev->is_c45) { + if (phydev->has_c45) { for (i = 1; i < num_ids; i++) { if (phydev->c45_ids.device_ids[i] == 0xffffffff) continue; @@ -648,7 +648,24 @@ struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id, dev->autoneg = AUTONEG_ENABLE; dev->pma_extable = -ENODATA; - dev->is_c45 = is_c45; + + /* Depending on the bus capabilities, we have to use C45-over-C22 + * register access. We have the following cases: + * + * 1) bus can only do C45. + * 2) bus can only do C22. + * 3) bus can do C22 and C45. + * + * 1) and 3) are easy, because we can just use C45 transfers. For 2) we + * don't have any other choice but to use C22 transfers. Even if the + * PHY wouldn't support it we cannot do any better. + * + * Set this for C22 PHYs, too, because the PHY driver might promote it + * to C45. + */ + dev->c45_over_c22 = bus->read && !bus->read_c45; + + dev->has_c45 = is_c45; dev->phy_id = phy_id; if (c45_ids) dev->c45_ids = *c45_ids; @@ -1456,7 +1473,7 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, * exist, and we should use the genphy driver. */ if (!d->driver) { - if (phydev->is_c45) + if (phydev->has_c45) d->driver = &genphy_c45_driver.mdiodrv.driver; else d->driver = &genphy_driver.mdiodrv.driver; @@ -3115,7 +3132,7 @@ static int phy_probe(struct device *dev) linkmode_copy(phydev->supported, phydrv->features); else if (phydrv->get_features) err = phydrv->get_features(phydev); - else if (phydev->is_c45) + else if (phydev->has_c45) err = genphy_c45_pma_read_abilities(phydev); else err = genphy_read_abilities(phydev); diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 319790221d7f..63bec523a211 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1642,7 +1642,7 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, * against all interface modes, which may lead to more ethtool link * modes being advertised than are actually supported. */ - if (phy->is_c45 && config.rate_matching == RATE_MATCH_NONE && + if (phy->has_c45 && config.rate_matching == RATE_MATCH_NONE && interface != PHY_INTERFACE_MODE_RXAUI && interface != PHY_INTERFACE_MODE_XAUI && interface != PHY_INTERFACE_MODE_USXGMII) @@ -2584,7 +2584,7 @@ static int phylink_phy_read(struct phylink *pl, unsigned int phy_id, reg); } - if (phydev->is_c45) { + if (phydev->has_c45 && !phydev->c45_over_c22) { switch (reg) { case MII_BMCR: case MII_BMSR: @@ -2626,7 +2626,7 @@ static int phylink_phy_write(struct phylink *pl, unsigned int phy_id, reg, val); } - if (phydev->is_c45) { + if (phydev->has_c45 && !phydev->c45_over_c22) { switch (reg) { case MII_BMCR: case MII_BMSR: @@ -3101,7 +3101,7 @@ static void phylink_sfp_link_up(void *upstream) */ static bool phylink_phy_no_inband(struct phy_device *phy) { - return phy->is_c45 && + return phy->has_c45 && (phy->c45_ids.device_ids[1] & 0xfffffff0) == 0xae025150; } diff --git a/include/linux/phy.h b/include/linux/phy.h index f7a5e110f95c..4c02c468a24b 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -532,8 +532,9 @@ struct macsec_ops; * @devlink: Create a link between phy dev and mac dev, if the external phy * used by current mac interface is managed by another mac interface. * @phy_id: UID for this device found during discovery - * @c45_ids: 802.3-c45 Device Identifiers if is_c45. - * @is_c45: Set to true if this PHY uses clause 45 addressing. + * @c45_ids: 802.3-c45 Device Identifiers if has_c45. + * @has_c45: Set to true if this PHY has clause 45 address space. + * @c45_over_c22: Set to true if c45-over-c22 addressing is used. * @is_internal: Set to true if this PHY is internal to a MAC. * @is_pseudo_fixed_link: Set to true if this PHY is an Ethernet switch, etc. * @is_gigabit_capable: Set to true if PHY supports 1000Mbps @@ -625,7 +626,8 @@ struct phy_device { u32 phy_id; struct phy_c45_device_ids c45_ids; - unsigned is_c45:1; + unsigned has_c45:1; + unsigned c45_over_c22:1; unsigned is_internal:1; unsigned is_pseudo_fixed_link:1; unsigned is_gigabit_capable:1; From patchwork Fri Jan 20 22:40:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 46659 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp465000wrn; Fri, 20 Jan 2023 14:48:23 -0800 (PST) X-Google-Smtp-Source: AMrXdXsbBaRhTBvlp2ZQSyR+eCWGxnhMOjeh8kgSspcslCoID8OF8KOSdNHuBotyJ8dmEmzdUDYY X-Received: by 2002:a05:6a20:8f0d:b0:a3:6f97:e658 with SMTP id b13-20020a056a208f0d00b000a36f97e658mr23373953pzk.58.1674254903390; Fri, 20 Jan 2023 14:48:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674254903; cv=none; d=google.com; s=arc-20160816; b=jzo6FGbeAt6+N7ce5RZpNyzowaik7MJx9R5zshoc5p0U6Jev81blq8Yq2kPqfJSzbo 2+Pc7Ys76UqjrtEG/h7/pF1GyflKA3ScBMIP3w/zXP8MS0BaJ+17z6uzQzibuJQwUhZw pAhlbDwIkQvR/T3qWUBcSYAdCrDh2agDVO+YVtH+qobLWNUb1lP+lbgm7dCqTGUh3R5K 8giN0OXUsO/S0yTJWcT2iMkv/EuHQRKev2hnqfARNnqOREr7IeAc9MBI5oiniD2a2sQ0 PX0iV6KQ1u9eKGTspCYofxd/AumXPuC8C0ZlsuTJOHba8kDoCjAc7mrAL3JRGAkeUZJG XNMA== ARC-Message-Signature: i=1; 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Miller" , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Broadcom internal kernel review list , Andrew Lunn , Heiner Kallweit , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Xu Liang Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH net-next 4/5] phy: net: introduce phy_promote_to_c45() Date: Fri, 20 Jan 2023 23:40:10 +0100 Message-Id: <20230120224011.796097-5-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230120224011.796097-1-michael@walle.cc> References: <20230120224011.796097-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755583509553456335?= X-GMAIL-MSGID: =?utf-8?q?1755583509553456335?= If not explitly asked to be probed as a C45 PHY, on a bus which is capable of doing both C22 and C45 transfers, C45 PHYs are first tried to be probed as C22 PHYs. To be able to promote the PHY to be a C45 one, the driver can call phy_promote_to_c45() in its probe function. This was already done in the mxl-gpy driver by the following snippet: if (!phydev->has_c45) { ret = phy_get_c45_ids(phydev); if (ret < 0) return ret; } Move that code into the core by creating a new function phy_promote_to_c45(). If a PHY is promoted, C45-over-C22 access is used, regardless if the bus supports C45 or not. That is because there might be C22 PHYs on the bus which gets confused by C45 accesses. Signed-off-by: Michael Walle --- drivers/net/phy/mxl-gpy.c | 9 ++++----- drivers/net/phy/phy_device.c | 23 +++++++++++++++++++---- include/linux/phy.h | 2 +- 3 files changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c index e86aea4381c2..4dc1093dbdc1 100644 --- a/drivers/net/phy/mxl-gpy.c +++ b/drivers/net/phy/mxl-gpy.c @@ -281,11 +281,10 @@ static int gpy_probe(struct phy_device *phydev) int fw_version; int ret; - if (!phydev->has_c45) { - ret = phy_get_c45_ids(phydev); - if (ret < 0) - return ret; - } + /* This might have been probed as a C22 PHY, but this is a C45 PHY */ + ret = phy_promote_to_c45(phydev); + if (ret) + return ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index d5ea034cde98..ae24b62abfac 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1058,18 +1058,33 @@ void phy_device_remove(struct phy_device *phydev) EXPORT_SYMBOL(phy_device_remove); /** - * phy_get_c45_ids - Read 802.3-c45 IDs for phy device. - * @phydev: phy_device structure to read 802.3-c45 IDs + * phy_promote_to_c45 - Promote to a C45 PHY + * @phydev: phy_device structure + * + * If a PHY supports both C22 and C45 and it isn't specifically asked to probe + * as a C45 PHY it might be probed as a C22 PHY. The driver can call this + * function to promote a PHY from C22 to C45. + * + * Can also be called if a PHY is already a C45 one. In that case it does + * nothing. + * + * Promoted PHYs will always use C45-over-C22 accesses to prevent any C45 + * transactions on the bus, which might confuse C22-only PHYs. * * Returns zero on success, %-EIO on bus access error, or %-ENODEV if * the "devices in package" is invalid. */ -int phy_get_c45_ids(struct phy_device *phydev) +int phy_promote_to_c45(struct phy_device *phydev) { + if (phydev->has_c45) + return 0; + + phydev->has_c45 = true; + phydev->c45_over_c22 = true; return get_phy_c45_ids(phydev->mdio.bus, phydev->mdio.addr, &phydev->c45_ids); } -EXPORT_SYMBOL(phy_get_c45_ids); +EXPORT_SYMBOL(phy_promote_to_c45); /** * phy_find_first - finds the first PHY device on the bus diff --git a/include/linux/phy.h b/include/linux/phy.h index 4c02c468a24b..9473e2ed8496 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1588,7 +1588,7 @@ static inline int phy_device_register(struct phy_device *phy) static inline void phy_device_free(struct phy_device *phydev) { } #endif /* CONFIG_PHYLIB */ void phy_device_remove(struct phy_device *phydev); -int phy_get_c45_ids(struct phy_device *phydev); +int phy_promote_to_c45(struct phy_device *phydev); int phy_init_hw(struct phy_device *phydev); int phy_suspend(struct phy_device *phydev); int phy_resume(struct phy_device *phydev); From patchwork Fri Jan 20 22:40:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 46657 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp463813wrn; Fri, 20 Jan 2023 14:44:23 -0800 (PST) X-Google-Smtp-Source: AMrXdXsFTtGQo/H1qy/Yc2jiYrXiFm/bttBkQqby4dWsAFW+NokPZ8Q63hGKVaKg8J4DkUMKpjj3 X-Received: by 2002:a17:906:7e10:b0:846:cdd9:d23 with SMTP id e16-20020a1709067e1000b00846cdd90d23mr17862741ejr.19.1674254663091; Fri, 20 Jan 2023 14:44:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674254663; cv=none; d=google.com; s=arc-20160816; b=JGSgk4l8i62EAsVEYk9g44LD2cz4BBKMTf2yQDFZ4VCv4/0gBfziV+G4+FZGfMcs44 LR9lgUVhY6AkA3wGAb2sbFR3vCgPzaODuwgF/n5CPjzpd79/D4LvsclzBb9d74c54YkZ WSM4LGGX5ANNMlAwqhnOqyfdAAk4rzbTqRBv8WociSFx6nzOxbAcYDhdKynfomcSSVMJ MH04u9wi/jZUlrTDLTLkzQP1alyMq39vrD+L9Ups2s7w10LlgvzFmcT8SseDvf8Ix3QK H5b8AMSNxIQ9K39oj1vV/iO77mGdkedqWXE72Y2p08OqTBduXo0YSmRz6H/1h/FK2Sl0 4IbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DaItXxFJlXbhnny9pEslryZf5rRWhsYt/rO9M38cY10=; b=qMS+CyeGaShXUHi9R5SOg+C8hilNgv84gmqYBAXuRl1hQpDXmLWRhuilbCOPTwnur8 iy5a3R22EEkyCuSRteIB4+3eSjQGDsfpd/MheSxes6+4rOAkn9F9P0vix9/B9JFXLJSX /UHKelU3cRjvaZxDMK5TCFphdo6IauavMUa8egwM7FJzealsH2AfR4l+82BGxwY4rPDg YJpo8Jm9sDc43aSRcDawdn/WAuQfbO051UZgtvvU6368IKac0lWkbLbxNF26XkfVShue 0mMtTrU6eM3DzGevYGCC1mpi7rOQ6nHgEGCyc4MnG4dL4bcVBYNw1TMQaOLWorXRjsMT SC5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@walle.cc header.s=mail2022082101 header.b=oziOGAoA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=walle.cc Received: from out1.vger.email (out1.vger.email. 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(unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id F27E61A07; Fri, 20 Jan 2023 23:40:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1674254423; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DaItXxFJlXbhnny9pEslryZf5rRWhsYt/rO9M38cY10=; b=oziOGAoAtdSNi/JUecBvPvqA2+q9KuVYTq8krY54od76W6nkT7pJpz5iBaNSk8zGbKHKKd 01Zg6OgdKHxXC8+I2kUG9zuLZMOFJ1wCUxXoVkYsbltboDBF4jcfabCG07Ld0aSM8Thv9M CyRuMmsnu11fWPDX5T4v+1mP88wfnQTMH4X+NexNUm7fL3UXEZGAxptJwIMj8f1E+JeWgl QG0/S1bplKHe8s/9LU9ZlXN8/j77fP6WcnqFobtIpsi0ClNgpQOh8UpV2O9a5njKIKTPul eanYSQgWPxQTKXkFOs0Nqz87pJlIKDYgblbocTyjA9NoH8udIvY+g82lzg1MZw== From: Michael Walle To: Yisen Zhuang , Salil Mehta , "David S . Miller" , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Broadcom internal kernel review list , Andrew Lunn , Heiner Kallweit , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Xu Liang Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH net-next 5/5] net: phy: mxl-gpy: remove unneeded ops Date: Fri, 20 Jan 2023 23:40:11 +0100 Message-Id: <20230120224011.796097-6-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230120224011.796097-1-michael@walle.cc> References: <20230120224011.796097-1-michael@walle.cc> MIME-Version: 1.0 X-Spam: Yes X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755583257285559291?= X-GMAIL-MSGID: =?utf-8?q?1755583257285559291?= Now that we have proper c45-over-c22 support and the PHY driver promote the PHY to a C45 device, we can drop the ops because the core will already call them. Signed-off-by: Michael Walle --- drivers/net/phy/mxl-gpy.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/drivers/net/phy/mxl-gpy.c b/drivers/net/phy/mxl-gpy.c index 4dc1093dbdc1..043c084a8a16 100644 --- a/drivers/net/phy/mxl-gpy.c +++ b/drivers/net/phy/mxl-gpy.c @@ -799,13 +799,11 @@ static struct phy_driver gpy_drivers[] = { { PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), .name = "Maxlinear Ethernet GPY2xx", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -817,13 +815,11 @@ static struct phy_driver gpy_drivers[] = { .phy_id = PHY_ID_GPY115B, .phy_id_mask = PHY_ID_GPYx15B_MASK, .name = "Maxlinear Ethernet GPY115B", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -834,13 +830,11 @@ static struct phy_driver gpy_drivers[] = { { PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), .name = "Maxlinear Ethernet GPY115C", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -852,13 +846,11 @@ static struct phy_driver gpy_drivers[] = { .phy_id = PHY_ID_GPY211B, .phy_id_mask = PHY_ID_GPY21xB_MASK, .name = "Maxlinear Ethernet GPY211B", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -869,13 +861,11 @@ static struct phy_driver gpy_drivers[] = { { PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), .name = "Maxlinear Ethernet GPY211C", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -887,13 +877,11 @@ static struct phy_driver gpy_drivers[] = { .phy_id = PHY_ID_GPY212B, .phy_id_mask = PHY_ID_GPY21xB_MASK, .name = "Maxlinear Ethernet GPY212B", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -904,13 +892,11 @@ static struct phy_driver gpy_drivers[] = { { PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), .name = "Maxlinear Ethernet GPY212C", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -922,13 +908,11 @@ static struct phy_driver gpy_drivers[] = { .phy_id = PHY_ID_GPY215B, .phy_id_mask = PHY_ID_GPYx15B_MASK, .name = "Maxlinear Ethernet GPY215B", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -939,13 +923,11 @@ static struct phy_driver gpy_drivers[] = { { PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), .name = "Maxlinear Ethernet GPY215C", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -956,13 +938,11 @@ static struct phy_driver gpy_drivers[] = { { PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), .name = "Maxlinear Ethernet GPY241B", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -973,13 +953,11 @@ static struct phy_driver gpy_drivers[] = { { PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM), .name = "Maxlinear Ethernet GPY241BM", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt, @@ -990,13 +968,11 @@ static struct phy_driver gpy_drivers[] = { { PHY_ID_MATCH_MODEL(PHY_ID_GPY245B), .name = "Maxlinear Ethernet GPY245B", - .get_features = genphy_c45_pma_read_abilities, .config_init = gpy_config_init, .probe = gpy_probe, .suspend = genphy_suspend, .resume = genphy_resume, .config_aneg = gpy_config_aneg, - .aneg_done = genphy_c45_aneg_done, .read_status = gpy_read_status, .config_intr = gpy_config_intr, .handle_interrupt = gpy_handle_interrupt,