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Signed-off-by: Abel Vesa --- The v1 was here: https://lore.kernel.org/all/20221116123505.2760397-1-abel.vesa@linaro.org/ Changes since v1: * Switched to single compatible for both PCIes (qcom,pcie-sm8550) * dropped enable-gpios property * dropped interconnects related properties, the power-domains properties and resets related properties the sm8550 specific allOf:if:then * dropped pipe_mux, phy_pipe and ref clocks from the sm8550 specific allOf:if:then clock-names array and decreased the minItems and maxItems for clocks property accordingly .../devicetree/bindings/pci/qcom,pcie.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a5859bb3dc28..78e8babd11d9 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -34,6 +34,7 @@ properties: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550 - qcom,pcie-ipq6018 reg: @@ -197,6 +198,7 @@ allOf: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550 then: properties: reg: @@ -611,6 +613,40 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8550 + then: + properties: + clocks: + minItems: 8 + maxItems: 9 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre # Aggre NoC PCIe0 AXI clock + - const: cnoc_pcie_sf_axi # Config NoC PCIe1 AXI clock + iommus: + maxItems: 1 + iommu-map: + maxItems: 2 + resets: + minItems: 1 + maxItems: 2 + reset-names: + items: + - const: pci # PCIe core reset + - const: pcie_1_link_down_reset # PCIe link down reset + - if: properties: compatible: @@ -694,6 +730,7 @@ allOf: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550 then: oneOf: - properties: From patchwork Wed Jan 18 11:17:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 45199 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2300413wrn; Wed, 18 Jan 2023 04:10:17 -0800 (PST) X-Google-Smtp-Source: AMrXdXvsmexjPL3SOnZoLKRx45J6+MqytMoX7vdd7Ee3PVUuxMiT/Eo6GYG20GO1F8SHBJ3Zm7py X-Received: by 2002:a17:90b:513:b0:225:ec6a:2d02 with SMTP id r19-20020a17090b051300b00225ec6a2d02mr7307909pjz.0.1674043817328; Wed, 18 Jan 2023 04:10:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674043817; cv=none; d=google.com; s=arc-20160816; b=q4qATbh5yBqwl7eonBH0GBQc83rYS7RMqRS5L2QAi5j/bUqsoLdPqJmUgADlNDPZ53 UWNm3X31eJyQpf+C/hlyCdEpomw2soFfFrMhRe0R2j6j0mwhyYq0glW7T0KvvzzYbpK9 4wlHn6j03ZZ2pfMvbhXJa0dM05tr+7wRCanRlyecZkygrFrBd4iP2BpMWJ4XE3hElbFC ICGAfdzkpsxl/Ek4fAHLAvAMC/eVNiJcWrVGtlvF1vmI54JqAm5bjpmwoObbQv2BNmg2 Cv+oA9sGDf7MXlohUPij9yf/oi2AW6SbgNQ9zW1/c6r28TEf7bL6rF71h0G9oLDZ6bfo zmgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ax0S1Mi21dQMczSaAgM0TaYM+PtE4awHpXsqNp1yeTs=; b=m2PMRvibdM589zrR7Q6LDf0YUKo/tmxeqSev2Cty3C1CezIUzES5VWKf3fxuI+22Hf UydfHwtoQtKPTdYh0bQ5YvZNm+PC7gchI/XlpIuhFchuP46l78cTI3BqBbn6DMv+ZpXI XyYv1Npz0fJU0Plkz8wJcnLsasb844lre5F5uDKlsDV+dXllITcfumIE5bNaqPjHz62S DaQ/dy1zQeDMIYcz9KD9Z5Bq3VaDgSFyHY6GoDnJwuahAUnF+yBQOovw3wFiOoLKD0cY bS0e2X5c4xIX/9cyLz09OXs9vlSOq32kQOWXNrmkd2OUHVJZHFjFUThLuch/wlnchdSv eyLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LVO8wtaT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Also add the cnoc_pcie_sf_axi clock needed by the SM8550. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- The v1 was here: https://lore.kernel.org/all/20221116123505.2760397-2-abel.vesa@linaro.org/ Changes since v1: * changed the subject line prefix for the patch to match the history, like Bjorn Helgaas suggested. * added Konrad's R-b tag drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 77e5dc7b88ad..85988b3fd4f6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[13]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "cnoc_pcie_sf_axi"; num_opt_clks = idx - num_clks; res->num_clks = idx; @@ -1828,6 +1829,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, { } };