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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id f26-20020aa7d85a000000b0048b0b329f9fsi4923568eds.416.2023.01.17.18.45.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 18:45:04 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 55CBF385B51A for ; Wed, 18 Jan 2023 02:44:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by sourceware.org (Postfix) with ESMTPS id 799C93858D28 for ; Wed, 18 Jan 2023 02:44:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 799C93858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp73t1674009859td4d870b Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 18 Jan 2023 10:44:18 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: /5D9664O2EXS7kDnYJaQ2kUYhYAStTmvF5Z102bJ+G2R2Ng8WEIVgkVOO6vF4 HXSrcsHd6Yvc1Wwxb6XyeRNKQXYJXf524IIvXIg8LuG6AQdLXnxBu5a47wabV/p2WolyOgH 80ziQ4NS5CODqKH++8yVnROPwk+it7WhOI/XPR8J/UPZdMGhtEiAJxadoMB31AKlQCoL18o LMlDL3vG4xibY/lThW2iA/NIR3EH68o0WoyvT6/6PDGeUe6dV1pNNSAUniVe6nSDKgmvmmq gneA2XVEjXWHdwSBO/Q9z7FEV5Shtyjbbeos6wQWUQpRjpLFmStQI7efHkojhNeb5tpusSd Hu5FDiKmb3ZCMJ7/HG1n9vby4P93nolaH0NYPEkNC+Xrfv044ShhNeU6yt37nc9Sz3G9OIe X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Fix incorrect attributes of vsetvl instructions pattern Date: Wed, 18 Jan 2023 10:44:15 +0800 Message-Id: <20230118024415.64340-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755326609904912057?= X-GMAIL-MSGID: =?utf-8?q?1755326609904912057?= From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/vector.md: Fix incorrect attributes. --- gcc/config/riscv/vector.md | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 4e93b7fead5..37cf4d6bcbf 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -95,13 +95,7 @@ (const_int 32) (eq_attr "mode" "VNx1DI,VNx2DI,VNx4DI,VNx8DI,\ VNx1DF,VNx2DF,VNx4DF,VNx8DF") - (const_int 64) - - (eq_attr "type" "vsetvl") - (if_then_else (eq_attr "INSN_CODE (curr_insn) == CODE_FOR_vsetvldi - || INSN_CODE (curr_insn) == CODE_FOR_vsetvlsi") - (symbol_ref "INTVAL (operands[2])") - (const_int INVALID_ATTRIBUTE))] + (const_int 64)] (const_int INVALID_ATTRIBUTE))) ;; Ditto to LMUL. @@ -149,12 +143,7 @@ (eq_attr "mode" "VNx4DI,VNx4DF") (symbol_ref "riscv_vector::get_vlmul(E_VNx4DImode)") (eq_attr "mode" "VNx8DI,VNx8DF") - (symbol_ref "riscv_vector::get_vlmul(E_VNx8DImode)") - (eq_attr "type" "vsetvl") - (if_then_else (eq_attr "INSN_CODE (curr_insn) == CODE_FOR_vsetvldi - || INSN_CODE (curr_insn) == CODE_FOR_vsetvlsi") - (symbol_ref "INTVAL (operands[3])") - (const_int INVALID_ATTRIBUTE))] + (symbol_ref "riscv_vector::get_vlmul(E_VNx8DImode)")] (const_int INVALID_ATTRIBUTE))) ;; It is valid for instruction that require sew/lmul ratio. @@ -531,7 +520,11 @@ "TARGET_VECTOR" "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5" [(set_attr "type" "vsetvl") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "sew") (symbol_ref "INTVAL (operands[2])")) + (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])")) + (set (attr "ta") (symbol_ref "INTVAL (operands[4])")) + (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))]) ;; vsetvl zero,zero,vtype instruction. ;; This pattern has no side effects and does not set X0 register. @@ -563,7 +556,11 @@ "TARGET_VECTOR" "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4" [(set_attr "type" "vsetvl") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "sew") (symbol_ref "INTVAL (operands[1])")) + (set (attr "vlmul") (symbol_ref "INTVAL (operands[2])")) + (set (attr "ta") (symbol_ref "INTVAL (operands[3])")) + (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))]) ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects. ;; Since we have many optmization passes from "expand" to "reload_completed",