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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id k18-20020adfb352000000b00241fab5a296sm27785372wrd.40.2023.01.16.12.47.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 12:47:58 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v7 1/7] dt-bindings: clock: Convert qcom,krait-cc to yaml Date: Mon, 16 Jan 2023 21:47:45 +0100 Message-Id: <20230116204751.23045-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230116204751.23045-1-ansuelsmth@gmail.com> References: <20230116204751.23045-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755213647549456519?= X-GMAIL-MSGID: =?utf-8?q?1755213647549456519?= Convert qcom,krait-cc to yaml Documentation. Signed-off-by: Christian Marangi Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../bindings/clock/qcom,krait-cc.txt | 34 ----------- .../bindings/clock/qcom,krait-cc.yaml | 59 +++++++++++++++++++ 2 files changed, 59 insertions(+), 34 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt deleted file mode 100644 index 030ba60dab08..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +++ /dev/null @@ -1,34 +0,0 @@ -Krait Clock Controller - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,krait-cc-v1" - "qcom,krait-cc-v2" - -- #clock-cells: - Usage: required - Value type: - Definition: must be 1 - -- clocks: - Usage: required - Value type: - Definition: reference to the clock parents of hfpll, secondary muxes. - -- clock-names: - Usage: required - Value type: - Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb". - -Example: - - kraitcc: clock-controller { - compatible = "qcom,krait-cc-v1"; - clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, ; - clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb"; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml new file mode 100644 index 000000000000..8caa5a677394 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait Clock Controller + +maintainers: + - Christian Marangi + +description: | + Qualcomm Krait Clock Controller used to correctly scale the CPU and the L2 + rates. + +properties: + compatible: + enum: + - qcom,krait-cc-v1 + - qcom,krait-cc-v2 + + clocks: + items: + - description: phandle to hfpll for CPU0 mux + - description: phandle to hfpll for CPU1 mux + - description: phandle to CPU0 aux clock + - description: phandle to CPU1 aux clock + - description: phandle to QSB fixed clk + + clock-names: + items: + - const: hfpll0 + - const: hfpll1 + - const: acpu0_aux + - const: acpu1_aux + - const: qsb + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&hfpll0>, <&hfpll1>, + <&acpu0_aux>, <&acpu1_aux>, <&qsb>; + clock-names = "hfpll0", "hfpll1", + "acpu0_aux", "acpu1_aux", "qsb"; + #clock-cells = <1>; + }; +... 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id k18-20020adfb352000000b00241fab5a296sm27785372wrd.40.2023.01.16.12.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 12:47:59 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v7 2/7] dt-bindings: arm: msm: Convert and split kpss-acc driver Documentation to yaml Date: Mon, 16 Jan 2023 21:47:46 +0100 Message-Id: <20230116204751.23045-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230116204751.23045-1-ansuelsmth@gmail.com> References: <20230116204751.23045-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755213662913368346?= X-GMAIL-MSGID: =?utf-8?q?1755213662913368346?= Convert kpss-acc driver Documentation to yaml. The original Documentation was wrong all along. Fix it while we are converting it. The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, split the Documentation to 2 different schema, v1 as clock-controller and v2 for power-manager as per msm-3.10 specification, the exposed regs handle power manager. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring --- .../bindings/arm/msm/qcom,kpss-acc.txt | 49 ------------- .../bindings/clock/qcom,kpss-acc-v1.yaml | 72 +++++++++++++++++++ .../bindings/power/qcom,kpss-acc-v2.yaml | 42 +++++++++++ 3 files changed, 114 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml create mode 100644 Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt deleted file mode 100644 index 7f696362a4a1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +++ /dev/null @@ -1,49 +0,0 @@ -Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) - -The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. -There is one ACC register region per CPU within the KPSS remapped region as -well as an alias register region that remaps accesses to the ACC associated -with the CPU accessing the region. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of: - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: optional - Value type: - Definition: Name of the output clock. Typically acpuX_aux where X is a - CPU number starting at 0. - -Example: - - clock-controller@2088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0x02088000 0x1000>, - <0x02008000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu0_aux"; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml b/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml new file mode 100644 index 000000000000..a466e4e8aacd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1 + +maintainers: + - Christian Marangi + +description: + The KPSS ACC provides clock, power domain, and reset control to a Krait CPU. + There is one ACC register region per CPU within the KPSS remapped region as + well as an alias register region that remaps accesses to the ACC associated + with the CPU accessing the region. ACC v1 is currently used as a + clock-controller for enabling the cpu and hanling the aux clocks. + +properties: + compatible: + const: qcom,kpss-acc-v1 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register region + minItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pll8_vote + - const: pxo + + clock-output-names: + description: Name of the aux clock. Krait can have at most 4 cpu. + enum: + - acpu0_aux + - acpu1_aux + - acpu2_aux + - acpu3_aux + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; + }; + +... diff --git a/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml new file mode 100644 index 000000000000..202a5d51ee88 --- /dev/null +++ b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2 + +maintainers: + - Christian Marangi + +description: + The KPSS ACC provides clock, power manager, and reset control to a Krait CPU. + There is one ACC register region per CPU within the KPSS remapped region as + well as an alias register region that remaps accesses to the ACC associated + with the CPU accessing the region. ACC v2 is currently used as a + power-manager for enabling the cpu. + +properties: + compatible: + const: qcom,kpss-acc-v2 + + reg: + items: + - description: Base address and size of the register region + - description: Optional base address and size of the alias register region + minItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + power-manager@f9088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0xf9088000 0x1000>, + <0xf9008000 0x1000>; + }; +... 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id k18-20020adfb352000000b00241fab5a296sm27785372wrd.40.2023.01.16.12.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 12:48:00 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring Subject: [PATCH v7 3/7] dt-bindings: arm: msm: Rework kpss-gcc driver Documentation to yaml Date: Mon, 16 Jan 2023 21:47:47 +0100 Message-Id: <20230116204751.23045-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230116204751.23045-1-ansuelsmth@gmail.com> References: <20230116204751.23045-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755213633190648616?= X-GMAIL-MSGID: =?utf-8?q?1755213633190648616?= Rework kpss-gcc driver Documentation to yaml Documentation and move it to clock as it's a clock-controller. The current kpss-gcc Documentation have major problems and can't be converted directly. Introduce various changes to the original Documentation. Add #clock-cells additional binding as this clock outputs a static clk named acpu_l2_aux with supported compatible. Only some compatible require and outputs a clock, for the others, set only the reg as a required binding to correctly export the kpss-gcc registers. As the reg is shared also add the required syscon compatible. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring --- .../bindings/arm/msm/qcom,kpss-gcc.txt | 44 ---------- .../bindings/clock/qcom,kpss-gcc.yaml | 88 +++++++++++++++++++ 2 files changed, 88 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt deleted file mode 100644 index e628758950e1..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +++ /dev/null @@ -1,44 +0,0 @@ -Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: should be one of the following. The generic compatible - "qcom,kpss-gcc" should also be included. - "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" - "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" - -- reg: - Usage: required - Value type: - Definition: base address and size of the register region - -- clocks: - Usage: required - Value type: - Definition: reference to the pll parents. - -- clock-names: - Usage: required - Value type: - Definition: must be "pll8_vote", "pxo". - -- clock-output-names: - Usage: required - Value type: - Definition: Name of the output clock. Typically acpu_l2_aux indicating - an L2 cache auxiliary clock. - -Example: - - l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; - reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; - clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml new file mode 100644 index 000000000000..88b7672123a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +maintainers: + - Christian Marangi + +description: + Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used + to control L2 mux (in the current implementation) and provide access + to the kpss-gcc registers. + +properties: + compatible: + items: + - enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 + - qcom,kpss-gcc-msm8660 + - qcom,kpss-gcc-mdm9615 + - const: qcom,kpss-gcc + - const: syscon + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: pll8_vote + - const: pxo + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - qcom,kpss-gcc-ipq8064 + - qcom,kpss-gcc-apq8064 + - qcom,kpss-gcc-msm8974 + - qcom,kpss-gcc-msm8960 +then: + required: + - clocks + - clock-names + - '#clock-cells' +else: + properties: + clock: false + clock-names: false + '#clock-cells': false + +additionalProperties: false + +examples: + - | + #include + + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; + }; + + - | + clock-controller@2011000 { + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; + reg = <0x02011000 0x1000>; + }; +... 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id k18-20020adfb352000000b00241fab5a296sm27785372wrd.40.2023.01.16.12.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 12:48:01 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v7 4/7] ARM: dts: qcom: add per SoC compatible for qcom,kpss-gcc nodes Date: Mon, 16 Jan 2023 21:47:48 +0100 Message-Id: <20230116204751.23045-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230116204751.23045-1-ansuelsmth@gmail.com> References: <20230116204751.23045-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755213734708339004?= X-GMAIL-MSGID: =?utf-8?q?1755213734708339004?= Add per Soc compatible for qcom,kpss-gcc nodes. While currently not used by the kpss driver they can serve further customization and they are required to be defined per Documentation schema. Signed-off-by: Christian Marangi --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-mdm9615.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8660.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8960.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 1f3e0aa9ab0c..7065f6e88dcf 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -880,7 +880,7 @@ mmcc: clock-controller@4000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 7e784b0995da..bd0728c57eab 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -570,7 +570,7 @@ IRQ_TYPE_EDGE_RISING)>, }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index b0fe1d95d88f..61dfec3b9037 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -116,7 +116,7 @@ lcc: clock-controller@28000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 86f76d0feff4..f601b40ebcf4 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -473,7 +473,7 @@ pm8058_led133: led@133 { }; l2cc: clock-controller@2082000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; reg = <0x02082000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 7debf9db7cb1..2dd90e57929a 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -183,7 +183,7 @@ clock-controller@4000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; }; From patchwork Mon Jan 16 20:47:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 44315 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1395302wrn; Mon, 16 Jan 2023 12:53:00 -0800 (PST) X-Google-Smtp-Source: AMrXdXua8sbU8KRUGJwmPdL3m5G2k3PrTMJ0mOIQxCBmSnqj6vC2LVZtdp6SUZ5ULtWUYr90hAdK X-Received: by 2002:a05:6a20:d68b:b0:b8:5134:a36b with SMTP id it11-20020a056a20d68b00b000b85134a36bmr270792pzb.21.1673902379784; Mon, 16 Jan 2023 12:52:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673902379; cv=none; d=google.com; s=arc-20160816; b=Lz1jVOOO6/nw+9ICKUOUdr3k8pNGy7G/HAdiGr6DFifQWhAuE8cz8QZ3SHBJqILHIo 5GTY1DHyb0c+wqOqTRL8kic3vYClEP1cnq73Rz837LbpAVjJaDg6RpV9TZ+JSCA2C7ak JX4fhpDcA8iRC85rYWRsiIkP94Te9PfOT12bVsnYmVY9Lf3JeV8lkn/9EhXwoGwhkLCU n8JR0hkPHh7eH2mP5I/XjJ5vQNwlWHM7ipB3k+mYjzirv3gG4MLS8RNiJGK6iDPXib6c aMWFU8iUh39nr+hIRWc/220lWRtdNRloHNcaU5CiPBj40EzAObDwMYAh5BtVl2Az4JfL 9NyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GkjLqcCTee4LPDv2iPQ2BaMG6gf64UUuhQ8hfxO58R8=; b=uXmLhvpV4FV33m806TUw8Ev1j77iAjZOgpIziYogfJuN/+4SC1YtxmIl/g7ljQix/q oip/BSzBv/GVYsNm61sGv6RFIZ/B5O3F4dyKH3sYv9c1VmO9q8oh2EVJBDQblI5mspTQ fEjbOwGZFrPmlBAk0jHJA2infBDsGhHlxBRgLBwGBqwENfay3/pmH4DK6sJIjCAs0Fv1 /aOwNHYrC6Jtso2jxCPxu5dgc1bqKeGeq5CqQ6eJIUUtfHgrD/fjTrKu0cBZRs/blJfk CW4gf5eLK9kJtynpbYKYAav/1FiW+l/KmnNpXS47xSIaWW9RDA1IjnZC77Kvju6OACLz /nvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Oz9oVCU0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id k18-20020adfb352000000b00241fab5a296sm27785372wrd.40.2023.01.16.12.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 12:48:02 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v7 5/7] ARM: dts: qcom: add and fix clock configuration for kpss-gcc nodes Date: Mon, 16 Jan 2023 21:47:49 +0100 Message-Id: <20230116204751.23045-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230116204751.23045-1-ansuelsmth@gmail.com> References: <20230116204751.23045-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755213861912506702?= X-GMAIL-MSGID: =?utf-8?q?1755213861912506702?= Add missing clock configuration by adding clocks, clock-names and #clock-cells bindings for each kpss-acc-v1 clock-controller node for apq8064 and msm8960 to reflect Documentation schema. Add missing #clock-cells binding and remove useless clock-output-names for ipq806x dtsi. Signed-off-by: Christian Marangi Reviewed-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8960.dtsi | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 7065f6e88dcf..1e68b42acb91 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -882,6 +882,9 @@ mmcc: clock-controller@4000000 { l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; rpm: rpm@108000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index bd0728c57eab..de87fcaaa836 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -574,7 +574,7 @@ l2cc: clock-controller@2011000 { reg = <0x02011000 0x1000>; clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; }; acc0: clock-controller@2088000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 2dd90e57929a..3bd07cac315b 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -185,6 +185,9 @@ clock-controller@4000000 { l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; rpm: rpm@108000 { From patchwork Mon Jan 16 20:47:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 44316 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1395447wrn; Mon, 16 Jan 2023 12:53:27 -0800 (PST) X-Google-Smtp-Source: AMrXdXvbPFw7h6GxrcbUtBfcfp9bI5A5jSQfcO8TJePdVB4bOeTyWzfNN+PgUODYVkDZtVTQWb1u X-Received: by 2002:a17:902:7e47:b0:193:3215:9621 with SMTP id a7-20020a1709027e4700b0019332159621mr20799062pln.33.1673902406868; Mon, 16 Jan 2023 12:53:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673902406; cv=none; d=google.com; s=arc-20160816; b=bkEejeKTeGChv5eT86OPSuOpPm4rG7EO8y7noUk+OsXDvDoWOHD9yQYrVIFVyWJ9+G L6/wsFGoCJHwZo6JoDZeBG8QmFcwq5Dh1SrBaWv1q/L+9fL5/wSSHrILtPs1SgwdGNQD zYYhKpHEmOxKUhpFlYMhByrXARkI/bp2/NY1hftZ5dr1DhUjz1gORF5bCrywfg6zTk6P 5mAM5djLb2TYV4Pw4X3vt+d/yhwbzmRPuSl4c3qLZ9jhp7e7JY7rBi5Fcr5+SBj4K6+Z OgNpIf5nuFporUWMZMFpL6jG33EyPbIFaK4X2DRqsP/njVPsOtssMp3Ai0Jtzdqb3pcH 9NsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XTQcxRSsDdNAmsWj8v2rraUSWcRmffK40pcDPX9MDPE=; b=RA6339vW0bIvYATZyM011NamXWEnzCe5MIWsoIX9VN9xXRQ1tijghxUoDG9+83Mdnt 6JygqvKv2cHcM5D94CXVcVCkt74EKioS++YTc7KOmplLIWie2hkVkIV4BzXVezPXwCki eydbziUmNEXDI1ea+gWXufnmA7D1XQxIDsrgbzRMGKgEo4YLpPg+DEBm3wjwpqbuAgo3 RGB7U8EXJcus4yFvIrBwdDbQpsWluPQJCQWM9iHn0odJomcpvnoh17BYv0UIVSimZRs4 Gf+jejTLaTjYSbFRcXqxWkHBGLlP77wk1pk28RUSYsok8kXrjcy/H/+qtPfijbJ6Mhj1 AuWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=eJpQMTL9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id k18-20020adfb352000000b00241fab5a296sm27785372wrd.40.2023.01.16.12.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 12:48:04 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Cc: Dmitry Baryshkov Subject: [PATCH v7 6/7] ARM: dts: qcom: add missing clock configuration for kpss-acc-v1 Date: Mon, 16 Jan 2023 21:47:50 +0100 Message-Id: <20230116204751.23045-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230116204751.23045-1-ansuelsmth@gmail.com> References: <20230116204751.23045-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755213890141037516?= X-GMAIL-MSGID: =?utf-8?q?1755213890141037516?= Add missing clock configuration by adding clocks, clock-names, clock-output-names and #clock-cells bindings for each kpss-acc-v1 clock-controller to reflect Documentation schema. Reviewed-by: Dmitry Baryshkov Signed-off-by: Christian Marangi --- arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++++++ arch/arm/boot/dts/qcom-msm8960.dtsi | 8 ++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 1e68b42acb91..af84f2d350ef 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -389,21 +389,37 @@ timer@200a000 { acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; acc2: clock-controller@20a8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu2_aux"; + #clock-cells = <0>; }; acc3: clock-controller@20b8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu3_aux"; + #clock-cells = <0>; }; saw0: power-controller@2089000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index de87fcaaa836..e796094a7af5 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -580,6 +580,10 @@ l2cc: clock-controller@2011000 { acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; saw0: regulator@2089000 { @@ -591,6 +595,10 @@ saw0: regulator@2089000 { acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; saw1: regulator@2099000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 3bd07cac315b..4fd56d85be3f 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -208,11 +208,19 @@ regulators { acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; saw0: regulator@2089000 { From patchwork Mon Jan 16 20:47:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 44317 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1399500wrn; Mon, 16 Jan 2023 13:03:41 -0800 (PST) X-Google-Smtp-Source: AMrXdXsQAqnbitJwviglfZsaZTZBb/AwDnFNG4zqAmtCpDZ15ZatnQdkLx77EzeZj6v3ONokl9ZU X-Received: by 2002:a05:6a00:3025:b0:58d:a683:bb2f with SMTP id ay37-20020a056a00302500b0058da683bb2fmr945904pfb.23.1673903020988; Mon, 16 Jan 2023 13:03:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673903020; cv=none; d=google.com; s=arc-20160816; b=MmvdbQUAh2YigMf4CZcjEFf8UdFmd4JNxE2VsraPMEYrxuQLfa4JUM92mtAVWJoT/e PlYpEOv4VaRAHS3QZKItbRx1MuDmP8CKkfsDics5uTbVYAoPVLwS6VPNGsOR8H/8YjQr T3Mp/1iJNgmYZXrjQHW6P4dAo15vFMPWjdt1rViOqxrYvuirnnkThxb1VMXlk17MPXdM GzIO2Nw1L2//zAJ3z8p5UMCzpqDwfLEDybzvMd6PQcm1tofiqm11wMKdkMaC2Zsxxmko 1kFVEpui6Q1nvPkbyuBOITow/UYaREHUBTpA0oTjPJtkv7Op15JgfoDsDZmEwrgCDxlj Bgaw== ARC-Message-Signature: i=1; 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[93.34.92.88]) by smtp.googlemail.com with ESMTPSA id k18-20020adfb352000000b00241fab5a296sm27785372wrd.40.2023.01.16.12.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 12:48:05 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Christian Marangi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v7 7/7] ARM: dts: qcom: rename kpss-acc-v2 nodes to power-manager nodes Date: Mon, 16 Jan 2023 21:47:51 +0100 Message-Id: <20230116204751.23045-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230116204751.23045-1-ansuelsmth@gmail.com> References: <20230116204751.23045-1-ansuelsmth@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755214534070704710?= X-GMAIL-MSGID: =?utf-8?q?1755214534070704710?= Change kpss-acc-v2 nodes naming to power-manager to reflect Documentation schema. Signed-off-by: Christian Marangi Reviewed-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8084.dtsi | 8 ++++---- arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++---- arch/arm/boot/dts/qcom-msm8974.dtsi | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 4b0d2b4f4b6a..e70ab70b6697 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -353,25 +353,25 @@ saw_l2: power-controller@f9012000 { regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-manager@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; }; - acc1: clock-controller@f9098000 { + acc1: power-manager@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; }; - acc2: clock-controller@f90a8000 { + acc2: power-manager@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; }; - acc3: clock-controller@f90b8000 { + acc3: power-manager@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index acb08dcf9442..442062b433fc 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -325,22 +325,22 @@ crypto: crypto@8e3a000 { status = "disabled"; }; - acc0: clock-controller@b088000 { + acc0: power-manager@b088000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; }; - acc1: clock-controller@b098000 { + acc1: power-manager@b098000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; }; - acc2: clock-controller@b0a8000 { + acc2: power-manager@b0a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; }; - acc3: clock-controller@b0b8000 { + acc3: power-manager@b0b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 4b485f5612c4..705ae61ee35c 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -416,22 +416,22 @@ saw_l2: power-controller@f9012000 { regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-manager@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; }; - acc1: clock-controller@f9098000 { + acc1: power-manager@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; }; - acc2: clock-controller@f90a8000 { + acc2: power-manager@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; }; - acc3: clock-controller@f90b8000 { + acc3: power-manager@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; };