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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:27 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 1/6] x86/cpufeature: add cpu feature bit for LKGS Date: Thu, 13 Oct 2022 13:01:29 -0700 Message-Id: <20221013200134.1487-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746605420808099110?= X-GMAIL-MSGID: =?utf-8?q?1746605420808099110?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for LKGS (Load "Kernel" GS). LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specificaton https://cdrdv2.intel.com/v1/dl/getContent/678938. LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor cache, which is exactly what Linux kernel does to load a user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Chang S. Bae Signed-off-by: Xin Li Link: https://lkml.org/lkml/2022/10/11/1139 --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b71f4f2ecdd5..3dc1a48c2796 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index ef4775c6db01..9d45071d1730 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ From patchwork Thu Oct 13 20:01:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 2354 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp465109wrs; Thu, 13 Oct 2022 13:24:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7hJcMMBy+BkjDXXfCZW4PjBIQ4z4urYnQEulfUmRxY/3/C5hCxkEKdqzNGs4hB7DRHbjzR X-Received: by 2002:a63:ed0a:0:b0:442:2514:95f5 with SMTP id d10-20020a63ed0a000000b00442251495f5mr1459263pgi.402.1665692657986; Thu, 13 Oct 2022 13:24:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665692657; cv=none; d=google.com; s=arc-20160816; b=j1AU4qYiGNK13okJ7nHep2q9l2uzl8J1Tx648+eDbhOEX4j8a7KKdj3a2g1u0D8QEd 6rDcuD2d72oKzHziC1kX39lN1j1ZRq66Dqjb6UGW1IJWkZqGcMuQzp/CIN0VbrpsqI5E 7AxXsu+9t6IE1mr5eoqQ5oNCV5zPN69nfT1WkHb2dV0XN1sRc4HGaDWY0W5wedGn8sDI EyCuJKIcxCbGT1iFJBv670LrcbMsnWkngoonQ+5Dt6KlRZQHpaO1YlQbGp4VDUD5BTMa dve19W2KXBzBe4dqcbM4uaR28+KVAo1QRWQD55oGN9nIX3nr7oc4Gt1/fk4r4BznR2uE Plzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+3L/zBhMiW903xYBCmWze24Rs8tywihmXNz1C+Zm5Es=; b=m6d2gnKpfAgWaG0OuN3SPWtBkLRCOgdpeHpIalKNJqXCXyy7VF8WoUcTXlQdCHa12i wjMgKLncXkI8BIlAkq70kdZ7TzsO+8aoxeOEpFRt625nmV6iOF+eqmgw8iMoIX965Mtt 6nkVkJ6toGQ4xZOAF8oI5PIZtr69fcwUMulL4tv5h/x9ptCt5WUqSoXiYmB1bIuKv0mL PhwbIl0Vgl8djVvBZMc8RCK0Gzoc9LJSgj3zyxR/IsaYcYzmW2nLzvdFpQ05LhQaaJIY MdGOHuRpaAbkBy2fXpw7SOloG7OlAU/KL4n+8sUwAGvU43vAoqafX/7lJxV54VHZEkhN gO6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=AKsPAOgk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:27 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 2/6] x86/opcode: add LKGS instruction to x86-opcode-map Date: Thu, 13 Oct 2022 13:01:30 -0700 Message-Id: <20221013200134.1487-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746605344442129929?= X-GMAIL-MSGID: =?utf-8?q?1746605344442129929?= From: "H. Peter Anvin (Intel)" Add the instruction opcode used by LKGS. Opcode number is per public FRED draft spec v3.0 https://cdrdv2.intel.com/v1/dl/getContent/678938. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 From patchwork Thu Oct 13 20:01:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 2355 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp465218wrs; Thu, 13 Oct 2022 13:24:37 -0700 (PDT) X-Google-Smtp-Source: AMsMyM77d8Gre4sM+vnyRd/wR6bDXYjHQoEMeZICj6CtALkrpM6oM6sZobDa+hTzWbmQKfhgOgiB X-Received: by 2002:a05:6a00:21c8:b0:52e:3404:eba5 with SMTP id t8-20020a056a0021c800b0052e3404eba5mr1556135pfj.67.1665692677434; Thu, 13 Oct 2022 13:24:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665692677; cv=none; d=google.com; s=arc-20160816; b=FfrZrs7VIuW0hx4nvSClxzgfagRcVNycZGSSO8HH+BBAOs9U1Iq9swbCxV2hOfstFs lgt/K6fJrK+rR1NoAxi9O4rYI7ua4BgZL0vztI3/q7LQbX83gIIqDnfyh41em0udpz/y 63lEtXf04/T4I+aioDV3qwNO8G7GhykKITUfg3lqNkZ84kUwkNF2EzFitfjPEhHJ9oJu k71q0Ngx17eoRIsO1gzjE+jlIgPXqy+iOf0gYAyIDhkk8J8LHKSocopBG6pvO/3RSttr Gr/jgF3a8fLJKe+9Jvfl6be7Q+apfQxxMjFowEyPsr2nOhfF9sSqJNSOXo4FHWA5SJ9O cFWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y0zyNmAYzT3ri+4nefmoVJ0xInwrkHd8fCwz/8mxmhE=; b=Xj1d1nd+/s819AWd+0TH+nij/RMUuVMS0oY2gqPXc2CzzYc9AiHk0maE9lIQbJ9QxJ jYgh+ouNZboJcx5UjbSufopC3b9y2W2bkXC38gJ9FoCJWWR6QdA1+CDievJvuKeCbsuf wVDZYyYWuwgVCkFVY7z4MVNzistNtQKexXViJH2bsp6frnYFZzD/FUNB7jtu6qbE161U wlbiRnRrEoZJyZn+RTD3M3C8kVoImBGk/uFDehyGeGCpH1BzJKwVLq5uS3NwP+x3WD4x HAzMKrtXWc0xawfOIHR5DxJ2DUb82HnDsE3eHgcaPV138Arv9VDFxG+XNjXTN8/ZTfFX gkxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=c6YHXMAq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:27 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 3/6] x86/gsseg: make asm_load_gs_index() take an u16 Date: Thu, 13 Oct 2022 13:01:31 -0700 Message-Id: <20221013200134.1487-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746605364923261807?= X-GMAIL-MSGID: =?utf-8?q?1746605364923261807?= From: "H. Peter Anvin (Intel)" Let gcc know that only the low 16 bits of load_gs_index() argument actually matter. It might allow it to create slightly better code. However, do not propagate this into the prototypes of functions that end up being paravirtualized, to avoid unnecessary changes. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/special_insns.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 9953d966d124..e0c48998d2fb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -779,7 +779,7 @@ _ASM_NOKPROBE(common_interrupt_return) /* * Reload gs selector with exception handling - * edi: new selector + * di: new selector * * Is in entry.text as it shouldn't be instrumented. */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 35f709f619fb..a71d0e8d4684 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,7 +120,7 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(unsigned int selector); +extern asmlinkage void asm_load_gs_index(u16 selector); static inline void native_load_gs_index(unsigned int selector) { From patchwork Thu Oct 13 20:01:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 2356 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp465466wrs; Thu, 13 Oct 2022 13:25:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5SMM2hTzQi6gbG0+xpoxtW2OO+yNd1wHYymWeJ5mvzI9bTpZ/xgGUwUT208V32jdlnOr0A X-Received: by 2002:a17:902:b942:b0:178:be25:203f with SMTP id h2-20020a170902b94200b00178be25203fmr1750786pls.101.1665692730549; Thu, 13 Oct 2022 13:25:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665692730; cv=none; d=google.com; s=arc-20160816; b=YVnmAlN+ZmYy+9xdmyj2DSODWMUa1faohKzPfuguEUz7Vce6N+2MINpWXEgoLobjPG 96hy8M/PDdUEVEexn25yh84/KYZKWjap+muJWL1jJxAqS2QvrL7SR+l1oB2BRNqRGzXA O5QcYtznmowlrGhWw/B7r4oM4xxnkexynHNN0t2U3ka+UXOH71tmxRt1nNeCQ5IGeuBS pK0Euehwkp1+DLlyLuykNKiV5VfswPsTZ7l8LSdbXB3QbaozVMua2qkGHdhiSQxXXVHj TsTWREHACJQRkPa7yO66jQKk6LA6xFXU1C7WkNwiYiFVhXRd78trq3RS0svKMJLQQ10M gjqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Mwx0bmL/iflkPSrLZX+z7nHqjep5uXu6l2HfgDQDt2o=; b=sY1XVGgLxxl9SntezX7l2CICivZnP5hseGipSGLmjmjO9t52VWRMUHrOlbelgmicMe qNseo0l7m5q/Nb052Zl1BmS4QUoqUu4un5KQ2oQf0GHiyrYZqWlK/Dz4etmHv8gmg/Oo AUe0vlqdxYto2+eXqEq4lvcOtGrV4TP/r4lJPArMDBuJylKyQQhTDHUJxN1C8E5/Spai csl9Cll9IvTNXQynAULvsLwY9TbaIDKAfc8azT6zOksX5TTK6ssCbbmIddtSDrfK+SNZ /qMQtt88ywIgqVUbW6Q4bqk4onfXJlAHA1wlMPnqXrZmhZM9GwFPbeqIIckfGJEPVihU pjWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=JXX3Y2FF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:27 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 4/6] x86/gsseg: move local_irq_save/restore() into asm_load_gs_index() Date: Thu, 13 Oct 2022 13:01:32 -0700 Message-Id: <20221013200134.1487-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746605420715235638?= X-GMAIL-MSGID: =?utf-8?q?1746605420715235638?= From: "H. Peter Anvin (Intel)" The need to disable/enable interrupts around asm_load_gs_index() is a consequence of the implementation. Prepare for using the LKGS instruction, which is locally atomic and therefore doesn't need interrupts disabled. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 26 +++++++++++++++++++++----- arch/x86/include/asm/special_insns.h | 4 ---- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index e0c48998d2fb..cc6ba6672418 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -778,19 +778,35 @@ SYM_CODE_END(common_interrupt_return) _ASM_NOKPROBE(common_interrupt_return) /* - * Reload gs selector with exception handling + * Reload gs selector with exception handling. This is used only on + * native, so using swapgs, pushf, popf, cli, sti, ... directly is fine. + * * di: new selector + * rax: scratch register * * Is in entry.text as it shouldn't be instrumented. + * + * Note: popf is slow, so use pushf to read IF and then execute cli/sti + * if necessary. */ SYM_FUNC_START(asm_load_gs_index) FRAME_BEGIN + pushf + pop %rax + andl $X86_EFLAGS_IF, %eax /* Interrupts enabled? */ + jz 1f + cli +1: swapgs .Lgs_change: ANNOTATE_NOENDBR // error_entry movl %edi, %gs 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE swapgs + testl %eax, %eax + jz 3f + sti +3: FRAME_END RET @@ -799,12 +815,12 @@ SYM_FUNC_START(asm_load_gs_index) swapgs /* switch back to user gs */ .macro ZAP_GS /* This can't be a string because the preprocessor needs to see it. */ - movl $__USER_DS, %eax - movl %eax, %gs + movl $__USER_DS, %edi + movl %edi, %gs .endm ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG - xorl %eax, %eax - movl %eax, %gs + xorl %edi, %edi + movl %edi, %gs jmp 2b _ASM_EXTABLE(.Lgs_change, .Lbad_gs) diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index a71d0e8d4684..6de00dec6564 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -124,11 +124,7 @@ extern asmlinkage void asm_load_gs_index(u16 selector); static inline void native_load_gs_index(unsigned int selector) { - unsigned long flags; - - local_irq_save(flags); asm_load_gs_index(selector); - local_irq_restore(flags); } static inline unsigned long __read_cr4(void) From patchwork Thu Oct 13 20:01:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 2357 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp465467wrs; Thu, 13 Oct 2022 13:25:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4qwdGFlu6I0RfXh85wRnAMYV1qvIQqta47eiaeFtNqKFzqiMdlSl487lsP6qyKdQDT8HFK X-Received: by 2002:a17:90b:3892:b0:20d:4bb5:91fe with SMTP id mu18-20020a17090b389200b0020d4bb591femr1714250pjb.31.1665692730565; Thu, 13 Oct 2022 13:25:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665692730; cv=none; d=google.com; s=arc-20160816; b=pf9E17wiupegvI2RyHtxruXPNm/EmRzwZiVqWqCB7osFjMPKBfoXrJmoXYHNR/x1ou /gsJ9F0LMcT9NuGL4YCr0+piJPp4Jki6uRvOKJhTZr48yJ8WczDNP7AEKqQ3DK00GUlz Ti8yYO+OpTSNoWfAMKNaChv33uCkjC55t21YWVSnYiPkWYz4LvemP3f3wzueQ8fQn7Bp DLye6EF0veCWOjJHgIJjjfhACtXE1FIMQKtcXyxu3/UA+tVVLYsc6FS+P+I2Tj1W9jJQ X27yaP22X2gtTaJU8ZjoCOkSkbiYFdJHUDbG+2dSfEwTqgkzV2rOVNx9obxoCjby6Al6 YgJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pZm/kyqoGIWzVOoMvTkc5/EE4DN9bg8f556Rl51v5Cs=; b=HubmbfQDzujLNB8CWC/Yrhw2P7QImGYCfXj804eD3ohXrIcLplSXuqnqcc1kWpLCP7 GUhioMGP7F4aBkBH9tplCXIETegjlid993dhLgHYiNHDsEKBhm4On8Y+tQ8HTmv47GLB XGyiA0AeV6RUGT0YrfBhJ2IPstH2KXaiQ3K+fxGB8CyG0WJOGJdYqqD44VgsvcfraR/6 QDeoepBDv1K4lD4swmRAkQtazKgXMva7eh55oQ4MmGGrQURmot6IJy8gt+Azrp2+7jLa SMTs/LJmiYdKtJvumH69LCSkwEopRd5spdr5aI/hOzhLG4VhvK+jGcGLarl4Tj3/xjaG +UWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=AIgriEcA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:28 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 5/6] x86/gsseg: move load_gs_index() to its own header file Date: Thu, 13 Oct 2022 13:01:33 -0700 Message-Id: <20221013200134.1487-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746605420605888313?= X-GMAIL-MSGID: =?utf-8?q?1746605420605888313?= From: "H. Peter Anvin (Intel)" depends on , so in order to be able to use alternatives in native_load_gs_index(), factor it out into a separate header file. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/ia32/ia32_signal.c | 1 + arch/x86/include/asm/gsseg.h | 32 ++++++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 17 --------------- arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/tls.c | 1 + 6 files changed, 36 insertions(+), 17 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index c9c3859322fa..14c739303099 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -34,6 +34,7 @@ #include #include #include +#include static inline void reload_segments(struct sigcontext_32 *sc) { diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h new file mode 100644 index 000000000000..5e3b56a17098 --- /dev/null +++ b/arch/x86/include/asm/gsseg.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_GSSEG_H +#define _ASM_X86_GSSEG_H + +#include +#include + +#ifdef CONFIG_X86_64 + +extern asmlinkage void asm_load_gs_index(u16 selector); + +static inline void native_load_gs_index(unsigned int selector) +{ + asm_load_gs_index(selector); +} + +#endif /* CONFIG_X86_64 */ + +#ifndef CONFIG_PARAVIRT_XXL + +static inline void load_gs_index(unsigned int selector) +{ +#ifdef CONFIG_X86_64 + native_load_gs_index(selector); +#else + loadsegment(gs, selector); +#endif +} + +#endif /* CONFIG_PARAVIRT_XXL */ + +#endif /* _ASM_X86_GSSEG_H */ diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index b8d40ddeab00..e01aa74a6de7 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -12,6 +12,7 @@ #include #include #include +#include extern atomic64_t last_mm_ctx_id; diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 6de00dec6564..cfd9499b617c 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,13 +120,6 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(u16 selector); - -static inline void native_load_gs_index(unsigned int selector) -{ - asm_load_gs_index(selector); -} - static inline unsigned long __read_cr4(void) { return native_read_cr4(); @@ -180,16 +173,6 @@ static inline void wbinvd(void) native_wbinvd(); } - -static inline void load_gs_index(unsigned int selector) -{ -#ifdef CONFIG_X86_64 - native_load_gs_index(selector); -#else - loadsegment(gs, selector); -#endif -} - #endif /* CONFIG_PARAVIRT_XXL */ static inline void clflush(volatile void *__p) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 7ca2d46c08cc..00f6a92551d2 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * nop stub, which must not clobber anything *including the stack* to diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c index 3c883e064242..3ffbab0081f4 100644 --- a/arch/x86/kernel/tls.c +++ b/arch/x86/kernel/tls.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "tls.h" From patchwork Thu Oct 13 20:01:34 2022 Content-Type: text/plain; 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:28 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 6/6] x86/gsseg: use the LKGS instruction if available for load_gs_index() Date: Thu, 13 Oct 2022 13:01:34 -0700 Message-Id: <20221013200134.1487-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746605448753364896?= X-GMAIL-MSGID: =?utf-8?q?1746605448753364896?= From: "H. Peter Anvin (Intel)" The LKGS instruction atomically loads a segment descriptor into the %gs descriptor registers, *except* that %gs.base is unchanged, and the base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly what we want this function to do. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Brian Gerst Signed-off-by: Xin Li link: https://lkml.org/lkml/2022/10/7/352 link: https://lkml.org/lkml/2022/10/7/373 link: https://lkml.org/lkml/2022/10/10/1286 --- arch/x86/include/asm/gsseg.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h index 5e3b56a17098..7463ac65ef56 100644 --- a/arch/x86/include/asm/gsseg.h +++ b/arch/x86/include/asm/gsseg.h @@ -3,15 +3,39 @@ #define _ASM_X86_GSSEG_H #include + +#include +#include +#include #include +#include #ifdef CONFIG_X86_64 extern asmlinkage void asm_load_gs_index(u16 selector); +/* Replace with "lkgs %di" once binutils support LKGS instruction */ +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7) + static inline void native_load_gs_index(unsigned int selector) { - asm_load_gs_index(selector); + u16 sel = selector; + + /* + * Note: the fixup is used for the LKGS instruction, but + * it needs to be attached to the primary instruction sequence + * as it isn't something that gets patched. + * + * %rax is provided to the assembly routine as a scratch + * register. + */ + asm_inline volatile("1:\n" + ALTERNATIVE("call asm_load_gs_index\n", + _ASM_BYTES(0x3e) LKGS_DI, + X86_FEATURE_LKGS) + _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel]) + : ASM_OUTPUT2([sel] "+D" (sel), ASM_CALL_CONSTRAINT) + : : _ASM_AX); } #endif /* CONFIG_X86_64 */