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Thu, 13 Oct 2022 11:39:10 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:39:10 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:39:06 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 01/21] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select" Date: Fri, 14 Oct 2022 00:08:34 +0530 Message-ID: <20221013183854.21087-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT010:EE_|SA1PR12MB7320:EE_ X-MS-Office365-Filtering-Correlation-Id: 5caef5e4-3b86-4085-f550-08daad4a3ded X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:20.2974 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5caef5e4-3b86-4085-f550-08daad4a3ded X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7320 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599609014711632?= X-GMAIL-MSGID: =?utf-8?q?1746599609014711632?= The GPIO DT property "nvidia,refclk-select" to select the PCIe reference clock is optional. Use devm_gpiod_get_optional() to get it. Signed-off-by: Vidya Sagar --- V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 9e64b948f999..d7ab33931de4 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1233,9 +1233,9 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) return err; } - pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, - "nvidia,refclk-select", - GPIOD_OUT_HIGH); + pcie->pex_refclk_sel_gpiod = devm_gpiod_get_optional(pcie->dev, + "nvidia,refclk-select", + GPIOD_OUT_HIGH); if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); const char *level = KERN_ERR; From patchwork Thu Oct 13 18:38:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2306 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp428813wrs; Thu, 13 Oct 2022 11:52:57 -0700 (PDT) X-Google-Smtp-Source: AMsMyM61TEr/H4NRAT4+YoDOuJBk/iyts6Xs9q+GzZAvMchd4eUpO/lZlYgE/yuTk8WjN5WwyE2g X-Received: by 2002:a17:90b:4ac5:b0:20d:ae54:f08b with SMTP id mh5-20020a17090b4ac500b0020dae54f08bmr3039528pjb.174.1665687176954; Thu, 13 Oct 2022 11:52:56 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687176; cv=pass; d=google.com; s=arc-20160816; b=QeWTAqgvvoJZp2BSa9TpV9THv+BhGhyuP1ZQhG815z23FxnSbYBlLkf2c4k7C6rkrp lgV4IcKtd8wdAuYD83u8XxRFHY174s5vf6jDABE9km472LqRN4kzBcO82kHvEYuIrDIG hpsbZww3F3KvXZSwj/fXuH/uVT6mfw27rqIPC419Y/JeDUJl8D8X0TVNe4nC4nwXw3wx wyWiublKBoVdH3D8lqD678hKbX+RfUnB35xpVNdlnqtJUWUxDjlgG+2I3IM57pRmR9r0 yhm/qvRfftzdIdKpPLhgdM2tsCJliWkEtlua+0BVrEsIDR+vSbEzLutCuHerSVailyTQ 4Rgg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=L2SDBLtaFY9fUZ7B1MAtE1kvtsVnPPZ5erFTxMZVi74=; b=ex2i1Eg3ph3GRDwxx/isPEC9ZIwTCZwMoZ/X3y5o1+pcLRdTSMikHotZx4ylm/Z4Jp rBrBxCWnw2H/T33GqkmzEm2Sr8JvJO/HIq0IxwlDhCbskHra43CcQC0N3AcUPZgOnuZR 1K8CeS0WWDjD90FROJURclchwJQ1f0+DTmYwHQa9UdMUahpd1reISpPY2mGJCkBqj9IB /qu2Ff4lfxFvyicT15ql702Lu2vd5QS/yArUGkxxzAVp1QJ3K91x8LU4o15bIyFJuV4e fGNZpg5gftJCBagCArtoFHg1pUxF9c2CU4OvWrtQgFKBAX3PBUWvS0lF0DNbDrz049d0 lDuw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="MdSMXr/f"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Thu, 13 Oct 2022 11:39:17 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:39:16 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:39:12 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 02/21] PCI: tegra194: Drive CLKREQ signal low explicitly Date: Fri, 14 Oct 2022 00:08:35 +0530 Message-ID: <20221013183854.21087-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT050:EE_|SN7PR12MB7021:EE_ X-MS-Office365-Filtering-Correlation-Id: 0beea1e1-012d-4ef4-7da8-08daad4a42c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:28.3936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0beea1e1-012d-4ef4-7da8-08daad4a42c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7021 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599597469792051?= X-GMAIL-MSGID: =?utf-8?q?1746599597469792051?= Currently, the default setting is that CLKREQ signal of a Root Port is internally overridden to '0' to enable REFCLK to flow out to the slot. It is observed that one of the PCIe switches (case in point Broadcom PCIe Gen4 switch) is propagating the CLKREQ signal of the root port to the downstream side of the switch and expecting the endpoints to pull it low so that it (PCIe switch) can give out the REFCLK although the Switch as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this patch drives the CLKREQ of the Root Port itself low to avoid link up issues between PCIe switch downstream port and endpoints. This is not a wrong thing to do after all the CLKREQ is anyway being overridden to '0' internally and now it is just that the same is being propagated outside also. Signed-off-by: Vidya Sagar --- V3: * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index d7ab33931de4..a33c86e3de9d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -47,6 +47,7 @@ #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE BIT(13) #define APPL_CTRL 0x4 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) @@ -1510,6 +1511,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, val = appl_readl(pcie, APPL_PINMUX); val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; + val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE; appl_writel(pcie, val, APPL_PINMUX); } From patchwork Thu Oct 13 18:38:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2314 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429346wrs; Thu, 13 Oct 2022 11:54:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5B1/YJGjVD+Q/OHOaiUIuyZ4690Nk251mEv6TnhkbbVCy8zuEMsmYHNFot3hUnlR4i0TtR X-Received: by 2002:a17:90b:4c42:b0:20d:7820:2e4e with SMTP id np2-20020a17090b4c4200b0020d78202e4emr12849150pjb.40.1665687264486; Thu, 13 Oct 2022 11:54:24 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687264; cv=pass; d=google.com; s=arc-20160816; b=0j7s1hffY0VxG9eUT3EnmdCy+EnIE+YPAEmKoenw1QJf7abVkNP2L59MdUVwZ+NLei 1Y4tze3kSSWlrge9isHQkIC+nnatw3OIBy8qQDFqYv9DiqI1bjIqpxkjj0jWKE8xuDGd NKgucx/M5g35lgXZcYIr4UFKlYHTHGEzSwaJbwjVzUtK4oa2Wrvjg4QhyrXldChUfu4+ innecQO5K7d+ydpg9oylofb4zlr7y4p9bPwcnrfea7m30sj5NFHtC4WrPmXnvkQBrDfc hLkpg8MMblqaw/J+tz5zzZXyWmfsHxL9W9DU0ehyrs465bMvgOSU1StaWOiyd/UW1//c N1Qw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=TBq528JAPZeXu0EMALg3NgzpdfQf6SWx9QDHMwRTqSg=; b=IASEd3cl1x/00nKqy2VSLrbvEC6F80o3FsUsKDviXtbCdT2Fb5SwAZ8wgtxdxi2Hdp 5nltWPkUOJig3tI+wXfE27ShJsrolC4yttGSK2JmbnAt4WM27so4UTmxrKnCoUUAM4Fb bST3hXtW/twU5n5L8d9MlnWJiTbMEiNWckr3oHRVVn746YnqTWAzLfgT0fdGAUIgTAjx aqwLW6Y8otfuQTMAguepVJWpMnaog1/N17t1weVPY6WlAJa33D/YyuFwcvnffHIz9hes AxHNicwhBkEBnO/yzzEZE4akakqCXrDpxAVNfH2ZBulfqOl8J8OxKUTDSu9JZqVRogyN r/hw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=sRl+oBpS; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:33.2554 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f8260e9-1b4f-43d6-cec7-08daad4a45a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5605 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599688808907865?= X-GMAIL-MSGID: =?utf-8?q?1746599688808907865?= As per PCIe spec r6.0, sec 5.3.3.2.1, after sending PME_Turn_Off message, Root port should wait for 1~10 msec for PME_TO_Ack message. Currently, driver is polling for 10 msec with 1 usec delay which is aggressive. Change it to 10 msec polling with 100 usec delay. Since this function is used in non-atomic context only, use non-atomic poll function. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar --- V3: * Changed atomic call to non-atomic call * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index a33c86e3de9d..685aee378c93 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -207,7 +207,8 @@ #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 -#define PME_ACK_TIMEOUT 10000 +#define PME_ACK_DELAY 100 /* 100 us */ +#define PME_ACK_TIMEOUT 10000 /* 10 ms */ #define LTSSM_TIMEOUT 50000 /* 50ms */ @@ -1611,9 +1612,9 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) val |= APPL_PM_XMT_TURNOFF_STATE; appl_writel(pcie, val, APPL_RADM_STATUS); - return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, - val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, - 1, PME_ACK_TIMEOUT); + return readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, + val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, + PME_ACK_DELAY, PME_ACK_TIMEOUT); } static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) From patchwork Thu Oct 13 18:38:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2313 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429345wrs; Thu, 13 Oct 2022 11:54:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5NAAOmN8bZpbAAnLI5dVtct0nSXCaaeht66xiEKFPczFtZWQbUAk6Tr9YArelSowLTQwpW X-Received: by 2002:a17:902:7589:b0:178:4ded:a90a with SMTP id j9-20020a170902758900b001784deda90amr1319580pll.74.1665687264484; Thu, 13 Oct 2022 11:54:24 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687264; cv=pass; d=google.com; s=arc-20160816; b=E0SCUATV9cYh3AZhVrQK3uoG62lKpnTHQGl3MPD6t8CrB4GTvWa+vwafcMKuaQK3b7 nrcwbXtYPK0/C4F/CzeJuUzP2y3tDbv/GXmRTmHdOdgnD5bf9Xtxv5k1LMIGpIE73ZD0 5j+PGatmFw9iJyDDdodNNrFeAG7x8wO/1/5doL1J63gu8+g+etzannc6M5rFPORgIoUR ziCXEeFnV2Ek9YaHGkO2/Uwy41sFhHzBiawjTyk0mVgTauKLQZhpD2SQNMINQyt2ZmYL n5PObZ2gVn3cK85G7KPFHWl62OnyYFYj/2J7vxUeWrz5eiWUOrK/5Xr8wIofQnEuZri6 uQtA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=SwtI5cUpY3q0pk36QJSITZFZxxHq+HlogbzFWEdtcgE=; b=nAXnDmCWB2N3QYNzHgd9mSp86gvXEbwvMQL+RqbN6smwo6Jeijrf7xquVo3iW0QCzF 1XQ3mpBLRALGbbzGoSUZIuEJykTklfzeEGlwxgsYyW2f6JeliBe6vG3/IohyOixxS0fr VjHj/vZAkkxlEYX1UlJqC+Irl54t/MFbNyvC2dQEfJwCBcHgEPJP1pJw/WEE1khQ1T6U vKlV+UHHn52MFhSYNXGtPEy3TWTXJ8L4GdifIt2xJz6zj7xtvD8DwCp2spzC6GGaUS2W +Qbvq4AW242L0OLGhMywcHtFs6QNOKjKmsisvpGdLAXphn672WsIcd7MTahVnU/AAKhr zdzQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=AATFWn7q; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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If the transaction succeeded, we also need to check the actual command's result code. Add code to do this. Signed-off-by: Vidya Sagar --- V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 685aee378c93..ae7e0d8f693b 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1260,6 +1260,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, struct mrq_uphy_response resp; struct tegra_bpmp_message msg; struct mrq_uphy_request req; + int err; /* * Controller-5 doesn't need to have its state set by BPMP-FW in @@ -1282,7 +1283,13 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, msg.rx.data = &resp; msg.rx.size = sizeof(resp); - return tegra_bpmp_transfer(pcie->bpmp, &msg); + err = tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + return err; + if (msg.rx.ret) + return -EINVAL; + + return 0; } static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, @@ -1291,6 +1298,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, struct mrq_uphy_response resp; struct tegra_bpmp_message msg; struct mrq_uphy_request req; + int err; memset(&req, 0, sizeof(req)); memset(&resp, 0, sizeof(resp)); @@ -1310,7 +1318,13 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, msg.rx.data = &resp; msg.rx.size = sizeof(resp); - return tegra_bpmp_transfer(pcie->bpmp, &msg); + err = tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + return err; + if (msg.rx.ret) + return -EINVAL; + + return 0; } static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) From patchwork Thu Oct 13 18:38:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2309 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp428886wrs; Thu, 13 Oct 2022 11:53:09 -0700 (PDT) X-Google-Smtp-Source: AMsMyM63FcSVtq5O/yZhJebrVnXCSH1QoYKFoPi9n8AU8xgTlMnIAiALeHv3E5HyuX9owqYWZRdD X-Received: by 2002:a17:90b:3b45:b0:20c:2eae:e70 with SMTP id ot5-20020a17090b3b4500b0020c2eae0e70mr1317725pjb.240.1665687189267; Thu, 13 Oct 2022 11:53:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687189; cv=pass; d=google.com; s=arc-20160816; b=NgAlwGjXkTese1UuiPBFxDW/NXw7rSV7iXP4b2p2C6xQgJsJLjD2fA/JP41+FIIYGa fiw2H1nZAG277AO4ZVak4jE+A/Qi5652OyJNbhy3FiJY0TuZ0afMc/0dxJaytHUN3mTV qq5Dkk1I9Ez+XEp1e/z7r+6WKSHouCx2rdVDIIJMsghLkTHtYh+WYcAioCedYgW/Rv78 psqvP/NgDEyIOQcysS1HlvT7+FPWa4w/8rwhCgi80LouwGTesUPgpeTISABND3AjLtCd KClqeBVc3sCaorBQ1mIxjeEFZ3cKVjdY+01zdBWLjdxHNAJCVc0Pa1iP23UvM8g0OwiO Mn6w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=jsqlbVud5olieId7V11LFR3ftBXKyulSOt8ZhpHQmFY=; b=PsUOT43po9Xt6fsW+CeVmfOdtRA8ZN6RqjWVCN5ExBno5zOv2jOIAjywDWn38Kc2pw XILGo7TuLVNX9pUJCsovpkEDYQItAURgGNcAXgsct7wVVG4WSM501cZw9npzQag8H1Z/ hf67L0EShRzwQv2PWkgAQpHy3/9QEJH495E/Swvmb+T5LXXAt1K9SewdRSBZsWaZxh54 qgMwWDHo8tVNPceXvDwg2IFsQs4uLD/AnzExcfqkZN3r++607nG0/Rd7baVyrsmpUKCW hgTPwqUjnEFOfIpUqC2Fjk0u9PTElPoNmnRV5s7QOlVKgDe+Wkilvrhpa50mJTZN/0ux 3+tA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=SCQBEg5X; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Move pinctrl_pm_select_default_state() function call from root port specific configuration function to probe(). Signed-off-by: Vidya Sagar --- V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index ae7e0d8f693b..69e11a74a0d7 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1716,12 +1716,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) goto fail_pm_get_sync; } - ret = pinctrl_pm_select_default_state(dev); - if (ret < 0) { - dev_err(dev, "Failed to configure sideband pins: %d\n", ret); - goto fail_pm_get_sync; - } - ret = tegra_pcie_init_controller(pcie); if (ret < 0) { dev_err(dev, "Failed to initialize controller: %d\n", ret); @@ -2191,6 +2185,19 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) pp = &pci->pp; pp->num_vectors = MAX_MSI_IRQS; + ret = pinctrl_pm_select_default_state(dev); + if (ret < 0) { + const char *level = KERN_ERR; + + if (ret == -EPROBE_DEFER) + level = KERN_DEBUG; + + dev_printk(level, dev, + "Failed to configure sideband pins: %d\n", + ret); + return ret; + } + ret = tegra_pcie_dw_parse_dt(pcie); if (ret < 0) { const char *level = KERN_ERR; From patchwork Thu Oct 13 18:38:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2310 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp428937wrs; Thu, 13 Oct 2022 11:53:16 -0700 (PDT) X-Google-Smtp-Source: AMsMyM61nszL6jwH2BggNurk1DUDaf2baHGscVNP/xRrmjS6NuboLACyraMyFiW+LtyizmFM41UB X-Received: by 2002:a17:907:270f:b0:78d:728b:ff4 with SMTP id w15-20020a170907270f00b0078d728b0ff4mr836042ejk.501.1665687195791; Thu, 13 Oct 2022 11:53:15 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687195; cv=pass; d=google.com; s=arc-20160816; b=I/PgoSXlg7ZNGRs9dGoHIOSmKK4L8sxLAQW73VC4I5CQVQZ3LvAVKUF+7+49I6+dvC CDLvF91vUEa38jrYzDOU7aoGi5Ukz4T1q8z0bqJbOkV6paG5YSClJdFCW+UFcm09pufq lekvdl0xHfW1VuaxaKSqbRy/Xjok5h/5tVZfiwwF+QArdnDJbn8pWY95oWr++OIy2lFU 8SbN1tuQ3QVno4PTMTP+vEsIu8PdIlWGfxp5uZrGv2+TuRtD3Uh7MJBI4RInkitwcd6d Eo8g+CfLrCdKUWaA+NeZrp8WAg3FHm8UkbVgkqqEXyWu41VOb4chQUYAPB14aCG0Q6ol ijBg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Wyu6fTt0uPsz0f6b6dJQ1icECHhFxvqxTh7+vbJDwUU=; b=SJs4pZS/lEXbBtg1rUC4bKORHhGz46jzrwzESeQFkkQ9uiKLoc2LwhNwOWi5exhuZ6 aWPc/UCdvTCgWI3qLLr8RJw6eOmZnNjUp66juoDH1H5DuIz3hmdXeXl+Ynu65XII23Zj Q0BeJCAC4s9osqBqK8eC9QwrNiRr3cRsAKCeX3kCVW7kXDxDpB7IpfXb100nk16IWg9/ BL69Q0bfCnEhFfM7ti/1OFgPK7cdr2J49qa6Ro81RW8RwnhuEa8pV30Kq2b1Z9ZMkwUX DkFaB8Cc0MN4p9xjYJ2qW9jNpUr5TPRI3QnftmRlZ98uk0jcrSO0yplr+2/RIu3ZOQkt uhPQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=hzh0osXW; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Thu, 13 Oct 2022 11:39:42 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:39:42 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:39:38 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 06/21] PCI: tegra194: Refactor LTSSM state polling on surprise down Date: Fri, 14 Oct 2022 00:08:39 +0530 Message-ID: <20221013183854.21087-7-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT040:EE_|MW4PR12MB6827:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ef0a5bf-ff76-43b6-ecb9-08daad4a4ebd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:48.5195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ef0a5bf-ff76-43b6-ecb9-08daad4a4ebd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6827 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599617038403306?= X-GMAIL-MSGID: =?utf-8?q?1746599617038403306?= On surprise down, LTSSM state transits from L0 -> Recovery.RcvrLock -> Recovery.RcvrSpeed -> Gen1 Recovery.RcvrLock -> Detect. Recovery.RcvrLock and Recovery.RcvrSpeed transit times are 24 msec and 48 msec respectively. So, the total time taken to transit from L0 to detect state is ~96 msec. Hence, increase the poll time to 120 msec. Disable the LTSSM state after it transits to detect to avoid LTSSM toggling between polling and detect states. tegra_pcie_dw_pme_turnoff() function is called in non-atomic context only, so use the non-atomic poll function. Signed-off-by: Vidya Sagar --- V3: * Addressed review comments from Bjorn * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 55 +++++++++++++--------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 69e11a74a0d7..897e2a22bcd3 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -141,7 +141,11 @@ #define APPL_DEBUG_PM_LINKST_IN_L0 0x11 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3) #define APPL_DEBUG_LTSSM_STATE_SHIFT 3 -#define LTSSM_STATE_PRE_DETECT 5 +#define LTSSM_STATE_DETECT_QUIET 0x00 +#define LTSSM_STATE_DETECT_ACT 0x08 +#define LTSSM_STATE_PRE_DETECT_QUIET 0x28 +#define LTSSM_STATE_DETECT_WAIT 0x30 +#define LTSSM_STATE_L2_IDLE 0xa8 #define APPL_RADM_STATUS 0xE4 #define APPL_PM_XMT_TURNOFF_STATE BIT(0) @@ -210,7 +214,8 @@ #define PME_ACK_DELAY 100 /* 100 us */ #define PME_ACK_TIMEOUT 10000 /* 10 ms */ -#define LTSSM_TIMEOUT 50000 /* 50ms */ +#define LTSSM_DELAY 10000 /* 10 ms */ +#define LTSSM_TIMEOUT 120000 /* 120 ms */ #define GEN3_GEN4_EQ_PRESET_INIT 5 @@ -1663,23 +1668,22 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) data &= ~APPL_PINMUX_PEX_RST; appl_writel(pcie, data, APPL_PINMUX); + err = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data, + ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT), + LTSSM_DELAY, LTSSM_TIMEOUT); + if (err) + dev_info(pcie->dev, "Link didn't go to detect state\n"); + /* - * Some cards do not go to detect state even after de-asserting - * PERST#. So, de-assert LTSSM to bring link to detect state. + * Deassert LTSSM state to stop the state toggling between + * polling and detect. */ data = readl(pcie->appl_base + APPL_CTRL); data &= ~APPL_CTRL_LTSSM_EN; writel(data, pcie->appl_base + APPL_CTRL); - - err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, - data, - ((data & - APPL_DEBUG_LTSSM_STATE_MASK) >> - APPL_DEBUG_LTSSM_STATE_SHIFT) == - LTSSM_STATE_PRE_DETECT, - 1, LTSSM_TIMEOUT); - if (err) - dev_info(pcie->dev, "Link didn't go to detect state\n"); } /* * DBI registers may not be accessible after this as PLL-E would be @@ -1769,19 +1773,24 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) if (pcie->ep_state == EP_STATE_DISABLED) return; - /* Disable LTSSM */ + ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_L2_IDLE), + LTSSM_DELAY, LTSSM_TIMEOUT); + if (ret) + dev_err(pcie->dev, "LTSSM state: 0x%x timeout: %d\n", val, ret); + + /* + * Deassert LTSSM state to stop the state toggling between + * polling and detect. + */ val = appl_readl(pcie, APPL_CTRL); val &= ~APPL_CTRL_LTSSM_EN; appl_writel(pcie, val, APPL_CTRL); - ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, - ((val & APPL_DEBUG_LTSSM_STATE_MASK) >> - APPL_DEBUG_LTSSM_STATE_SHIFT) == - LTSSM_STATE_PRE_DETECT, - 1, LTSSM_TIMEOUT); - if (ret) - dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); - reset_control_assert(pcie->core_rst); tegra_pcie_disable_phy(pcie); From patchwork Thu Oct 13 18:38:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2315 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429432wrs; Thu, 13 Oct 2022 11:54:35 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5sTc6F1XAbwECS+97Tn+NkWdxtuF50pqdc40O2+UDn2fnWKf0sr/Cn1nmCwxWsK1eg1jbO X-Received: by 2002:a63:26c3:0:b0:46b:1dab:fd88 with SMTP id m186-20020a6326c3000000b0046b1dabfd88mr1126927pgm.251.1665687274736; Thu, 13 Oct 2022 11:54:34 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687274; cv=pass; d=google.com; s=arc-20160816; b=jJMTF74zThnyIlMMo0U7R4fBocIaMuiKVzDt+GzBw0kQmKoDxIPdppuixFnh9tpM94 n6+iEizrJtDxhJqBPI6GgqZ+lyGo5qh5b69Nh2oSeDOzfoYz9RhUj9m3DSf6V7ENa3mG xiabFfy8l0L5ssIabsyyz/rDs5AGyhIHdaZ8PctemzsjVE0ScxKWIgQ0aFIvBrjKFla/ FuShDgs5fJ2MJubGC0CuZs4PDCaP93OjcJaMr9j5w+nkuh01GT+AR54VYYQerdHAURzV 5nA59ykDigClVT0NL36dRXagoMiISOjL0b9JTDWOqq4byaJaIBkhs6n3RuDa9L6uwxm0 ch/g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=XeP2n9kvp0meTUaeqD+YLu2d/BVbWALLwpD5bIe6CYA=; b=jqfM8jaFgiJaf/BaBaObJrohJI4hFXE87aTT9LkRYbY5sbwaGarpaYjyMOeMEcOlba gYXCIoYa5NCS2n46DQpSUeD7XGKEfF81jGAmFWzbOWsnsuweT96z1gEw2GtF/QgchCuD x7Uyh0ykKSskX0MOy2FRdezB+3FGzdUqNtC4xpI5H1kTbw6Fab4re0NeXkGyKy+yUCM5 7Tk2lb3Hvkd6RQkLEk8KGa0phSH7d8I6NcpYGbbtUX1Q517jVZuQj3g774pHEMQ1HV+D 22NL2KKk6CWcGxCWpIx37bd//hev2PF5f0d12uw8J4SD9/P6qGtPDPcu9LcY5K2sEpU3 atkw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=gUBAjen9; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Thu, 13 Oct 2022 11:39:49 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:39:48 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:39:44 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 07/21] PCI: tegra194: Disable direct speed change for EP Date: Fri, 14 Oct 2022 00:08:40 +0530 Message-ID: <20221013183854.21087-8-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT098:EE_|BL1PR12MB5302:EE_ X-MS-Office365-Filtering-Correlation-Id: 15b41eb3-eaff-47ff-e793-08daad4a5541 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This leaves the speed change ownership with the host. Signed-off-by: Vidya Sagar --- V3: * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 897e2a22bcd3..dff38f73d9a7 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1929,6 +1929,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) reset_control_deassert(pcie->core_rst); + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_SPEED_CHANGE; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + if (pcie->update_fc_fixup) { val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; From patchwork Thu Oct 13 18:38:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2311 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp428949wrs; Thu, 13 Oct 2022 11:53:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5QKNlc547nDUkQHYlkAN0tu3bHuGu5KeoaQfK96GIX0/y5LwEiVRQy0lT1AKSrAHD9wxXD X-Received: by 2002:a17:903:230b:b0:17e:ca9:6b9 with SMTP id d11-20020a170903230b00b0017e0ca906b9mr1382237plh.146.1665687198320; Thu, 13 Oct 2022 11:53:18 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687198; cv=pass; d=google.com; s=arc-20160816; b=F8He8h0e9LhcQhGA4SowIn75t9C5j7Vj9foU/NSLEuL3j/Kn2PPexVFdtChnAYazTI z1VuACd2pvmySFhCaBtBvL7QKBk/6XR/c/sk/jtOTqyB79/mslRjB+ExvrhH5UXkmbiP ct3wG2xCcp1WS4ZJU8iCFr1k7sKUeMGmAwkNPtRwCUynEmkjQil9rcWc3vExNW3jrAvl SknS7A09ed5sQEYcEYSiTqBd888HUC1KwH6SAcIM8ydrk02vbHbHnH8TZjx84W6LtlrQ A3lQm/fjp6Y4eVBRzj7JYlEBfQEgnLyILTX6JYqzqBJWyN4zy+zrfKu7QpI6QO4HN7uU aNwA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=1h7DH9QivaaRrlV63quENGYaC9GelpiOJdLiPP0ha7o=; b=YnkFQ7zDCprjRH+AzJ+B/VWgGNltm5yTtaCWZbbJGwVllxLKDmcslxFmGCe2r/vZbX 9EKO4JddfwQi/F0EVP0cnDgY1aiwtbie2YiLg9ibOPoCVYwKHKRulwgAvQ7aJrLN5xQE lCxIX6lEFXM5+kDclgl6Q1TM06JWr2TzvVqgScJj9rxn5OL03K3jI4XSQiSvHOcYyjGc JS8S2ry+FanIzYORFf8Ws2w/51DfJB9a/QLciWiaku6c2olylNvAUmjeV7o9rCL9ELYy +DVEv4LYJDbVo1vLFRfVRtKzsDSV0l5RsLsCr1BN+7ve1faGQiL9OLoNURynphmyt5Ip AEeg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=AOk5Cwuh; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:06.9033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df9accda-60ec-4ee7-375d-08daad4a59d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT076.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7334 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599619977893685?= X-GMAIL-MSGID: =?utf-8?q?1746599619977893685?= Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change to Gen1 during initialization. This helps in the below surprise link down cases, - Surprise link down happens at Gen3/Gen4 link speed. - Surprise link down happens and external REFCLK is cut off, which causes UPHY PLL rate to deviate to an invalid rate. Signed-off-by: Vidya Sagar --- V3: * Removed "Reported-by: kernel test robot " based on Bjorn's review comment * Reworded the commit message V2: * Addressed review comment from test bot and Vinod drivers/phy/tegra/phy-tegra194-p2u.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c index 1415ca71de38..633e6b747275 100644 --- a/drivers/phy/tegra/phy-tegra194-p2u.c +++ b/drivers/phy/tegra/phy-tegra194-p2u.c @@ -15,6 +15,7 @@ #include #define P2U_CONTROL_CMN 0x74 +#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE BIT(13) #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20) #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0 @@ -85,8 +86,21 @@ static int tegra_p2u_power_on(struct phy *x) return 0; } +static int tegra_p2u_calibrate(struct phy *x) +{ + struct tegra_p2u *phy = phy_get_drvdata(x); + u32 val; + + val = p2u_readl(phy, P2U_CONTROL_CMN); + val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE; + p2u_writel(phy, val, P2U_CONTROL_CMN); + + return 0; +} + static const struct phy_ops ops = { .power_on = tegra_p2u_power_on, + .calibrate = tegra_p2u_calibrate, .owner = THIS_MODULE, }; From patchwork Thu Oct 13 18:38:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2321 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429616wrs; Thu, 13 Oct 2022 11:55:03 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5dV9Akbstdm5PVZ2dtyvLSttAfaqCsR59RBzwH/T9MrFi2A/mUTAnTYNmoTwFidqG/AkoS X-Received: by 2002:a63:1e05:0:b0:451:31d0:8c0f with SMTP id e5-20020a631e05000000b0045131d08c0fmr1106815pge.227.1665687303304; Thu, 13 Oct 2022 11:55:03 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687303; cv=pass; d=google.com; s=arc-20160816; b=QEJ5qVZyu5T9dGi90mZ2/9ft3fkqWmmgzSxK+kkCa4A9umij5MD40gzWlxYPFIxyKk 02HZ9ml4geeqVOd6K4XJOt312cBpD5GD/QWGglMiBam+jBU4n6xliMJG9rrGMO0nK1mW QkfjhtPqyQeeGSEPmLxJfTXsI3jxvdg7XwU7rmYS2BxuzfrcZdqYXmBuPLLHDunQF6RL gVM3pReeAU1Mjy4O37bhQegSZqD6oS3DhnHBHPelUJnvX1xRIrax3uEKD0xUuFLFnt7U EIHV2pFoh/Rvjn/L5Uo+E0V4yOPaaE1p66Qxzu0KnpY9x+jaYpIVLm7xGnxbO8GH9EAH QNpw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=AEfQavBN7MZ0wUAhnJBthx7U6nJZTglMIirSa0jSIYU=; b=IFRglW61ggQtFMhd0Vs5KWzPyfqjbUkWrbSgrTO93j5X9cGolmLCIo6Q4B51hNrlRJ QD2/ay1sVqcHwM2MbFbRE/auIB1XzLEFnQ+vSQQSmuGUXMcLJLrXFrWkO87FTfiO9ae6 mDzA4IK4aOrUod3769rxB/1iKpvzUixRB8fXGGdxoeatICcrRac4+MjCUTLBrWoKmriJ LON/GomHkwWevjuSv8GjFWhCB9ngSulOrhFJ02L+HdmsA/+OboiKiOu/yn3BUiFrWWWs 6PTnP86X4my1cB+8txQrjuR09bNbwKUhoOpIQW4IwtRwvbkc2RzX0AModbiPsHcrqw2i OeiA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=dhmsjTfg; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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This helps to reset stale PLL state from the previous bad link state. Signed-off-by: Vidya Sagar --- V3: * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index dff38f73d9a7..910dc6c2154e 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1130,6 +1130,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) ret = phy_power_on(pcie->phys[i]); if (ret < 0) goto phy_exit; + + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) + phy_calibrate(pcie->phys[i]); } return 0; From patchwork Thu Oct 13 18:38:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2318 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429543wrs; Thu, 13 Oct 2022 11:54:52 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5Gn37wi4abKkcfU80QY4+zalMPYF6OhxqohYCZVbU6Xg+di6avKohp4D9oLKPvOYZRfUSF X-Received: by 2002:a63:91ca:0:b0:460:c57f:9d8a with SMTP id l193-20020a6391ca000000b00460c57f9d8amr1151928pge.400.1665687292093; Thu, 13 Oct 2022 11:54:52 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687292; cv=pass; d=google.com; s=arc-20160816; b=am/Fd+lwhR7fntUK+Gj39eq/XhgT5GEGLntPKwf2etTOgk7sD0neq0FUECuMvu9P7u sGj3BHaA5Bo4hIwptO/NIEaz8wzjFX2PcTHymz9ybt5HJJtnDU1iTSgXdp5Z92JZEa6d wK/eN6snYeu6dZ5hiD/AtEqSaMCw3pqY5+l+x2zaBsvExNeTLBZQBOwOcOJgLo/YhlG7 Y5GvCuCIJD/jP5nDPtAGbzAZPIg1mJnagE5Tq+dV2HPGsidzlPtqSrRGDodshDQbqqca E5JtMUhiVPD+CEYlO/FO04J3lSUYoyNae5RXpc9nO6OsFnhMN7SfgsdktOyN95FnfziN aJ/A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=7weGrSIDLBM7TO9gaN5MsLe4MAx+Wl+GvpEGP4EWS6c=; b=VQQSLOoWwGRAUpKZhrxc6/VJyXsxYVZuGY68ShlTiT1nESYNKk/DeMiDZNSv0Y204+ DKTDhjsSBLtzVn6T6ZJU8H6NAmo0/E/2wAVslL4MAeRxJC4Tog/1dwld753rgtEAutzT kNCoLssYHgsR3peFYUYN+jJvWASfGdvZfcyJspQWULCNgewHvXKiIr07lU/Z1rPdwNjB VnqQ4+FiWuvBbcDufAN5A3An6tXNc4GIynXFwzJ6Gs58M1M3zNxDSfBpEGRlr5bzbWf7 HaDPfH61ISayEHXbhOfCVA7DtfhdWhzSwqQXPVmDkQTkysl9IrwHF2tU/wnZQKeqxE3G f9Wg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=oh7FAcE6; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 910dc6c2154e..7820bf4b9786 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1770,12 +1770,16 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) { + struct dw_pcie *pci = &pcie->pci; + struct dw_pcie_ep *ep = &pci->ep; u32 val; int ret; if (pcie->ep_state == EP_STATE_DISABLED) return; + dw_pcie_ep_deinit_notify(ep); + ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) || ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) || From patchwork Thu Oct 13 18:38:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2317 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429502wrs; Thu, 13 Oct 2022 11:54:45 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6fZIBGBLQLZaXk3FQV4Wzpf9mf6PdMvJfEl17UT0N5vi4ociaUXRo/H0XFO23OIvy+Jr7d X-Received: by 2002:aa7:9397:0:b0:562:cbf1:1186 with SMTP id t23-20020aa79397000000b00562cbf11186mr950715pfe.5.1665687284898; Thu, 13 Oct 2022 11:54:44 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687284; cv=pass; d=google.com; s=arc-20160816; b=Y+YKJqGZMmuAWzL5WmrNGki0BsB3sPEt/NzKi7HWRwUu9j7vxPWpC5Q8zzx4BoRBe1 2+CueM4MrVZmFJw1qhc7l169Z6N8shsj0JPxyPo3D9GUsqqLJQkAm1Ply6jOGbX8EDoN l+2X9GWpsb/t5kZsph2ZgG7AGh8T13Vw/1gRg97FanU+p6P87HCEtMlOAxL6DHjlCx4G lu92ExfQD3RQ5arZS52RllPLhydevYEzjJI7iAlowjqRaWrfutkas+DpT4AJEhGHaX2b wpNMSz4ea+VKhdMzynzB1UgL8/rMxMC/hzT8cQbji9wMvXr2vKfyk16sBgxscIJikYpX ETiQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=xVuYUqRhNPYBMdQehhp7uCUQLfpn9tioYb4AOYBLaCo=; b=YVC4nAzqu8lLflRIBEkU6zrfrPXrFYi4TNyu6GA3zNNlLGJYydhOCPqeoE+SvZnlHR 3UDfBmo4/7IyHrea00h7L4I30+dbkYO6rJYSWbiCbzXAMUeh8FqItEYmeCIDnpoKAdHZ iTkuNHFLHhKKwMRIvVMxIcdmORuBDEQdbOxJBAPfAY05FE5w5I75pdr5t7hDWpSFW7cX JYne9wPaM/Mi8n4Mw3P+weNdXfOAPxkKDx9+jQ4GuLwHwNnpKe3ElPVYXEvYsrJBAOaO pK7P9/2MPrVruq7gqQRqPWlkWFxFyu0EQnFepLogl+MWohbibN/NzPYQefiM8Ro22sxS tWeQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=XfEm2AaN; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:25.3635 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a27a0a5-6cfa-41e7-6a96-08daad4a64bd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5363 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599710330079225?= X-GMAIL-MSGID: =?utf-8?q?1746599710330079225?= Tegra PCIe endpoint has a common interrupt that notifies hardware events like link up, LTR send, etc. DMA completion event is also notified over this interrupt. Remove IRQF_ONESHOT flag from interrupt registration and allow DMA driver to share this interrupt. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 7820bf4b9786..786e5d5f43b9 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2354,7 +2354,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) ret = devm_request_threaded_irq(dev, pp->irq, tegra_pcie_ep_hard_irq, tegra_pcie_ep_irq_thread, - IRQF_SHARED | IRQF_ONESHOT, + IRQF_SHARED, "tegra-pcie-ep-intr", pcie); if (ret) { dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, From patchwork Thu Oct 13 18:38:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2320 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429603wrs; Thu, 13 Oct 2022 11:55:02 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5fZNpUxbtH1qp0RJM2awrnLT9orW7ARM7rgk7JbVFlDYxfkBScoLPQDKQj+iCcfR4pqwQ6 X-Received: by 2002:a17:903:2286:b0:182:2f05:8abb with SMTP id b6-20020a170903228600b001822f058abbmr1158306plh.14.1665687301901; Thu, 13 Oct 2022 11:55:01 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687301; cv=pass; d=google.com; s=arc-20160816; b=OmD/LDvuOp0hCwkz445XT9ZQASQLbQXFJvN0JkjM5QmGmROdRyhM/Ou9ChphsxMtzK t4lAPWSb6KofW7HNzrFUS/SheYsqjb/+IA5/cRTwxjxOZQ/U9NGwkEN6d8/QH2wBUTMo GNkGjsbxnk+Xxpj6QwWvUIno9m+fNQdbTJLgghyi4RDK7iR+0Ac0jUuZFavLKKxTkfnS QEiZGiccW3eXd+LFvtx7Ucb7g1seExKViRL6a/HTnWP1HqshxDIrnArlL+0uWaoJ2NLA 75aJ1jnajJ/kfAdoTYpbbXjUXTx50ZohIM5gngsVUA7matbMWnuVjWVe3nGKLYjEBRYe 2LvQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=77XraY8HtmI9RvcMC5QA1FxyGab/cPTg6lOI+Whf5qo=; b=GV3eMluZITuiOw9H0QR5BKuFERuRQDJa0N09JVXa0Pn6sO4IJCseAqFS1V1jagrcLr kIGmxTdqpe97sWY4KjQCRhDaoxYMrpJyN6qUA+iJZ8+XLYTl2xUz9iouhRQagHepOuJt SbWUSJT7NG/iWCkB12d9wRfyzvZ4DAmoZzG/wHDP/pLqOQ2Qph0nHFV3grd5/TUbd8d9 DYebh1drwwxY1HZHmCFRu1iRP5PEORNYNfck0vrkILsaE6bw9NRwke/rAxIKo9ppeNOP wMyqamzYkbIcPNOYaS4eNLCnMdi+6+Mv5ojzphiZLhYAyJklwLiYVInsx/XGXHxilwVE harA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=oXBcCauq; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 786e5d5f43b9..a1c3481585c9 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -94,6 +94,7 @@ #define APPL_INTR_EN_L1_8_0 0x44 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2) #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3) +#define APPL_INTR_EN_L1_8_EDMA_INT_EN BIT(6) #define APPL_INTR_EN_L1_8_INTX_EN BIT(11) #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15) @@ -552,6 +553,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) spurious = 0; } + if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) { + status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0); + /* Interrupt is handled by dma driver, don't treat it as spurious */ + if (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK) + spurious = 0; + } + if (spurious) { dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", status_l0); @@ -781,6 +789,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct dw_pcie_rp *pp) val |= APPL_INTR_EN_L1_8_INTX_EN; val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN; + val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; if (IS_ENABLED(CONFIG_PCIEAER)) val |= APPL_INTR_EN_L1_8_AER_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); @@ -1927,6 +1936,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN; + val |= APPL_INTR_EN_L0_0_INT_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L0_0); val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); @@ -1934,6 +1944,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); + val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); + val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; + appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); + reset_control_deassert(pcie->core_rst); val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); From patchwork Thu Oct 13 18:38:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2322 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429724wrs; Thu, 13 Oct 2022 11:55:17 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6c/EnjDqTHbTzm6p8dzPqMqZj0CXfJD+rbL5DHDm9jfpxUvPTtRfLKh0dIlXylg/tTQeZ9 X-Received: by 2002:a17:902:6944:b0:181:898b:6440 with SMTP id k4-20020a170902694400b00181898b6440mr1442669plt.78.1665687316905; Thu, 13 Oct 2022 11:55:16 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687316; cv=pass; d=google.com; s=arc-20160816; b=yB1WJ0lDOGVMkCekKTYhWkDy4bpHDXgBo7xtAMdny/rEHGN75Ail6ZL6ZBA1yhtuMm hPBMAa7URneIXpKIOMSqbLJfqRC5tvDiRdXUbSE90dbGz4wJocTvXQieWw6/q05Cux+M YadSuerMmhH+uNT199nuh0sEjFBtqKHL686kmhWMvXE21wnvkI5tBwi8OiJEZtgvPIYO uJEP1lRZj7jQpmtQ0atbTFD6XhUXX5lijXN8QWw331abimP9vcS0dv5KAG2RRMpcGMCM D0WqRXn+V9PnRNjDnnKKLIXK0S6e7pSDSnMJtCsD/dtJnnllekFHborBonYExC+Kb3zV SiUQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=NVum5g4iSVlMg0X000qp1jZQMVyDsz0ZHu0LASebBOg=; b=zXX9eqsBq5dOsBw/I5a4wrLBVWOhBQE0FZNNJp8plxj2yYXh7V0hu6+2uIaT9FnKsH tC8jz0Mxyg0De1a1cmX/AiuWzxv0QGQ5bOvG+ywb3c0ja5WU9pb5y8IKEbt9+Rj1cHXi dlnFQZo2xxRGjKT0Qw/bVtN3s26kNq+cBx5Sa7eYNt2ezs8itKqho75h2FgbIWeJ/cLb a34eN/5baoykPB30ETICJaTw7UtQahAtKPTqULVGh+7B473EDP2SqitK9VZEtY3jgj5Q MZYQyQ0QroUOTRPvuIfe8mriQ0h0Gjfg3CvedbCorBXCZwWrg4NDJU2iw6TBC7fPQXdi faYw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=osA6MSIK; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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To enable this feature, program the APPL_CTRL register with hardware hot reset with immediate LTSSM enable mode. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index a1c3481585c9..78ee0f713e71 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1913,6 +1913,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val = appl_readl(pcie, APPL_CTRL); val |= APPL_CTRL_SYS_PRE_DET_STATE; val |= APPL_CTRL_HW_HOT_RST_EN; + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SHIFT); + val |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT_RST_MODE_SHIFT); appl_writel(pcie, val, APPL_CTRL); val = appl_readl(pcie, APPL_CFG_MISC); From patchwork Thu Oct 13 18:38:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2334 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp431110wrs; Thu, 13 Oct 2022 11:58:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7dEMMUFaBbjASnlo6ub1/i6hXDwdQ3hZPszT96zf47DfbUjAasuyCvM52oyl8SU2uz4x4e X-Received: by 2002:a63:1317:0:b0:42a:e7a5:ef5a with SMTP id i23-20020a631317000000b0042ae7a5ef5amr1167112pgl.392.1665687508802; Thu, 13 Oct 2022 11:58:28 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687508; cv=pass; d=google.com; s=arc-20160816; b=Bhq0hD+25gzaqhu4xiRT7S+BluxZDlyxPpDfPV9JV37sIvtjTHm/bCcXxshmmr/xLu 9q/jGzaDZQSdBMstkO6D6qxkjhINw1mc7hZ2ReRlA0ub5HcIrqKzbRxf4QCQheoNlIF5 f1T+oIwhVFEmlXNLdncIhpU0USIZyARMB3qSV5H0D4he+kY0WHDQlygDYSf5xeY7i0k0 q8C8shkgloxvfUoA3kOxfZerzwejsuGZ/AfQKsT2xXM5rq0e9CFSquQASKCfaaustuBi 9H7UsooI+ee5rfkd3O41ncOKLK+6ERvXSAI7zOGBkvteN65m5scwT0I+FWHU+egvBQaM F2sw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+bXebElS7MWyWIU/lLGwPuIvaTTVF7LsfxdEit/+aa8=; b=E/NA+uBhGWdQNZ5xuG8RF9Zb37WhAStpw9mGFuPeL2WFpZMp4BlFxDGWHM0rp41yA6 iBIlgKSgKZ/tELurgUeHYZKeJGy89m57zCouNXv4R8US7Xb9IlQ4gqQreIBDbd44YSp1 2JjoZpNXIjtAfQtJKeYVJv+0+n6V/kQt8KrX1d8NRBLsVWljy0GKXWCdjZTFMStPhStP YorFAHljwFWAUHEA19M4BRNMEvMEwxadL3gvHdWfY6ADWwYvea/MFeypXwKKoQ7UtW8C Kku6ykgOKs2acNU8oH6t0QNTIWATkOAMhQV0byQf3ECe0srHraLvKTZPH6XDPxY7FIk8 42Lg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=r0iHytgO; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Thu, 13 Oct 2022 11:40:36 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:40:35 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:40:31 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 14/21] PCI: tegra194: Allow system suspend when the Endpoint link is not up Date: Fri, 14 Oct 2022 00:08:47 +0530 Message-ID: <20221013183854.21087-15-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT027:EE_|BN9PR12MB5147:EE_ X-MS-Office365-Filtering-Correlation-Id: f5492732-131d-41d9-da2f-08daad4a7193 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PCIe link is kept in L2 state during suspend. If Endpoint mode is enabled and the link is up, the software cannot proceed with suspend. However, when the PCIe Endpoint driver is probed, but the PCIe link is not up, Tegra can go into suspend state. So, allow system to suspend in this case. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 78ee0f713e71..e6fd713e9868 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2425,8 +2425,14 @@ static int tegra_pcie_dw_suspend_late(struct device *dev) u32 val; if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { - dev_err(dev, "Failed to Suspend as Tegra PCIe is in EP mode\n"); - return -EPERM; + disable_irq(pcie->pex_rst_irq); + + if (pcie->ep_state == EP_STATE_ENABLED) { + dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed"); + return -EPERM; + } else { + return 0; + } } if (!pcie->link_state && !pcie->slot_pluggable) @@ -2448,6 +2454,9 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) { struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) + return 0; + if (!pcie->link_state && !pcie->slot_pluggable) return 0; @@ -2463,6 +2472,9 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev) struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); int ret; + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) + return 0; + if (!pcie->link_state && !pcie->slot_pluggable) return 0; @@ -2495,8 +2507,8 @@ static int tegra_pcie_dw_resume_early(struct device *dev) u32 val; if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { - dev_err(dev, "Suspend is not supported in EP mode"); - return -ENOTSUPP; + enable_irq(pcie->pex_rst_irq); + return 0; } if (!pcie->link_state && !pcie->slot_pluggable) From patchwork Thu Oct 13 18:38:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2316 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429488wrs; Thu, 13 Oct 2022 11:54:42 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5Zenzluj+Sls+JaNBxovjdaCS38sM1HDEhG7epZ1964M1c8tW6EZrRKaGOhonwy/1PS1te X-Received: by 2002:a17:902:ebca:b0:183:d123:e2a7 with SMTP id p10-20020a170902ebca00b00183d123e2a7mr1292843plg.105.1665687282188; Thu, 13 Oct 2022 11:54:42 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687282; cv=pass; d=google.com; s=arc-20160816; b=dfmrFmWmA1cd4rzGeisexrKfTj9fXVkcMBBh3T5zmuTGle9iXhoWOASz45R7KHMQXC GB3jV7Al3CR5yUJAnCRIo+HA+QrQ4aZ6a7+i5UNb9AnHmGmhIBR+xH5oSjRQWOMncl9a FEaJ59P/CFO5uh/ml8LenNqLjYedM1nx1d532GljRRbPhzyx+St5gFQ30SRDAjShN6Ol nl1ELAQ2JPdW+Uky02KoK3W2p6W/X708vx7Ak6Xew9JPBwZrs0BHoJRFvIgGyJP6uJg5 /br14pi0je3eO2Cjmw0YKZU9ULYOQau1OUBPR09tIA2Wvo4bMajDsZLyw8iRNMSo11kB hQiw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qxhMeYnpGTaigWSLa7nBbJua/yYgWcM6sOMyjZ7BhdQ=; b=HTd/YkFb/bYONsaLOcx0jZvoSzIrEZO5MdSBtqAywMTzNOQtDL3EVA9zu+UvMWMb0q KiUVPU35K05AyPAd5bcOqzDjFGby+ckBRKSQghriCnsDes3gdU8a17O9TtX7BIMb5GzH d+Oa4Sdcinv+PtN10vPAyIroO1Fq4r6k5fcDEV1OPEt89gHk1U7diy8EWSd5jtaOXnGc UPK9h5D9cQwiD7Kb3i7SJjeOnXZZAt2BuTJOB3zKPuaWkyzI5k1Ye4NrRJk5WyFqJ5Mm LFj4+kfH54QhWK2qYmm16CAzxmsjqlRVSnn1yvZD1rwDjdWraHrEj0gHfXbYEqIi3SFY xRiQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Aexbpkln; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:48.2339 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: febfad2c-a646-48ad-0091-08daad4a7258 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT081.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6087 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599707833334814?= X-GMAIL-MSGID: =?utf-8?q?1746599707833334814?= When Tegra234 is operating in the endpoint mode with L1.2 enabled, PCIe link goes down during L1.2 exit. This is because Tegra234 is powering up UPHY PLL immediately without making sure that the REFCLK is stable. This is causing UPHY PLL to not lock to the correct frequency and leading to link going down. There is no hardware fix for this, hence do not advertise the L1.2 capability in the endpoint mode. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index e6fd713e9868..d592cf68b02c 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -246,6 +246,7 @@ struct tegra_pcie_dw_of_data { bool has_sbr_reset_fix; bool has_l1ss_exit_fix; bool has_ltr_req_fix; + bool disable_l1_2; u32 cdm_chk_int_en_bit; u32 gen4_preset_vec; u8 n_fts[2]; @@ -1967,10 +1968,11 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) init_host_aspm(pcie); /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ - if (!pcie->supports_clkreq) { + if (!pcie->supports_clkreq) disable_aspm_l11(pcie); + + if (!pcie->supports_clkreq || pcie->of_data->disable_l1_2) disable_aspm_l12(pcie); - } if (!pcie->of_data->has_l1ss_exit_fix) { val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); @@ -2589,6 +2591,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = { .mode = DW_PCIE_EP_TYPE, .has_l1ss_exit_fix = true, .has_ltr_req_fix = true, + .disable_l1_2 = true, .cdm_chk_int_en_bit = BIT(18), /* Gen4 - 6, 8 and 9 presets enabled */ .gen4_preset_vec = 0x340, From patchwork Thu Oct 13 18:38:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2331 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp431007wrs; Thu, 13 Oct 2022 11:58:11 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6BLwU1b5ZOCbGCE/BEby67oM2uyW3dQwiDXa2/Mh98BAJB94fTl4XxezmlaXVNIG+sgOeR X-Received: by 2002:a65:56ca:0:b0:439:169f:f027 with SMTP id w10-20020a6556ca000000b00439169ff027mr1120731pgs.580.1665687490912; Thu, 13 Oct 2022 11:58:10 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687490; cv=pass; d=google.com; s=arc-20160816; b=DsxcllKlLdMxhHa1dYSVeRLy2iHn1rXe4Q44lebxMR/8PToyfYv59W6XennWNf5Fx0 FiRzuaEVGjFbxKZCktmmptrZ8dSklVtXgXg0Larixi7pBUhs7jxTQRI0BcJpSRgM0cJi Gg0lk0+ZtTocIe+AYt7wViym2+ColAB4b0BEy3wezTCMCu+pUr+AvU2qKvFCV4ufXffy qWYhzRpBvep11aERwlivBxIG8QgzmnKdfqJuYJC/ROrSDFrVcSjiBv8TZ41tbiAHRyvH qlqKt+F4yrZiptgGBJSrRV8XfNfIKA2uFR5SnlmPaGR/xI+er4F9gRUJiOpFwGnZSooh R3Pw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=do7jFBBJDjTpxwmlaFOhTACn7os+1N3Tp0MI+EIdnpo=; b=poOK4jehkhI8FvD/jQaXASj5X3Q5T3xY79MVH1PrqbWvvBu0A1w3xkipjPZqxWLIHG dpGVqeo7FakM201/dMC6tdurO8tdj5BnrpgMktr0zdhJyCT5ui8nGuhKkpM37SEt4fGb Xq3BN2TqYWMZt3qkZZmR96mrQgdMbduaknC87lq1mB+G7C3u1C3eIa1bU6UUeV20RLxp 0QAZEYTDEF/mVwU1V73JqlCrY7tniAi97AtsI+r3HPgvhbr/WeE4JVHXyldZOT07SI4N 1wa6w0r+w8hpGAxBkqLsUYU4sv5EX5bVflBR+/ASVVt1AGcKrAB/cGmdcGAT5DdJkUzg Eh3g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=IHW+LJJL; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Set snoop & no snoop LTR timing and LTR message request before PCIe links up. This ensures that LTR message is sent upstream as soon as LTR is enabled. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index d592cf68b02c..23ca97401339 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -493,11 +493,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) if (val & PCI_COMMAND_MASTER) { ktime_t timeout; - /* 110us for both snoop and no-snoop */ - val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ; - val |= (val << LTR_MST_NO_SNOOP_SHIFT); - appl_writel(pcie, val, APPL_LTR_MSG_1); - /* Send LTR upstream */ val = appl_readl(pcie, APPL_LTR_MSG_2); val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE; @@ -1951,6 +1946,11 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); + /* 110us for both snoop and no-snoop */ + val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ; + val |= (val << LTR_MST_NO_SNOOP_SHIFT); + appl_writel(pcie, val, APPL_LTR_MSG_1); + reset_control_deassert(pcie->core_rst); val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); From patchwork Thu Oct 13 18:38:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2323 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429810wrs; Thu, 13 Oct 2022 11:55:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4anuc/Je57jm7PYBj8NAnsTWceFCClAhsgvdaw6LY+k5IwyaZRJf9ZHxEb5PPBffFlqM2U X-Received: by 2002:a62:1bd1:0:b0:562:a99e:93cd with SMTP id b200-20020a621bd1000000b00562a99e93cdmr930205pfb.21.1665687329729; Thu, 13 Oct 2022 11:55:29 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687329; cv=pass; d=google.com; s=arc-20160816; b=C3oA0gWD8e0ysPc9DEZSNPWtQqRVLWp30jXnuQmmW15Ba+Y6JrJnsDwngDsvB2T2QQ 79mRwEM/6g0vuc/s0nuhztajIyz89c3mqoSzVBOex+2NXKhGa05KRMlWXE5VAJ/GzQqS WrgkNO8Cgo1ur4h4Ur8GLn3p+B5y0y/KEafao2rlE/DCLcJNUmCKuEV+CJ0TX0RaTqLJ M5kCWGYkJUok1UinnC38oXtImOr20nTUq8mDXCwLQ2f4DNvV1fUYo5nJEmdxrLWTlLrH 6WXoM2Q97pXbmxA/MsqD7EwS5cOMeGIiuzz0K5wGZs18t5o3JxmiZAGzDXsPCdmPuaVT oZ/g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=aH5YgaTVUz7eF4RuTjJb3wToT5WFijNGSYa0v+Q8n9k=; b=hpePZcmfmRd4lVXyLNkkFIl3QJercTEW4TrxkN1q+3DvMYSkvb1kSMtggXxbsmzZJV EACQVb/GYJZ1tkoLMOF3ILzBy0coxSiwzfkLL7MOD5jdGRwOqKdGgQ0z7JtsQ5ppJtqv 4CrosFtOZZ4UEZL08XRZFhKChZ/+0dWpIKluXdWxfnCoD3MUClw6JQeKG2BV1EdYeoyc zmwhgtVdlZRKpoeI4ZrygqOOrfKWJZFQcrl3fTMRmNZR+LTRr6qdsWW0d7GBvakHaR1G RHzG3jEBVgQoO3Iy6+Du9x4lu97elDshqNEjHOKoC5nXetkMD7xYM6nqS67J0LHljqPG 4azw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=APXpY6Aa; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Thu, 13 Oct 2022 11:40:55 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:40:55 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:40:50 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 17/21] PCI: tegra194: Reduce AXI slave timeout value Date: Fri, 14 Oct 2022 00:08:50 +0530 Message-ID: <20221013183854.21087-18-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT106:EE_|SJ1PR12MB6123:EE_ X-MS-Office365-Filtering-Correlation-Id: e6fd0f5b-70bc-41f4-0daf-08daad4a7adf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:41:02.4938 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6fd0f5b-70bc-41f4-0daf-08daad4a7adf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6123 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599757207222161?= X-GMAIL-MSGID: =?utf-8?q?1746599757207222161?= Reduce the AXI slave timeout value to 7ms to be in line with the CBB logic's timeout value and to avoid CBB reporting errors because of no response from the PCIe IPs AXI slave logic for configuration space accesses through ECAM when the PCIe link is down. Also, set the Completion Timeout value to Range-A: 1ms~10ms to be inline with the AXI timeout value. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 23ca97401339..7890e0c0c0d2 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -198,6 +198,12 @@ #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2 +#define PORT_LOGIC_AMBA_LINK_TIMEOUT 0x8D4 +#define AMBA_LINK_TIMEOUT_PERIOD_MASK GENMASK(7, 0) +#define AMBA_LINK_TIMEOUT_PERIOD_VAL 0x7 + +#define PCI_EXP_DEVCTL2_CPL_TO_VAL 0x2 /* Range-A: 1ms to 10ms */ + #define MSIX_ADDR_MATCH_LOW_OFF 0x940 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0) #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2) @@ -922,6 +928,18 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) AMBA_ERROR_RESPONSE_CRS_SHIFT); dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); + /* Reduce the AXI slave Timeout value to 7ms */ + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_LINK_TIMEOUT); + val &= ~AMBA_LINK_TIMEOUT_PERIOD_MASK; + val |= AMBA_LINK_TIMEOUT_PERIOD_VAL; + dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_LINK_TIMEOUT, val); + + /* Set the Completion Timeout value in 1ms~10ms range */ + val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2); + val_16 &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT; + val_16 |= PCI_EXP_DEVCTL2_CPL_TO_VAL; + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2, val_16); + /* Configure Max lane width from DT */ val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); val &= ~PCI_EXP_LNKCAP_MLW; @@ -1988,6 +2006,12 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B; dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16); + /* Set the Completion Timeout value in 1ms~10ms range */ + val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2); + val_16 &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT; + val_16 |= PCI_EXP_DEVCTL2_CPL_TO_VAL; + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2, val_16); + /* Clear Slot Clock Configuration bit if SRNS configuration */ if (pcie->enable_srns) { val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + From patchwork Thu Oct 13 18:38:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2329 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp430253wrs; Thu, 13 Oct 2022 11:56:27 -0700 (PDT) X-Google-Smtp-Source: AMsMyM77I7EhEZD5dfHhh2ZXXiNFXDs867LeQvGHS0Zos+IoLv2q1ZcrakRP5Ajx75ROC+NpLSlm X-Received: by 2002:a63:6c07:0:b0:457:523c:4bd0 with SMTP id h7-20020a636c07000000b00457523c4bd0mr1136004pgc.101.1665687387555; Thu, 13 Oct 2022 11:56:27 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687387; cv=pass; d=google.com; s=arc-20160816; b=Y6fYAqpbb38VSc3NDucD8TLFghnjOKxxDSOIcQYeoKj2m/EIrn09wkgj0DOKA7pkZA 4ho/PZWn1JQuPwLDmflhVmKwKxgRwXMfKviHfrPoMS5vFuwFjrCYV7ovlBjaoRNYmsl9 noKfRDCKJ9tw7P95d8e9XwqzTlpmXdvPw99Pc8FxNJZrJu1yVBSm8WeBlqXJzcPL3cXF uohYsTvcN+PJDmC2Nem0fDWgvkgxmko6Xf6HZet5nHRChTdFiiElCuIoRxP9xFCDur6I w8NAU21VZ1loPMuqRNBJ6MAYa6h8s7Ru83WKCQilYRAu6XvJjoC5xmgsWny+f1zIYto7 g2iA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=vQO+syzulpuiLINlA8pRWfiNhP9XqNn52zizQyJSPbM=; b=u0gNpFsBiel/6kUQj57Hy7DaSxCr852E8+3+QNt+lx0LozUFR/FX5Rhc8QubyXWmvD KhbsM1yjKy6GS73guWelhn29P0kM3uMxBQbHwSr6a/X1YR3EsppN8jVwoTeq2qpSG3bo wHeG1nZP18sEY95IM7tZLaATz1XWXiTRRlE2Eid71AJEmi+57BJstXOan3c5G2DhHtmu Qbx80gsPgCNxxc9nas14oPufIw70vHiMB3bVDDtCb6I+hbJ8a3JykXl5vJloZWBwafQd gwybCQ9/ePaUvQMIfV1rGiIDU6S75NYf8HZo7Kwv02juCOfeI2waARqhAxfgVmH2qJE+ Szqg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=rhiQOvAq; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:41:09.2633 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0345859-7829-4ed5-d5cd-08daad4a7ee0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6179 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599818012830979?= X-GMAIL-MSGID: =?utf-8?q?1746599818012830979?= As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe endpoint device should be in D3 state to assert wake# pin. This takes precedence over PCI Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management which states that the device can be put into D0 state before taking the link to L2 state. So, to enable the wake functionality for endpoints, do not force the devices to D0 state before taking the link to L2 state. There is no functional issue with the endpoints where the link doesn't go into L2 state (the reason why the earlier change was made in the first place) as the root port proceeds with the usual flow post PME timeout. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 41 ---------------------- 1 file changed, 41 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 7890e0c0c0d2..3baf1a26fe68 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1358,44 +1358,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, return 0; } -static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) -{ - struct dw_pcie_rp *pp = &pcie->pci.pp; - struct pci_bus *child, *root_bus = NULL; - struct pci_dev *pdev; - - /* - * link doesn't go into L2 state with some of the endpoints with Tegra - * if they are not in D0 state. So, need to make sure that immediate - * downstream devices are in D0 state before sending PME_TurnOff to put - * link into L2 state. - * This is as per PCI Express Base r4.0 v1.0 September 27-2017, - * 5.2 Link State Power Management (Page #428). - */ - - list_for_each_entry(child, &pp->bridge->bus->children, node) { - /* Bring downstream devices to D0 if they are not already in */ - if (child->parent == pp->bridge->bus) { - root_bus = child; - break; - } - } - - if (!root_bus) { - dev_err(pcie->dev, "Failed to find downstream devices\n"); - return; - } - - list_for_each_entry(pdev, &root_bus->devices, bus_list) { - if (PCI_SLOT(pdev->devfn) == 0) { - if (pci_set_power_state(pdev, PCI_D0)) - dev_err(pcie->dev, - "Failed to transition %s to D0 state\n", - dev_name(&pdev->dev)); - } - } -} - static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) { pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); @@ -1725,7 +1687,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { - tegra_pcie_downstream_dev_to_D0(pcie); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2486,7 +2447,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) if (!pcie->link_state && !pcie->slot_pluggable) return 0; - tegra_pcie_downstream_dev_to_D0(pcie); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2565,7 +2525,6 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev) if (pcie->slot_pluggable) unregister_gpio_hotplug_slot(&pcie->hp_slot); debugfs_remove_recursive(pcie->debugfs); - tegra_pcie_downstream_dev_to_D0(pcie); disable_irq(pcie->pci.pp.irq); if (IS_ENABLED(CONFIG_PCI_MSI)) From patchwork Thu Oct 13 18:38:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2324 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp429889wrs; Thu, 13 Oct 2022 11:55:40 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4HNBCW3lR+WuUOn56pe0NRkNPPdNOQ1K8zjGU+YqH1edFSPM1/XI+oh/v2IBd36NfEicKi X-Received: by 2002:a17:902:7481:b0:180:fde5:98a8 with SMTP id h1-20020a170902748100b00180fde598a8mr1380241pll.81.1665687339857; Thu, 13 Oct 2022 11:55:39 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687339; cv=pass; d=google.com; s=arc-20160816; b=zsj/BV7P5v4s7OoXBgLRFtHjyVL294s6iC/5cCkgBJoy1lDs4I095ppceDtp5p2YAc 6fSzR/ujoj0N5ES+w0nqXD1l1rPyHLdPP325f0DxumLkfdnCdHEiB/o1zDDJkwzk1+ab zHUuQPT79GKZ5kM1gtibsbjnrl0uCyhhl4JZEQB+Zr5ZIYDUEVnvWrTZSI+1+LadZ2/x +zFEznPAuUvLUHuEHAwbxo/khW5UFEhpvIGPDnlI3SA+hBttLUgFJ9V+LyHBUH8vxFco innyecJxs4nhFV4YSwoMWeHv8LNL3b/9Z3lgjGycCtoCYLI6DjVsFsms52wdZtLWceUY cZ2Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Lv0j2URtTMYtnBqq/A4uaetsHamRfZm8w0XaTV8Uimk=; b=k+voFcLvjxej34uZ8L411Z4UhsxEe0YQUZ7gvydM1KN9smfoDC/QzgiTgA8pqy2gXD OElMX9ZL/Tq3XGuqx/0X21o3y0ZsRgS/vHq0zS+2/X1ycCOtDnM9z1We3Xu5C0pPatUU TMU1bBpYCfWSbphnUVqMq8SNDXFkNj4mKzu28A09skP9bW98lroraw6ccorxnHHD6mSS EnehmUWcua8JD0AJFvgipVG+404piE19H54Jii9REHDYe8dSYbyCTSgvrCNJtgy5OXiz vUoZw/f9iNDZ0go5PVNWw9C+i/0Z+fIS7uIn9jI2Znt1UmBcIztBqJhLG1WPlAO5mSml GsZQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Yi0GhQBM; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 3baf1a26fe68..c88c36d85ee5 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2383,6 +2383,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) static int tegra_pcie_dw_remove(struct platform_device *pdev) { struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); + struct dw_pcie_ep *ep = &pcie->pci.ep; if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { if (!pcie->link_state && !pcie->slot_pluggable) @@ -2396,6 +2397,7 @@ static int tegra_pcie_dw_remove(struct platform_device *pdev) } else { disable_irq(pcie->pex_rst_irq); pex_ep_event_pex_rst_assert(pcie); + dw_pcie_ep_exit(ep); } pm_runtime_disable(pcie->dev); From patchwork Thu Oct 13 18:38:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2326 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp430002wrs; Thu, 13 Oct 2022 11:55:56 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7ZqyjfD1SQ43y4Is0uWVembfSJaVbsnpSd/ZL3LuABmMnK8zQ1w/xD8OKZ1lcfO0xCcfxG X-Received: by 2002:a17:906:4783:b0:780:5be5:c81b with SMTP id cw3-20020a170906478300b007805be5c81bmr899751ejc.76.1665687356209; Thu, 13 Oct 2022 11:55:56 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687356; cv=pass; d=google.com; s=arc-20160816; b=a9KWNQqVDhEc+9/7aUE31meg4vwtSxx1rGPWAIACQvymS4vnewROb0HWFV+NPicnyP apDV2z5njmVFdvfpiP2qOr9GcuodzUQgalhObSLH9PNBemA3sWqns9pckXnBCLRKbkvO F/MsGJZfAaKFqRqLpBNH4WHjZtFAR8+nGpmmgfGIARqkXUNKlcwD8K2Xc7dN1AK55clB wcbfzuAKuJxZglvdtUsw0TO/LYexIICS3BEW8O5qVPMpplceys4Jj2Orz9jBPYkIctre EOMuohPijxWDAM9d55yUzgQIR6PC4vHCOC8Ipsn+BLHJ8IzjvMN+pxiTS9lrLm2Nuvmd oZog== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=+OYl6hX3/oChjrgjuOaGFWyc0+88Bn9/AYVGZVWF5mc=; b=G3EAJH3kBY/bMwNXNu/HmxXRvx3w2JORawhCB/T1fdXTc6VFa559C4dCiKTON5xmJb cTT/Qikz0aSwa4UMnSiDZlMqmPpOgxcrSlg7ZoH2FyUzpObAz9rQokXxk93P1+uC5kyO /BQQquH7za4oEX8XfIrlSYxjh96kFXJbnQwsihFvkjsMoXYRwm4j5b2YYVx+jiAydzDa oB+nE+O2pOruGw9biqm+PNirUD8ovX80G8wib/YnWvIiyCIt7MebYveLAkHLrEu1/Ftg vk4UimmBlBx4bYF4NSTR7+vidN6PLHxu6ON5EdNKm7n2yXg5f5ScFO6Vmv1AjFNT7PvV R80g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="QX2O/DwP"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:41:20.7320 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29b66c5d-8da7-4b57-7170-08daad4a85b4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5709 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599785297551222?= X-GMAIL-MSGID: =?utf-8?q?1746599785297551222?= Tegra supports PCIe core clock monitoring for any rate changes that may be happening because of the link speed changes. This is useful in tracking any changes in the core clock that are not initiated by the software. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series .../devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml | 6 +++++- .../devicetree/bindings/pci/nvidia,tegra194-pcie.yaml | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml index a24fb8307d29..7c6900802f04 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml @@ -55,12 +55,16 @@ properties: - const: intr clocks: + minItems: 1 items: - - description: module clock + - description: module's core clock + - description: module's monitor clock clock-names: + minItems: 1 items: - const: core + - const: core_m resets: items: diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml index 75da3e8eecb9..aaaa238e6dc1 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml @@ -54,12 +54,16 @@ properties: - const: msi clocks: + minItems: 1 items: - - description: module clock + - description: module's core clock + - description: module's monitor clock clock-names: + minItems: 1 items: - const: core + - const: core_m resets: items: From patchwork Thu Oct 13 18:38:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 2330 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp430353wrs; Thu, 13 Oct 2022 11:56:39 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4wyebjbExiXAAbWxlH3RJHaGkUp3AqHzyDMUOhHxbdu2sfWvKzF/TmPS16DytWOI7CFgRG X-Received: by 2002:a17:90b:314a:b0:20d:904b:18a8 with SMTP id ip10-20020a17090b314a00b0020d904b18a8mr10560335pjb.96.1665687399038; Thu, 13 Oct 2022 11:56:39 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1665687399; cv=pass; d=google.com; s=arc-20160816; b=jp1D7n1/jrU2RFe1NqaV8jZC6a78kCOGd09ocBPuCe3xS8EburexqU2IgiJh6Fjq/s YVTC4D3HeFMqSM7hlIXnMQFkZl7C5cmE7BlO6OMKbXUdCb6rkwEzk7uid4t6VpVb9NXA owTv1tnzXsFIAQLKldbveOge4Z5VRBvXu1yhHpkLsocCIDiURWUxjtdHYf7FQdrOAJbZ nk0Mah5ExA6ITIcfb0UrSjuu4H7c+NPuCn7DT9a0Gq+OvcXy+jMIvoL0LZUxRowrejrg ByzDFXI87+oUBEMwgu4MRnhoRubiWPJwS6llZqsQrPk53+xraQTmUmCwNVjR1RybeqKD VsQA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=bPsdh/LeAVLGI//ZKIOszKcbprG+fe9y5UUxgVPd5tM=; b=cZPJVJapRoA32HZLZcCXnqgdppCs1Cl5ZPQucffpyNzThKmfZdRjkEPrmPE4LNQ3R8 6b/6geUqD8odQ4xZN5+dJ4Zq550biOojgkdh10XafWDZrivZFOq28g4sWIgZ/fZhxjw/ NuOFsPNF9c4wwRo6x4cPbk0io4MEih18BFpGw6dAVo9wKJrbfKe8IU1GacJyB9Dyntbm CIFFTU8fCq6jpvWa6Yp6NOEBeYoUa0oUIbMIOJelZVUC9bvwA/wL3N267q2gUTpwCg2L j9qh9+fLF0qEtR5J4iTa0eWYoF4mLloMWLiBgvWghcpCw5I7m8MebauFcE45+uUmB9Rx 5mtA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=g0xuRTQ9; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:41:29.8247 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca3fdb91-1640-4f59-1c4a-08daad4a8b1b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6776 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746599830077454559?= X-GMAIL-MSGID: =?utf-8?q?1746599830077454559?= Tegra supports PCIe core clock monitoring for any rate changes that may be happening because of the link speed changes. This is useful in tracking any changes in the core clock that are not initiated by the software. This patch adds support to parse the monitor clock info from device-tree and enable it if present. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index c88c36d85ee5..28512dc60172 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -265,6 +265,7 @@ struct tegra_pcie_dw { struct resource *atu_dma_res; void __iomem *appl_base; struct clk *core_clk; + struct clk *core_clk_m; struct reset_control *core_apb_rst; struct reset_control *core_rst; struct dw_pcie pci; @@ -978,6 +979,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) } clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); + if (clk_prepare_enable(pcie->core_clk_m)) + dev_err(pci->dev, "Failed to enable core monitor clock\n"); return 0; } @@ -1050,6 +1053,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) val &= ~PCI_DLF_EXCHANGE_ENABLE; dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val); + /* + * core_clk_m is enabled as part of host_init callback in + * dw_pcie_host_init(). Disable the clock since below + * tegra_pcie_dw_host_init() will enable it again. + */ + clk_disable_unprepare(pcie->core_clk_m); tegra_pcie_dw_host_init(pp); dw_pcie_setup_rc(pp); @@ -1059,7 +1068,8 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & PCI_EXP_LNKSTA_CLS; - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); + if (!pcie->core_clk_m) + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); tegra_pcie_enable_interrupts(pp); @@ -1687,6 +1697,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { + clk_disable_unprepare(pcie->core_clk_m); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2266,6 +2277,13 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) return PTR_ERR(pcie->core_clk); } + pcie->core_clk_m = devm_clk_get_optional(dev, "core_m"); + if (IS_ERR(pcie->core_clk_m)) { + dev_err(dev, "Failed to get monitor clock: %ld\n", + PTR_ERR(pcie->core_clk_m)); + return PTR_ERR(pcie->core_clk_m); + } + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "appl"); if (!pcie->appl_res) { @@ -2449,6 +2467,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) if (!pcie->link_state && !pcie->slot_pluggable) return 0; + clk_disable_unprepare(pcie->core_clk_m); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie);